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1. 发明申请

WO2018182986A1 PROFILES FOR COLLECTING TELEMETRY DATA 审中-公开
公开(公告)号：WO2018182986A1
公开(公告)日：2018-10-04
申请号：PCT/US2018/022591
申请日：2018-03-15
申请人： INTEL CORPORATION
发明人： CHAYAT, Ronen , CHILIKIN, Andrey , BROWNE, John J. , MACNAMARA, Chris , KANTECKI, Tomasz
IPC分类号： H04L29/08
摘要： An apparatus includes telemetry registers, a memory, and a virtualized telemetry controller. The memory may store a set of telemetry profiles, including a first telemetry profile specifying a collection trigger, a set of telemetry registers, and a telemetry data destination. The virtualized telemetry controller may be to: detect a condition satisfying the collection trigger specified in the first telemetry profile; in response to a detection of the condition, read telemetry values from the set of telemetry registers specified in the first telemetry profile; generate a telemetry container including the telemetry values; and send the telemetry container to the telemetry data destination specified in the first telemetry profile.

2. 发明申请

WO2018026380A1 SYSTEMS AND METHODS FOR DATA SERVICE REQUEST CLASSIFICATION AND ROUTING 审中-公开
标题翻译：用于数据服务请求分类和路由的系统和方法
公开(公告)号：WO2018026380A1
公开(公告)日：2018-02-08
申请号：PCT/US2016/045882
申请日：2016-08-05
申请人： INTEL CORPORATION
发明人： POWER, Damien , MACNAMARA, Chris , VARLESE, Marco
IPC分类号： H04L12/851 , H04L29/12 , H04L12/24 , H04L12/26
CPC分类号： H04L12/00 , H04L12/4625 , H04L45/00
摘要： A Service Routing Agent and methods are disclosed that classify and route data service requests. One embodiment includes a control circuit and at least one orchestrator, processor, and service handler circuit. The control circuit performs a process to: receive a configuration of at least one service handler circuit, initialize a list of service handler circuits and associated applications, program the at least one processor to listen for data service requests associated with the application, receive a data service request, and determine whether a service handler circuit associated with the application has been activated; when the service handler circuit has been activated, forwards the data service request to the service handler circuit, and when the service handler circuit has not been activated, request that the service handler circuit be activated, and then forwards the data service request to the service handler circuit. The Service Routing Agent reports updated traffic statistics.
摘要翻译：公开了一种服务路由代理和方法，其对数据服务请求进行分类和路由。一个实施例包括控制电路和至少一个协调器，处理器和服务处理器电路。控制电路执行以下处理：接收至少一个服务处理器电路的配置，初始化服务处理器电路和关联应用的列表，编程至少一个处理器以监听与应用关联的数据服务请求，接收数据服务请求，并且确定与该应用相关联的服务处理器电路是否已被激活; 当服务处理器电路已被激活时，将数据服务请求转发到服务处理器电路，并且当服务处理器电路未被激活时，请求激活服务处理器电路，然后将数据服务请求转发到服务处理器电路。服务路由代理报告更新的流量统计信息。

3. 发明申请

WO2018156153A1 CONFIGURATION OF BASE CLOCK FREQUENCY OF PROCESSOR BASED ON USAGE PARAMETERS 审中-公开
公开(公告)号：WO2018156153A1
公开(公告)日：2018-08-30
申请号：PCT/US2017/019484
申请日：2017-02-24
申请人： INTEL CORPORATION
发明人： SRINIVASAN, Vasudevan , SISTLA, Krishnakanth V. , GOUGH, Corey D. , STEINER, Ian M. , GUPTA, Nikhil , GARG, Vivek , VARMA, Ankush , VORA, Sujal A. , LERNER, David P. , SULLIVAN, Joseph M. , GURUMOORTHY , Nagasubramanian , BOWHILL, William J. , RAMAMURTHY , Venkatesh , MACNAMARA, Chris , BROWNE, John J. , DAS, Ripan
IPC分类号： G06F1/32 , G06F1/08 , G06F9/50
摘要： A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

4. 发明申请

WO2018125686A2 METHODS AND DEVICES FOR RADIO COMMUNICATIONS 审中-公开
公开(公告)号：WO2018125686A2
公开(公告)日：2018-07-05
申请号：PCT/US2017/067466
申请日：2017-12-20
申请人： INTEL CORPORATION , INTEL IP CORPORATION
发明人： AZIZI, Shahrnaz , BADIC, Biljana , BROWNE, John , CAVALCANTI, Dave , CHOI, Hyung-nam , CLEVORN, Thorsten , GUPTA, Ajay , GUPTA, Maruti , HASHOLZNER, Ralph , HIMATAT, Nageen , HUNT, Simon , KARLS, Ingolf , KENNEY, Thomas , LIAO, Yiting , MACNAMARA, Chris , MARTINEZ TARRADELL, Marta , MUECK, Markus, Dominik , NALLAMPATTI EKAMBARAM, Venkatesan , POWER, Niall , RAAF, Bernhard , SCHNEIDER, Reinhold , SINGH, Ashish , SINGH, Sarabjot , SRIKANTESWARA, Srikathyayani , TALWAR, Shilpa , XUE, Feng , YU, Zhibin , ZAUS, Robert , FRANZ, Stefan , KLIEMANN, Uwe , DREWES, Christian , KREUCHAUF, Juergen
IPC分类号： H04W4/029 , H04W4/30 , H04W48/18 , H04W28/26 , H04W76/28 , H04W12/06 , H04W88/06 , H04W88/16 , H04W88/18
摘要： A communication device can include a processor configured to receive, on a radio channel, an uplink radio transmission in a first waveform format from a terminal device that instructs the communication device to forward the uplink radio transmission to a network access node, and transmit, on the radio channel, the uplink radio transmission to the network access node with a preamble in a second waveform format to protect the uplink radio transmission from collisions.

5. 发明申请

WO2016167915A1 APPARATUS AND METHOD FOR ADJUSTING PROCESSOR POWER USAGE BASED ON NETWORK LOAD 审中-公开
标题翻译：基于网络负载调整处理器功率的装置和方法
公开(公告)号：WO2016167915A1
公开(公告)日：2016-10-20
申请号：PCT/US2016/022572
申请日：2016-03-16
申请人： INTEL CORPORATION
发明人： BROWNE, John , MACNAMARA, Chris
IPC分类号： G06F9/50 , G06F1/32 , G06F11/30
CPC分类号： G06F1/3296 , G06F1/3209 , G06F1/3228 , G06F1/3243 , G06F9/4893 , G06F2209/548 , Y02D10/152 , Y02D50/20
摘要： In an embodiment, a system includes a processor that includes a plurality of cores and a plurality of queue. Each queue includes storage locations to store packets to be processed by at least one of the cores. Each queue has a corresponding state that is one of active and inactive. Each active queue is enabled to store an incoming packet, and each inactive queue is disabled from storage of the incoming packet. Each queue has a corresponding queue depth that includes a count of occupied storage locations of the queue. The system also includes packet distribution logic to determine whether to change the state of a first queue of the plurality of queues from a first state to a second state based on a total queue depth that includes a sum of the queue depths of the active queues. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，系统包括包括多个核心和多个队列的处理器。每个队列包括用于存储要由至少一个核心处理的分组的存储位置。每个队列都有一个对应的状态，它是一个活动和非活动状态。启用每个活动队列以存储传入的数据包，并且禁止每个不活动队列存储进入的数据包。每个队列具有对应的队列深度，其包括队列占用的存储位置的计数。该系统还包括分组分配逻辑，用于基于包括活动队列的队列深度的总和的总队列深度来确定是否将多个队列中的第一队列的状态从第一状态改变到第二状态。描述和要求保护其他实施例。

6. 发明申请

WO2022093439A1 TRANSIENT DATASET MANAGEMENT SYSTEM 审中-公开
公开(公告)号：WO2022093439A1
公开(公告)日：2022-05-05
申请号：PCT/US2021/051297
申请日：2021-09-21
申请人： INTEL CORPORATION
发明人： VEDANTHAM, Sundar , LIN, Bin , PATHAK, Pravin , CHEN, Ximing , MACNAMARA, Chris
IPC分类号： G06F21/60 , G06F16/27
摘要： Examples described herein relate to a manner of provide a time of life of data. In some examples, data and control parameters are received from a data source. The data can be encrypted and stored. In addition, at least a portion of the control parameters can be stored into a distributed ledger. In some examples, the portion of the control parameters include an indicator of expiration time of the data. In some examples, a data header for the data is generated, where the data header includes an indication that the data is subject to a limited life span and a data identifier. The data header can be accessed with a request to access the encrypted data.

7. 发明申请

WO2022066339A1 CACHE AND MEMORY CONTENT MANAGEMENT 审中-公开
公开(公告)号：WO2022066339A1
公开(公告)日：2022-03-31
申请号：PCT/US2021/047395
申请日：2021-08-24
申请人： INTEL CORPORATION
发明人： CHILIKIN, Andrey , KANTECKI, Tomasz , MACNAMARA, Chris , BROWNE, John J. , DOHERTY, Declan , POWER, Niall
IPC分类号： H04L29/08 , H04L12/24 , G06F12/0862 , G06F1/28 , H04L12/26
摘要： Examples described herein relate to a network interface apparatus that includes an interface; circuitry to determine whether to store content of a received packet into a cache or into a memory, at least during a configuration of the network interface to store content directly into the cache, based at least in part on a fill level of a region of the cache allocated to receive copies of packet content directly from the network interface; and circuitry to store content of the received packet into the cache or the memory based on the determination, wherein the cache is external to the network interface.

8. 发明申请

WO2018004944A1 SYSTEM TO MONITOR AND CONTROL DATA IN A NETWORK 审中-公开
标题翻译：在网络中监测和控制数据的系统
公开(公告)号：WO2018004944A1
公开(公告)日：2018-01-04
申请号：PCT/US2017/035144
申请日：2017-05-31
申请人： INTEL CORPORATION
发明人： POWER, Damien , MACNAMARA, Chris , MURTAGH, Sinead , HUNT, Laura , LOUGHNANE, Gary
IPC分类号： H04L12/725 , H04L12/813 , H04L12/26
摘要： This disclosure is directed to system to monitor and control data flow in a network. At least one device in a core network may be responsible for charging functions related to the data requests. During certain high usage scenarios (e.g., emergencies, special events, etc.), it may be possible for the charging system to be overwhelmed. For example, a policing system may be implemented in the core network to at least manage the flow of requests to the charging system. The policing system may monitor and control request flow to the charging system based on at least one policy. When a request is determined to violate a policy, the policing system may take corrective action to prevent the charging system from being overwhelmed. For example, the policing system may block the request, divert the request to another charging system that may have available capacity, etc.
摘要翻译：本公开针对用于监视和控制网络中的数据流的系统。核心网络中的至少一个设备可以负责与数据请求相关的收费功能。在某些高使用情况下（例如，紧急情况，特殊事件等），充电系统可能会不堪重负。例如，可以在核心网络中实施警务系统以至少管理对充电系统的请求流。警务系统可以基于至少一个策略来监视和控制对计费系统的请求流。当确定请求违反策略时，警务系统可以采取纠正措施来防止收费系统不堪重负。例如，警务系统可能阻止请求，将请求转移到可能具有可用容量的另一个收费系统等。

9. 发明公开

EP3283959A1 APPARATUS AND METHOD FOR ADJUSTING PROCESSOR POWER USAGE BASED ON NETWORK LOAD 审中-公开
标题翻译：基于网络负载调整处理器功率使用的装置和方法
公开(公告)号：EP3283959A1
公开(公告)日：2018-02-21
申请号：EP16780426.9
申请日：2016-03-16
申请人： Intel Corporation
发明人： BROWNE, John , MACNAMARA, Chris
IPC分类号： G06F9/50 , G06F1/32 , G06F11/30
CPC分类号： G06F1/3296 , G06F1/3209 , G06F1/3228 , G06F1/3243 , G06F9/4893 , G06F2209/548 , Y02D10/152 , Y02D10/24 , Y02D50/20
摘要： In an embodiment, a system includes a processor that includes a plurality of cores and a plurality of queue. Each queue includes storage locations to store packets to be processed by at least one of the cores. Each queue has a corresponding state that is one of active and inactive. Each active queue is enabled to store an incoming packet, and each inactive queue is disabled from storage of the incoming packet. Each queue has a corresponding queue depth that includes a count of occupied storage locations of the queue. The system also includes packet distribution logic to determine whether to change the state of a first queue of the plurality of queues from a first state to a second state based on a total queue depth that includes a sum of the queue depths of the active queues. Other embodiments are described and claimed.

10. 发明申请

WO2022139922A1 PRIORITIZING BOOTING OF VIRTUAL EXECUTION ENVIRONMENTS 审中-公开
公开(公告)号：WO2022139922A1
公开(公告)日：2022-06-30
申请号：PCT/US2021/051800
申请日：2021-09-23
申请人： INTEL CORPORATION
发明人： MISRA, Amruta , MACNAMARA, Chris , BROWNE, John J. , MA, Liang , JAIN, Shobhi , HUNT, David
IPC分类号： G06F9/455 , G06F9/50 , H04L12/24 , G06F9/4401
摘要： Examples described herein relate to circuitry to boot a virtualized execution environment (VEE) by use of system resources, wherein the system resources are allocated based on a priority level of the VEE. In some examples, the circuitry to boot a VEE by use of system resources is to access an identification of system resources to use to boot the VEE and priority level of the VEE from stored data. In some examples, the priority level of the VEE is based on a service level agreement (SLA), service level objective (SLO), or class of service (COS) that identifies boot time of the VEE. In some examples, the circuitry is to boot a VEE by use of system resources, wherein the system resources are allocated based on a priority level of the VEE and also based on a number of VEEs that boot concurrently.

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