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1. 发明申请

WO2011163022A3 MEMORY WRITE OPERATION METHODS AND CIRCUITS 审中-公开
标题翻译：存储器写操作方法和电路
公开(公告)号：WO2011163022A3
公开(公告)日：2012-03-01
申请号：PCT/US2011040458
申请日：2011-06-15
申请人： INTEL CORP , KULKARNI JAYDEEP P , KHELLAH MUHAMMAD M , GEUSKENS BIBICHE M , RAYCHOWDHURY ARIJIT , KARNIK TANAY , DE VIVEK K
发明人： KULKARNI JAYDEEP P , KHELLAH MUHAMMAD M , GEUSKENS BIBICHE M , RAYCHOWDHURY ARIJIT , KARNIK TANAY , DE VIVEK K
IPC分类号： G11C8/08 , G11C7/10 , G11C7/12
CPC分类号： G11C8/08 , G11C7/12 , G11C7/20 , G11C11/412 , G11C11/413
摘要： In some embodiments, write wordline boost may be obtained from wordline driver boost and/or from bit line access transistor boost.
摘要翻译：在一些实施例中，可以从字线驱动器升压和/或来自位线存取晶体管升压获得写入字线升压。

2. 发明申请

WO2006039606A2 CPU POWER DELIVERY SYSTEM 审中-公开
标题翻译： CPU电源传输系统
公开(公告)号：WO2006039606A2
公开(公告)日：2006-04-13
申请号：PCT/US2005035388
申请日：2005-09-29
申请人： INTEL CORP , NARENDRA SIVA , WILSON HOWARD , GARDNER DONALD , HAZUCHA PETER , SCHROM GERHARD , KARNIK TANAY , BORKAR NITIN , DE VIVEK , BORKAR SHEKHAR
发明人： NARENDRA SIVA , WILSON HOWARD , GARDNER DONALD , HAZUCHA PETER , SCHROM GERHARD , KARNIK TANAY , BORKAR NITIN , DE VIVEK , BORKAR SHEKHAR
CPC分类号： G06F1/26 , G06F1/189 , H01L25/16 , H01L25/18 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2924/00014 , H01L2924/01068 , H01L2924/15311 , H01L2924/3011 , H01L2224/05599
摘要： A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a voltage regulator/ converter die bonded to the CPU die in a three dimensional packaging layout.
摘要翻译：公开了一种中央处理单元（CPU）。 CPU包括CPU管芯; 以及以三维封装布局结合到CPU管芯的电压调节器/转换器管芯。

3. 发明申请

WO2006039048A3 AN APPARATUS AND METHOD FOR MULTI-PHASE TRANSFORMERS 审中-公开
标题翻译：多相变压器的装置和方法
公开(公告)号：WO2006039048A3
公开(公告)日：2006-08-10
申请号：PCT/US2005031311
申请日：2005-09-01
申请人： INTEL CORP , SCHROM GERHARD , HAZUCHA PETER , GARDNER DONALD , DE VIVEK , KARNIK TANAY
发明人： SCHROM GERHARD , HAZUCHA PETER , GARDNER DONALD , DE VIVEK , KARNIK TANAY
IPC分类号： H01F37/00 , H02M3/158
CPC分类号： H02M3/1584 , H01F27/38 , H01F27/42 , H01F37/00 , H01F2038/026
摘要： A method and apparatus for multi-phase transformers (200) are described. In one embodiment, a coupled inductor topology for the multi-phase transformers comprising N primary inductors (210-240). In one embodiment, each primary inductor is coupled to one of N input nodes (201-1, 201-2, 201-3, 201-4) and a common output node (205). The transformer further includes N-1 secondary inductors (222-242) coupled in series between one input node (201-1) and the common output node (250). In one embodiment, the N-1 secondary inductors (222-242) are arranged to couple energy from N-1 of the primary inductors (220-240) to provide a common node voltage (250) as an average of N input node voltages (201-1, 201-2, 201-3, 201-4), wherein N is an integer greater than two. Other embodiments are described and claimed.
摘要翻译：描述了一种用于多相变压器（200）的方法和装置。在一个实施例中，用于多相变压器的耦合电感器拓扑结构包括N个初级电感器（210-240）。在一个实施例中，每个初级电感器耦合到N个输入节点（201-1,201-2,201-3,201-4-4）和公共输出节点（205）中的一个。变压器还包括串联耦合在一个输入节点（201-1）和公共输出节点（250）之间的N-1个次级电感器（222-242）。在一个实施例中，N-1次级电感器（222-242）被布置成耦合来自主电感器（220-240）的N-1的能量，以提供作为N个输入节点电压的平均值的公共节点电压（250）（201-1,201-2,201-3,201-4），其中N是大于2的整数。描述和要求保护其他实施例。

4. 发明申请

WO2015088626A3 BIOMETRIC SENSORS FOR PERSONAL DEVICES 审中-公开
标题翻译：用于个人设备的生物量传感器
公开(公告)号：WO2015088626A3
公开(公告)日：2015-08-13
申请号：PCT/US2014057581
申请日：2014-09-26
申请人： INTEL CORP , PANT MONDIRA D , ABDELMONEUM MOHAMED A , KARNIK TANAY , PISENTI STEPHEN , POISNER DAVID I , MAHAMEED RASHED
发明人： PANT MONDIRA D , ABDELMONEUM MOHAMED A , KARNIK TANAY , PISENTI STEPHEN , POISNER DAVID I , MAHAMEED RASHED
IPC分类号： G06K9/00 , G06F21/32
CPC分类号： G01N29/265 , G01N2291/106 , G06F21/32 , G06F2221/2111 , G06K9/0002 , Y10T29/49005
摘要： Methods and systems may provide for a system having a flexible substrate, an ultrasonic transducer array coupled to the flexible substrate and a processor coupled to the ultrasonic transducer array. The processor may identify a fingerprint based on a signal from the ultrasonic transducer array. The system may also include an external component having a curved profile, wherein the ultrasonic transducer array is embedded in the external component and includes a read surface that conforms to the curved profile. In one example, the external component includes a button having a function that is separate from identification of the fingerprint.
摘要翻译：方法和系统可以提供具有柔性衬底，耦合到柔性衬底的超声换能器阵列和耦合到超声换能器阵列的处理器的系统。处理器可以基于来自超声换能器阵列的信号识别指纹。该系统还可以包括具有弯曲轮廓的外部部件，其中超声换能器阵列嵌入在外部部件中并且包括符合弯曲轮廓的读取表面。在一个示例中，外部组件包括具有与指纹的识别分离的功能的按钮。

5. 发明申请

WO2007038529A3 POWER DELIVERY AND POWER MANAGEMENT OF MANY-CORE PROCESSORS 审中-公开
标题翻译：电源交付和多核处理器的电源管理
公开(公告)号：WO2007038529A3
公开(公告)日：2007-06-28
申请号：PCT/US2006037522
申请日：2006-09-26
申请人： INTEL CORP , BORKAR SHEKHAR , GARVER SHU-LING , KARNIK TANAY
发明人： BORKAR SHEKHAR , GARVER SHU-LING , KARNIK TANAY
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/3287 , G06F1/3296 , H01L25/0657 , H01L25/16 , H01L25/18 , H01L2225/06513 , H01L2225/06527 , H01L2924/0002 , Y02D10/171 , Y02D10/172 , H01L2924/00
摘要： According to embodiments of the disclosed subject matter in this application, a power management system with multiple voltage regulator ("VRs") may be used to supply power to cores in a many-core processor. Each VR may supply power to a core or a part of a core. Different VRs may provide multiple voltages to a core/part in the many-core processor. The value of the output voltage of a VR may be modulated under the direction of the core/part to which the voltage regulator supplies power. In one embodiment, the multiple VRs may be integrated with cores in a single die. In another embodiment, the power management system with multiple VRs may be on a die ("the VR die") separate from the die of the many-core processor. The VR die may be included in the same package as the many-core processor die.
摘要翻译：根据本申请中公开的主题的实施例，具有多个电压调节器（“VR”）的电力管理系统可以用于向多核处理器中的核供电。每个VR可以为核心或核心的一部分供电。不同的VR可以为多核处理器中的核心/部分提供多个电压。 VR的输出电压的值可以在电压调节器供电的核心/部件的方向上被调制。在一个实施例中，可以将多个VR与核心集成在单个管芯中。在另一个实施例中，具有多个VR的电力管理系统可位于与多核处理器的管芯分离的管芯（“VR管芯”）上。 VR芯片可能与多核处理器芯片包含在相同的封装中。

6. 发明申请

WO2009061789A3 METHODS OF FORMING MAGNETIC VIAS TO MAXIMIZE INDUCTANCE IN INTEGRATED CIRCUITS AND STRUCTURES FORMED THEREBY 审中-公开
标题翻译：形成磁性VIAS的方法最大限度地提高了集成电路中的电感和形成的结构
公开(公告)号：WO2009061789A3
公开(公告)日：2009-09-03
申请号：PCT/US2008082443
申请日：2008-11-05
申请人： INTEL CORP , GARDNER DONALD , SCHROM GERHARD , HAZUCHA PETER , PAILLET FABRICE , KARNIK TANAY
发明人： GARDNER DONALD , SCHROM GERHARD , HAZUCHA PETER , PAILLET FABRICE , KARNIK TANAY
IPC分类号： H01L27/04
CPC分类号： H01F41/046 , H01F17/0006 , H01F27/324 , H01F2017/0066 , H01L23/5227 , H01L2924/0002 , Y10T29/4902 , Y10T428/24331 , H01L2924/00
摘要： Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of a magnetic material on a substrate, forming an oxide layer on the first layer of the magnetic material, forming at least one conductive structure on the first magnetic layer, forming a dielectric layer on the at least one conductive structure, forming a second layer of the magnetic material on the at least one conductive structure, and forming a magnetic via coupled to the first and second layers of the magnetic material, wherein the magnetic via comprises a shape to increase inductance of the inductive structure.
摘要翻译：描述形成微电子器件的方法和相关结构。这些方法可以包括在衬底上形成磁性材料的第一层，在磁性材料的第一层上形成氧化物层，在第一磁性层上形成至少一个导电结构，在至少一个上形成介电层在所述至少一个导电结构上形成所述磁性材料的第二层，以及形成耦合到所述磁性材料的所述第一和第二层的磁通孔，其中所述磁通孔包括增加所述电感结构的电感的形状。

7. 发明申请

WO0146989A3 DECOUPLING CAPACITORS FOR THIN GATE OXIDES 审中-公开
标题翻译：用于薄栅氧化物的去除电容器
公开(公告)号：WO0146989A3
公开(公告)日：2002-05-10
申请号：PCT/US0031352
申请日：2000-11-13
申请人： INTEL CORP , KESHAVARZI ALI , VIVEK K DE , KARNIK TANAY , NAIR RAJENDRAN
发明人： KESHAVARZI ALI , DE VIVEK K , KARNIK TANAY , NAIR RAJENDRAN
IPC分类号： H01L27/04 , H01L21/822 , H01L27/08 , H01L29/94 , H01L27/06
CPC分类号： H01L27/0805 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： In some embodiments, the invention involves a die having a first conductor carrying a power supply voltage and a second conductor carrying a ground voltage. A semiconductor capacitor operating in depletion mode is coupled between the first and second conductors to provide decoupling capacitance between the first and second conductors, the semiconductor capacitor having a gate voltage. Various configurations may be used including: n+ gate poly and n+ source/drain regions in an n-body; p+ gate poly and n+ source/drain regions in an n-body; p+ gate poly and p+ source/drain regions in an n-body; p+ gate poly and p+ source/drain regions in a p-body; n+ gate poly and p+ source/drain regions in a p-body; n+ gate poly and n+ source/drain regions in a p-body. The power supply voltage may have a larger absolute value than does a flatband voltage.
摘要翻译：在一些实施例中，本发明涉及具有承载电源电压的第一导体和承载接地电压的第二导体的管芯。以耗尽模式工作的半导体电容器耦合在第一和第二导体之间，以在第一和第二导体之间提供去耦电容，半导体电容器具有栅极电压。可以使用各种配置，包括：n体中的n +栅极多晶硅和n +源极/漏极区域; p +栅极多晶硅和n +源极/漏极区域; p +栅极poly和p +源极/漏极区域在n体中; p体中的p +栅极多晶硅和p +源极/漏极区域; p体中的n +栅极多晶硅和p +源极/漏极区域; p体中的n +栅极多晶硅和n +源极/漏极区域。电源电压可能比平带电压具有更大的绝对值。

8. 发明申请

WO2008003008A2 INTEGRATED INDUCTOR 审中-公开
标题翻译：集成电感器
公开(公告)号：WO2008003008A2
公开(公告)日：2008-01-03
申请号：PCT/US2007072293
申请日：2007-06-27
申请人： INTEL CORP , HAZUCHA PETER , BURTON EDWARD , NGUYEN TRANG T , SCHROM GERHARD , PAILLET FABRICE , RADHAKRISHNAN KALADHAR , GARDNER DONALD S , MOON SUNG T , KARNIK TANAY
发明人： HAZUCHA PETER , BURTON EDWARD , NGUYEN TRANG T , SCHROM GERHARD , PAILLET FABRICE , RADHAKRISHNAN KALADHAR , GARDNER DONALD S , MOON SUNG T , KARNIK TANAY
CPC分类号： H05K1/165 , H01L23/645 , H01L2223/6677 , H01L2924/0002 , H01L2924/3011 , H05K1/0263 , H05K3/42 , H05K2201/09627 , H05K2201/09709 , H01L2924/00
摘要： An inductor and multiple inductors embedded in a substrate (e.g., IC package substrate, board substrate, and/or other substrate) is provided herein.
摘要翻译：本文提供了嵌入基板（例如IC封装基板，板基板和/或其他基板）中的电感器和多个电感器。

9. 发明专利

JP2010016377A Multiple-die integrated circuit device and method 有权
标题翻译：多芯片集成电路设备及方法
公开(公告)号：JP2010016377A
公开(公告)日：2010-01-21
申请号：JP2009153602
申请日：2009-06-29
申请人： Intel Corp , インテル・コーポレーション
发明人： SOMASEKHAR DINESH , KARNIK TANAY , XU JIANPING , YE YIBIN
IPC分类号： H01L21/822 , H01L21/3205 , H01L23/52 , H01L25/065 , H01L25/07 , H01L25/18 , H01L27/04
CPC分类号： H01L25/18 , G11C5/02 , G11C5/063 , H01L23/481 , H01L23/5286 , H01L2224/05573 , H01L2224/13025 , H01L2224/16225 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2224/05599
摘要： PROBLEM TO BE SOLVED: To provide a device which can locate the contacting pads of its through silicon vias efficiently when laminating a plurality of dice as a three-dimensional integrated circuit package. SOLUTION: In an integrated circuit including a first die coupled to such a second die as a memory die, a plurality of through silicon vias TSV are located so as to pass them through the second die, and a power reference is fed to the first die. The plurality of through silicon vias are made relocatable in a lateral direction without interfering with a plurality circuit sections MS of the second die. COPYRIGHT: (C)2010,JPO&INPIT

10. 发明专利

JP2010250856A Power delivery system 审中-公开
标题翻译：电力输送系统
公开(公告)号：JP2010250856A
公开(公告)日：2010-11-04
申请号：JP2010158580
申请日：2010-07-13
申请人： Intel Corp , インテルコーポレイション
发明人： BORKAR SHEKHAR , KARNIK TANAY , HAZUCHA PETER , SCHROM GERHARD , DERMER GREG
IPC分类号： G06F1/28
CPC分类号： G06F1/28
摘要： PROBLEM TO BE SOLVED: To efficiently manage power consumption of a load. SOLUTION: The system includes a load coupled to the power supply to receive one or more voltages from the power supply, a voltage regulator circuit coupled to the load, and a digital bus coupled between the power supply and the load. The digital bus transmits power consumption measurements from the load to the power supply and transmits power consumption measurements from the power supply to the load. COPYRIGHT: (C)2011,JPO&INPIT

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