专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06385020B1 Methods of forming HSG capacitors from nonuniformly doped amorphous silicon layers and HSG capacitors formed thereby 失效
标题翻译：由不均匀掺杂的非晶硅层和由此形成的HSG电容器形成HSG电容器的方法
公开(公告)号：US06385020B1
公开(公告)日：2002-05-07
申请号：US09487740
申请日：2000-01-19
申请人： Hyun-bo Shin , Myeong-cheol Kim , Jin-won Kim , Ki-hyun Hwang , Jae-young Park , Bon-young Koo
发明人： Hyun-bo Shin , Myeong-cheol Kim , Jin-won Kim , Ki-hyun Hwang , Jae-young Park , Bon-young Koo
IPC分类号： H02H700
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/84
摘要： A hemispherical grain (HSG) capacitor having HSGs on at least a part of the surface of capacitor lower electrodes, and a method of forming the same. In the capacitor, lower electrodes are formed of at least two amorphous silicon layers including an amorphous silicon layer doped with a high concentration of impurities and an amorphous silicon layer doped with a low concentration of impurities, and HSGs are formed, wherein the size of the hemispherical grains can be adjusted such that the size of HSGs formed on the inner surface of a U-shaped lower electrode or on the top of a stacked lower electrode is larger than that of HSGs formed on the outer surface of the U-shaped lower electrode or on the sidews of the stacked lower electrode. Thus, bridging between neighboring lower electrodes can be avoided by appropriately adjusting the size of HSGs, resulting in uniform capacitance wafer-to-wafer and within a wafer. The mechanical strength of the U-shaped lower electrode can also be enhanced.
摘要翻译：在电容器下电极的表面的至少一部分上具有HSG的半球状晶粒（HSG）电容器及其形成方法。在电容器中，下电极由至少两个非晶硅层形成，包括掺杂有高浓度杂质的非晶硅层和掺杂有低浓度杂质的非晶硅层，形成HSG，可以调节半球形颗粒，使得形成在U形下电极的内表面上或堆叠的下电极的顶部上的HSG的尺寸大于形成在U形下电极的外表面上的HSG的尺寸或在堆叠的下电极的侧面上。因此，可以通过适当地调节HSG的尺寸来避免相邻的下部电极之间的桥接，导致晶片到晶片和晶片内的均匀电容。也可以提高U形下电极的机械强度。

2. 发明授权

US06265740B1 Semiconductor device capacitor using a fill layer and a node on an inner surface of an opening 有权
标题翻译：使用填充层的半导体器件电容器和开口的内表面上的节点
公开(公告)号：US06265740B1
公开(公告)日：2001-07-24
申请号：US09427173
申请日：1999-10-25
申请人： Jin-won Kim
发明人： Jin-won Kim
IPC分类号： H01L27108
CPC分类号： H01L28/55 , H01L21/31053 , H01L27/10852 , H01L28/60 , H01L28/91
摘要： A capacitor of a semiconductor device includes a first insulating layer having a contact hole therethrough and a contact plug that is in the contact hole and electrically connected to a semiconductor substrate. Also, a diffusion barrier layer is on the contact plug and fills the contact hole, and a storage node is on the insulating layer in contact with the diffusion barrier layer. The storage node has a uniform outer surface morphology and a cavity therein. A second insulating layer is on the first insulating layer and separates the storage nodes from adjacent storage nodes, and a fill layer fills the cavities of the storage nodes. A dielectric layer having a large dielectric constant covers the second insulating layer, the fill layer, and the storage nodes, and a plate node is on the dielectric layer. The storage node has a smooth surface adjacent the dielectric layer, which decreases leakage current. The diffusion barrier layer is buried in the contact hole and avoids oxidation that would otherwise increase contact resistance.
摘要翻译：半导体器件的电容器包括具有穿过其中的接触孔的第一绝缘层和位于接触孔中并与半导体衬底电连接的接触插塞。此外，扩散阻挡层在接触塞上并填充接触孔，并且存储节点位于与扩散阻挡层接触的绝缘层上。存储节点具有均匀的外表面形态和其中的空腔。第二绝缘层位于第一绝缘层上，并将存储节点与相邻存储节点分开，填充层填充存储节点的空腔。具有大介电常数的电介质层覆盖第二绝缘层，填充层和存储节点，并且电介质层上具有平板节点。存储节点具有与介电层相邻的平滑表面，这降低了漏电流。扩散阻挡层埋在接触孔中，避免了否则会增加接触电阻的氧化。

3. 发明授权

US06380579B1 Capacitor of semiconductor device 失效
标题翻译：半导体器件电容器
公开(公告)号：US06380579B1
公开(公告)日：2002-04-30
申请号：US09547940
申请日：2000-04-11
申请人： Sang-don Nam , Jin-won Kim
发明人： Sang-don Nam , Jin-won Kim
IPC分类号： H01L27108
CPC分类号： H01L28/75 , H01L28/55
摘要： A capacitor of a semiconductor device which uses a high dielectric layer and a method of manufacturing the same are provided. The capacitor includes a storage electrode having at least two conductive patterns which overlap each other and a thermally-stable material layer pattern being positioned between the conductive layer patterns. The storage electrode and the thermally-stable material layer pattern are formed by alternately forming a conductive layer and a thermally-stable material layer, and patterning the conductive layer and the thermally-stable material layer to have predetermined shapes. With the present structure, it is possible to prevent the storage electrode from being transformed or broken during a thermal treatment process for forming a high dielectric layer on the storage electrode or in a subsequent high temperature thermal treatment process.
摘要翻译：提供了使用高介电层的半导体器件的电容器及其制造方法。电容器包括具有彼此重叠的至少两个导电图案的存储电极和位于导电层图案之间的热稳定材料层图案。存储电极和热稳定材料层图案通过交替形成导电层和热稳定材料层而形成，并且将导电层和热稳定材料层图案化以具有预定形状。利用本结构，可以防止在用于在存储电极上形成高电介质层的热处理工艺中或在随后的高温热处理工艺中存储电极变形或破裂。

4. 发明授权

US07018933B2 Method of forming a metal-insulator-metal capacitor 有权
公开(公告)号：US07018933B2
公开(公告)日：2006-03-28
申请号：US10426743
申请日：2003-04-30
申请人： Wan-don Kim , Jin-won Kim , Seok-jun Won , Cha-young Yoo
发明人： Wan-don Kim , Jin-won Kim , Seok-jun Won , Cha-young Yoo
IPC分类号： H01L21/302 , H01L21/8242
CPC分类号： H01L21/02183 , H01L21/0228 , H01L21/02337 , H01L21/02348 , H01L21/31604 , H01L28/91
摘要： A metal-insulator-metal (MIM) capacitor of a semiconductor device, and a manufacturing method thereof, includes a lower electrode formed of a refractory metal or a conductive compound including the refractory metal, a dielectric film formed of a high dielectric material, and an upper electrode formed of a platinum-family metal or a platinum-family metal oxide. Accordingly, the MIM capacitor satisfies the criteria of step coverage, electrical characteristics and manufacturing costs, as compared to a conventional MIM capacitor in which the upper and lower electrodes are formed of the same material such as a platinum-family metal, a refractory metal or a conductive compound including the refractory metal. The capacitor is especially suitable for mass production in semiconductor fabrication processes.

5. 发明申请

US20070168896A1 Method and apparatus for verifying logic circuit 有权
标题翻译：用于验证逻辑电路的方法和装置
公开(公告)号：US20070168896A1
公开(公告)日：2007-07-19
申请号：US11649628
申请日：2007-01-04
申请人： Sang-ho Park , Jong-bae Lee , Moon-hyun Yoo , Ho Shim , Jin-won Kim
发明人： Sang-ho Park , Jong-bae Lee , Moon-hyun Yoo , Ho Shim , Jin-won Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5022
摘要： A method and an apparatus for verifying a logic circuit, capable of quicker operation, being applied to a logic gate-level or transistor-level circuit design, and verifying timing and analog signal characteristics of a signal. The logic circuit verification method includes a wave file generation stage and a logic circuit verification stage. The wave file generation stage generates a wave file that includes the waveforms of all nodes of the logic circuit using a design source file of the logic circuit. The stage of verification of the logic circuit verifies the logic circuit using a design reference file, which includes ideal operations of all the nodes of the logic circuit, and the wave file.
摘要翻译：一种用于验证逻辑电路的方法和装置，其能够更快的操作，被应用于逻辑门级或晶体管级电路设计，以及验证信号的定时和模拟信号特性。逻辑电路验证方法包括波形文件生成阶段和逻辑电路验证阶段。波形文件生成阶段使用逻辑电路的设计源文件生成包括逻辑电路的所有节点的波形的波形文件。逻辑电路的验证阶段使用设计参考文件验证逻辑电路，该设计参考文件包括逻辑电路的所有节点和波形文件的理想操作。

6. 发明授权

US06580111B2 Metal-insulator-metal capacitor 有权
标题翻译：金属绝缘体金属电容器
公开(公告)号：US06580111B2
公开(公告)日：2003-06-17
申请号：US09863679
申请日：2001-05-23
申请人： Wan-don Kim , Jin-won Kim , Seok-jun Won , Cha-young Yoo
发明人： Wan-don Kim , Jin-won Kim , Seok-jun Won , Cha-young Yoo
IPC分类号： H01L27108
CPC分类号： H01L21/02183 , H01L21/0228 , H01L21/02337 , H01L21/02348 , H01L21/31604 , H01L28/91
摘要： A metal-insulator-metal (MIM) capacitor of a semiconductor device, and a manufacturing method thereof, includes a lower electrode formed of a refractory metal or a conductive compound including the refractory metal, a dielectric film formed of a high dielectric material, and an upper electrode formed of a platinum-family metal or a platinum-family metal oxide. Accordingly, the MIM capacitor satisfies the criteria of step coverage, electrical characteristics and manufacturing costs, as compared to a conventional MIM capacitor in which the upper and lower electrodes are formed of the same material such as a platinum-family metal, a refractory metal or a conductive compound including the refractory metal. The capacitor is especially suitable for mass production in semiconductor fabrication processes.
摘要翻译：半导体器件的金属 - 绝缘体 - 金属（MIM）电容器及其制造方法包括由难熔金属形成的下电极或包含难熔金属的导电化合物，由高电介质材料形成的电介质膜，以及由铂族金属或铂族金属氧化物形成的上电极。因此，与常规的MIM电容器相比，MIM电容器满足阶梯覆盖，电特性和制造成本的标准，其中上电极和下电极由相同的材料形成，例如铂族金属，难熔金属或包括难熔金属的导电化合物。电容器特别适用于半导体制造工艺中的批量生产。

7. 发明授权

US07913207B2 Method and apparatus for verifying logic circuit 有权
标题翻译：用于验证逻辑电路的方法和装置
公开(公告)号：US07913207B2
公开(公告)日：2011-03-22
申请号：US11649628
申请日：2007-01-04
申请人： Sang-ho Park , Jong-bae Lee , Moon-hyun Yoo , Ho Shim , Jin-won Kim
发明人： Sang-ho Park , Jong-bae Lee , Moon-hyun Yoo , Ho Shim , Jin-won Kim
IPC分类号： G06F17/50 , G06F9/455 , G06F11/22
CPC分类号： G06F17/5031 , G06F17/5022
摘要： A method and an apparatus for verifying a logic circuit, capable of quicker operation, being applied to a logic gate-level or transistor-level circuit design, and verifying timing and analog signal characteristics of a signal. The logic circuit verification method includes a wave file generation stage and a logic circuit verification stage. The wave file generation stage generates a wave file that includes the waveforms of all nodes of the logic circuit using a design source file of the logic circuit. The stage of verification of the logic circuit verifies the logic circuit using a design reference file, which includes ideal operations of all the nodes of the logic circuit, and the wave file.
摘要翻译：一种用于验证逻辑电路的方法和装置，其能够更快的操作，被应用于逻辑门级或晶体管级电路设计，以及验证信号的定时和模拟信号特性。逻辑电路验证方法包括波形文件生成阶段和逻辑电路验证阶段。波形文件生成阶段使用逻辑电路的设计源文件生成包括逻辑电路的所有节点的波形的波形文件。逻辑电路的验证阶段使用设计参考文件验证逻辑电路，该设计参考文件包括逻辑电路的所有节点和波形文件的理想操作。

8. 发明授权

US06500763B2 Method for manufacturing an electrode of a capacitor 失效
标题翻译：制造电容器电极的方法
公开(公告)号：US06500763B2
公开(公告)日：2002-12-31
申请号：US09735901
申请日：2000-12-14
申请人： Jin-won Kim , Sang-don Nam , Wan-don Kim , Kab-jin Nam
发明人： Jin-won Kim , Sang-don Nam , Wan-don Kim , Kab-jin Nam
IPC分类号： H01L21302
CPC分类号： H01L28/91 , H01L21/31111 , H01L21/31116 , H01L21/31122
摘要： A method for manufacturing an electrode of a capacitor used in a semiconductor device, wherein a support insulating layer, an etch stop layer including a tantalum oxide layer, and a mold sacrificial insulating layer are sequentially formed on a semiconductor substrate. The mold sacrificial insulating layer, the etch stop layer and the support insulating layer are sequentially patterned to form a three-dimensional mold for a storage node. A storage node layer is formed to cover the inner surface of the mold. Next, storage nodes for capacitors are formed by dividing the storage node layer. The residual mold sacrificial insulating layer is removed by selectively wet etching, using the tantalum oxide layer as an etch stopper.
摘要翻译：在半导体器件中制造用于电容器的电极的方法，其中在半导体衬底上依次形成支撑绝缘层，包括氧化钽层的蚀刻停止层和模具牺牲绝缘层。模具牺牲绝缘层，蚀刻停止层和支撑绝缘层被顺序地图案化以形成用于存储节点的三维模具。形成存储节点层以覆盖模具的内表面。接下来，通过划分存储节点层来形成用于电容器的存储节点。通过使用氧化钽层作为蚀刻停止器，通过选择性湿法蚀刻除去残余模具牺牲绝缘层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式