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1. 发明申请

US20100232213A1 CONTROL SIGNAL TRANSMITTING SYSTEM OF A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件的控制信号传输系统
公开(公告)号：US20100232213A1
公开(公告)日：2010-09-16
申请号：US12711586
申请日：2010-02-24
申请人： Hyong-Ryol Hwang , Chi-Sung Oh , Sang-Kyu Kang
发明人： Hyong-Ryol Hwang , Chi-Sung Oh , Sang-Kyu Kang
IPC分类号： G11C11/24 , G11C7/00 , G11C8/18
CPC分类号： G11C7/1048 , G11C7/1051 , G11C7/1069 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4091 , G11C11/4096
摘要： Exemplary embodiments relate to a control signal driving device of a semiconductor device, including: a bus line; a converter receiving a first periodic control signal having the period (frequency) of a clock signal, converting the first periodic control signal into a converted control signal that has twice the period (half the frequency) of the clock signal, and outputting the converted control signal to the bus line; and a restoring unit connected to the opposite end of the bus line and receiving the converted control signal and restoring the converted control signal back into the first periodic control signal.
摘要翻译：示例性实施例涉及半导体器件的控制信号驱动装置，包括：总线; 接收具有时钟信号的周期（频率）的第一周期性控制信号的转换器，将所述第一周期性控制信号转换成具有所述时钟信号的两倍周期（一半频率）的转换控制信号，并输出所述转换控制信号到总线; 以及恢复单元，连接到总线的相对端并接收转换的控制信号，并将转换的控制信号恢复到第一周期性控制信号中。

2. 发明授权

US07492647B2 Voltage generation circuit and semiconductor memory device including the same 有权
标题翻译：电压产生电路和包括其的半导体存储器件
公开(公告)号：US07492647B2
公开(公告)日：2009-02-17
申请号：US12025442
申请日：2008-02-04
申请人： Hyong-Ryol Hwang , Young-Hyun Jun
发明人： Hyong-Ryol Hwang , Young-Hyun Jun
IPC分类号： G11C7/00
CPC分类号： G11C5/14
摘要： A voltage generation circuit and semiconductor memory device including the same are provided. The voltage generation circuit includes: a voltage level detector, which detects a level of a first high voltage to generate a first high voltage level detection signal and detects a level of a second high voltage to generate a second high voltage level detection signal; a control signal generator, which generates at least four pumping control signals in sequence when the first high voltage level detection signal is active, generates a control signal when the first high voltage level detection signal is inactive, and generates a first one of the at least four pumping control signals in response to a level of a power supply voltage; and a voltage generator, which pumps a boost node in response to the at least four pumping control signals to generate the first high voltage and transmits charge from the boost node to a second high voltage generation terminal in response to the control signal to generate the second high voltage.
摘要翻译：提供了包括该电压产生电路和半导体存储器件的电压产生电路。电压产生电路包括：电压电平检测器，其检测第一高电平的电平以产生第一高电压电平检测信号，并检测第二高电平的电平以产生第二高电压电平检测信号; 控制信号发生器，当所述第一高电压电平检测信号有效时，依次产生至少四个泵送控制信号，当所述第一高电压电平检测信号无效时产生控制信号，并且产生至少四个泵送控制信号响应于电源电压的电平; 以及电压发生器，其响应于所述至少四个泵送控制信号泵送升压节点以产生所述第一高电压，并且响应于所述控制信号将电压从所述升压节点传输到第二高电压发生端子，以产生所述第二高电压高压。

3. 发明申请

US20060120179A1 Voltage generation circuit and semiconductor memory device including the same 有权
公开(公告)号：US20060120179A1
公开(公告)日：2006-06-08
申请号：US11293890
申请日：2005-12-02
申请人： Hyong-Ryol Hwang , Young-Hyun Jun
发明人： Hyong-Ryol Hwang , Young-Hyun Jun
IPC分类号： G11C7/00
CPC分类号： G11C5/14
摘要： A voltage generation circuit and semiconductor memory device including the same are provided. The voltage generation circuit includes: a voltage level detector, which detects a level of a first high voltage to generate a first high voltage level detection signal and detects a level of a second high voltage to generate a second high voltage level detection signal; a control signal generator, which generates at least four pumping control signals in sequence when the first high voltage level detection signal is active, generates a control signal when the first high voltage level detection signal is inactive, and generates a first one of the at least four pumping control signals in response to a level of a power supply voltage; and a voltage generator, which pumps a boost node in response to the at least four pumping control signals to generate the first high voltage and transmits charge from the boost node to a second high voltage generation terminal in response to the control signal to generate the second high voltage.

4. 发明授权

US06819617B2 System and method for performing partial array self-refresh operation in a semiconductor memory device 有权
标题翻译：在半导体存储器件中进行部分阵列自刷新操作的系统和方法
公开(公告)号：US06819617B2
公开(公告)日：2004-11-16
申请号：US10452176
申请日：2003-06-02
申请人： Hyong-Ryol Hwang , Jong-Hyun Choi , Hyun-Soon Jang
发明人： Hyong-Ryol Hwang , Jong-Hyun Choi , Hyun-Soon Jang
IPC分类号： G11C700
CPC分类号： G11C11/40622 , G11C7/1018 , G11C11/406 , G11C11/4087
摘要： Systems and methods for performing a PASR (partial array self-refresh) operation wherein a refresh operation for recharging stored data is performed on a portion (e.g., ½ ¼, ⅛, or {fraction (1/16)}) of one or more selected memory banks comprising a cell array in a semiconductor memory device. In one aspect, a PASR operation is performed by (1) controlling the generation of row addresses by a row address counter during a self-refresh operation and (2) controlling a self-refresh cycle generating circuit to adjust the self-refresh cycle output therefrom. The self-refresh cycle is adjusted in a manner that provides a reduction in the current dissipation during the PASR operation. In another aspect, a PASR operation is performed by controlling one or more row addresses corresponding to a partial cell array during a self-refresh operation, whereby a reduction in a self-refresh current dissipation is achieved by blocking the activation of a non-used block of a memory bank.
摘要翻译：执行PASR（部分阵列自刷新）操作的系统和方法，其中对一个或多个部分（例如，1 / 2,1 / 8或{分数（1/16））的一部分执行用于对存储数据进行再充电的刷新操作在一个方面，通过（1）在自刷新操作期间通过行地址计数器控制行地址的生成来执行PASR操作，以及（2）控制自身的自身 - 刷新周期产生电路，用于调整其自刷新周期输出，在PASR操作期间以减少电流消耗的方式调整自刷新周期，另一方面，通过控制一个PASR操作来执行PASR操作或更多行对应于自刷新操作期间的部分单元阵列的行地址，从而通过阻止存储器组的未使用块的激活来实现自刷新电流消耗的减少。

5. 发明授权

US07613063B2 Internal power voltage generating circuit in semiconductor memory device 有权
标题翻译：半导体存储器件内部电源电压产生电路
公开(公告)号：US07613063B2
公开(公告)日：2009-11-03
申请号：US11646543
申请日：2006-12-28
申请人： Hyong-Ryol Hwang , Ki-Ho Jang
发明人： Hyong-Ryol Hwang , Ki-Ho Jang
IPC分类号： G11C5/14
CPC分类号： G11C5/147
摘要： A method and circuit are disclosed for generating an internal power voltage in a semiconductor memory device. The method includes receiving an external power voltage in an internal power voltage generating circuit and activating a power-up signal during a first period in the applied external power voltage rising to a desired level, powering-up the internal power voltage in relation to the external power voltage during the first period, and continuing the power-up of the internal power voltage during a second period following the first period, the second period extending beyond the deactivation of the power-up signal until receipt of an active command signal.
摘要翻译：公开了用于在半导体存储器件中产生内部电源电压的方法和电路。该方法包括在内部电源电压产生电路中接收外部电源电压，并且在施加的外部电源电压上升至期望电平的第一时段期间激活上电信号，将内部电源电压相对于外部电源并且在第一周期之后的第二周期期间继续上电内部电源电压，第二周期延长超过上电信号的去激活，直到接收到有效指令信号为止。

6. 发明授权

US07349268B2 Voltage generation circuit and semiconductor memory device including the same 有权
标题翻译：电压产生电路和包括其的半导体存储器件
公开(公告)号：US07349268B2
公开(公告)日：2008-03-25
申请号：US11293890
申请日：2005-12-02
申请人： Hyong-Ryol Hwang , Young-Hyun Jun
发明人： Hyong-Ryol Hwang , Young-Hyun Jun
IPC分类号： G11C7/00
CPC分类号： G11C5/14
摘要： A voltage generation circuit and semiconductor memory device including the same are provided. The voltage generation circuit includes: a voltage level detector, which detects a level of a first high voltage to generate a first high voltage level detection signal and detects a level of a second high voltage to generate a second high voltage level detection signal; a control signal generator, which generates at least four pumping control signals in sequence when the first high voltage level detection signal is active, generates a control signal when the first high voltage level detection signal is inactive, and generates a first one of the at least four pumping control signals in response to a level of a power supply voltage; and a voltage generator, which pumps a boost node in response to the at least four pumping control signals to generate the first high voltage and transmits charge from the boost node to a second high voltage generation terminal in response to the control signal to generate the second high voltage.
摘要翻译：提供了包括该电压产生电路和半导体存储器件的电压产生电路。电压产生电路包括：电压电平检测器，其检测第一高电平的电平以产生第一高电压电平检测信号，并检测第二高电平的电平以产生第二高电压电平检测信号; 控制信号发生器，当所述第一高电压电平检测信号有效时，依次产生至少四个泵送控制信号，当所述第一高电压电平检测信号无效时产生控制信号，并且产生至少四个泵送控制信号响应于电源电压的电平; 以及电压发生器，其响应于所述至少四个泵送控制信号泵送升压节点以产生所述第一高电压，并且响应于所述控制信号将电压从所述升压节点传输到第二高电压发生端子，以产生所述第二高电压高压。

7. 发明授权

US07505353B2 Multi-port semiconductor memory device having variable access paths and method 有权
标题翻译：具有可变存取路径和方法的多端口半导体存储器件
公开(公告)号：US07505353B2
公开(公告)日：2009-03-17
申请号：US11466389
申请日：2006-08-22
申请人： Nam-Jong Kim , Ho-Cheol Lee , Kyoung-Hwan Kwon , Hyong-Ryol Hwang , Hyo-Joo Ahn
发明人： Nam-Jong Kim , Ho-Cheol Lee , Kyoung-Hwan Kwon , Hyong-Ryol Hwang , Hyo-Joo Ahn
IPC分类号： G11C8/00 , G11C8/12 , G11C8/16 , G11C7/10
CPC分类号： G11C8/12 , G11C7/1075 , G11C29/1201 , G11C29/26 , G11C29/48 , G11C2029/1802
摘要： A multi-port semiconductor memory device having variable access paths and a method therefore are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports.
摘要翻译：提供具有可变存取路径的多端口半导体存储器件及其方法。半导体存储器件包括多个输入/输出端口; 分成多个存储区域的存储器阵列; 以及选择控制单元，用于可变地控制存储区域和输入/输出端口之间的访问路径，使得通过至少一个输入/输出端口访问每个存储器区域。

8. 发明授权

US06795369B2 Address buffer and semiconductor memory device using the same 失效
标题翻译：地址缓冲器和使用其的半导体存储器件
公开(公告)号：US06795369B2
公开(公告)日：2004-09-21
申请号：US10303409
申请日：2002-11-22
申请人： Jong Hyun Choi , Jae-Young Lee , Hyong-Ryol Hwang
发明人： Jong Hyun Choi , Jae-Young Lee , Hyong-Ryol Hwang
IPC分类号： G11C800
CPC分类号： G11C8/18 , G11C8/06
摘要： The present invention discloses an address buffer and a semiconductor memory device having the address buffer. The address buffer comprises a first buffer for latching a signal in response to a first control signal in a normal operation mode in the semiconductor memory device and generating a buffered signal by buffering the latched signal in response to a second control signal, and a second buffer for maintaining a mode-setting signal in a reset status in the normal operation mode and for outputting the mode-setting signal by using the latched signal in response to the first control signal and a mode-setting command in a mode-setting operation mode. Accordingly, the mode-setting signal is generated only in the mode-setting operation mode, thereby reducing undesirable current consumption.
摘要翻译：本发明公开了一种地址缓冲器和具有地址缓冲器的半导体存储器件。地址缓冲器包括：第一缓冲器，用于响应于在半导体存储器件中的正常操作模式中的第一控制信号来锁存信号，并且通过响应于第二控制信号缓冲锁存信号并产生缓冲信号;以及第二缓冲器用于在正常操作模式中将模式设置信号保持在复位状态，并且在模式设置操作模式中响应于第一控制信号和模式设置命令，通过使用锁存信号来输出模式设置信号。因此，仅在模式设定操作模式下产生模式设定信号，从而减少不期望的电流消耗。

9. 发明申请

US20100232249A1 MULTI-PORT SEMICONDUCTOR MEMORY DEVICE HAVING VARIABLE ACCESS PATHS AND METHOD THEREFOR 有权
标题翻译：具有可变存取码的多端口半导体存储器件及其方法
公开(公告)号：US20100232249A1
公开(公告)日：2010-09-16
申请号：US12785832
申请日：2010-05-24
申请人： Nam-Jong Kim , Ho-Cheol Lee , Kyoung-Hwan Kwon , Hyong-Ryol Hwang , Hyo-Joo Ahn
发明人： Nam-Jong Kim , Ho-Cheol Lee , Kyoung-Hwan Kwon , Hyong-Ryol Hwang , Hyo-Joo Ahn
IPC分类号： G11C8/16 , G11C8/00
CPC分类号： G11C8/12 , G11C7/1075 , G11C29/1201 , G11C29/26 , G11C29/48 , G11C2029/1802
摘要： A multi-port semiconductor memory device having variable access paths and a method therefor are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports.
摘要翻译：提供一种具有可变访问路径的多端口半导体存储器件及其方法。半导体存储器件包括多个输入/输出端口; 分成多个存储区域的存储器阵列; 以及选择控制单元，用于可变地控制存储区域和输入/输出端口之间的访问路径，使得通过至少一个输入/输出端口访问每个存储器区域。

10. 发明授权

US07606982B2 Multi-path accessible semiconductor memory device having data transmission mode between ports 有权
标题翻译：具有在端口之间的数据传输模式的多路径可访问半导体存储器件
公开(公告)号：US07606982B2
公开(公告)日：2009-10-20
申请号：US11466406
申请日：2006-08-22
申请人： Hyong-Ryol Hwang , Sang-Kyun Park
发明人： Hyong-Ryol Hwang , Sang-Kyun Park
IPC分类号： G06F12/00
CPC分类号： G11C7/1075 , G11C8/16
摘要： A semiconductor memory device including a plurality of ports, at least one shared memory region of a memory cell array accessible through the ports, and a data transmission controller coupled to the shared memory region and the ports. The data transmission controller is configured to apply a read command of a read operation to the shared memory region after a write command of a write operation before applying any other commands to the shared memory region when at least a portion of a write address associated with the write operation and at least a portion of a read address associated with the read operation are substantially equivalent.
摘要翻译：一种包括多个端口的半导体存储器件，可通过端口访问的存储器单元阵列的至少一个共享存储器区域，以及耦合到共享存储器区域和端口的数据传输控制器。所述数据传输控制器被配置为在与所述共享存储器区域相关联的写入地址的至少一部分与所述共享存储器区域相关联的写入地址的至少一部分之前，在写入操作的写入命令之后，向所述共享存储器区域应用读取操作的读取命令写入操作和与读取操作相关联的读取地址的至少一部分基本相同。

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