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1. 发明授权

US07606982B2 Multi-path accessible semiconductor memory device having data transmission mode between ports 有权
标题翻译：具有在端口之间的数据传输模式的多路径可访问半导体存储器件
公开(公告)号：US07606982B2
公开(公告)日：2009-10-20
申请号：US11466406
申请日：2006-08-22
申请人： Hyong-Ryol Hwang , Sang-Kyun Park
发明人： Hyong-Ryol Hwang , Sang-Kyun Park
IPC分类号： G06F12/00
CPC分类号： G11C7/1075 , G11C8/16
摘要： A semiconductor memory device including a plurality of ports, at least one shared memory region of a memory cell array accessible through the ports, and a data transmission controller coupled to the shared memory region and the ports. The data transmission controller is configured to apply a read command of a read operation to the shared memory region after a write command of a write operation before applying any other commands to the shared memory region when at least a portion of a write address associated with the write operation and at least a portion of a read address associated with the read operation are substantially equivalent.
摘要翻译：一种包括多个端口的半导体存储器件，可通过端口访问的存储器单元阵列的至少一个共享存储器区域，以及耦合到共享存储器区域和端口的数据传输控制器。所述数据传输控制器被配置为在与所述共享存储器区域相关联的写入地址的至少一部分与所述共享存储器区域相关联的写入地址的至少一部分之前，在写入操作的写入命令之后，向所述共享存储器区域应用读取操作的读取命令写入操作和与读取操作相关联的读取地址的至少一部分基本相同。

2. 发明授权

US08395953B2 Bit-line sense amplifier, semiconductor memory device having the same, and method of testing bit-line micro-bridge defect 有权
标题翻译：位线读出放大器，具有相同的半导体存储器件以及测试位线微桥缺陷的方法
公开(公告)号：US08395953B2
公开(公告)日：2013-03-12
申请号：US12958726
申请日：2010-12-02
申请人： Cheol Kim , Sang-Kyun Park , Jung-Bae Lee , Jun-Phyo Lee
发明人： Cheol Kim , Sang-Kyun Park , Jung-Bae Lee , Jun-Phyo Lee
IPC分类号： G11C7/00
CPC分类号： G11C11/4091 , G11C29/025 , G11C29/12005 , G11C29/1201 , G11C2029/1204
摘要： The bit-line sense amplifier includes a driving-voltage control circuit and an amplifier. The driving-voltage control circuit generates a first test driving voltage having a voltage level of a pre-charge voltage, a second test driving voltage having a voltage level of a pre-charge voltage added by a voltage difference between a bit-line and a complementary bit-line, and a third test driving voltage having a voltage level of a pre-charge voltage subtracted by the voltage difference in a test mode. The amplifier senses and amplifies a voltage difference between the bit-line and the complementary bit-line.
摘要翻译：位线读出放大器包括驱动电压控制电路和放大器。驱动电压控制电路产生具有预充电电压的电压电平的第一测试驱动电压，具有由位线和位线之间的电压差相加的预充电电压的电压电平的第二测试驱动电压以及第三测试驱动电压，其具有在测试模式下被电压差减去的预充电电压的电压电平。放大器感测并放大位线和互补位线之间的电压差。

3. 发明申请

US20110199836A1 BIT-LINE SENSE AMPLIFIER, SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME, AND METHOD OF TESTING BIT-LINE MICRO-BRIDGE DEFECT 有权
标题翻译：双线感测放大器，具有相同功能的半导体存储器件以及测试位线微桥缺陷的方法
公开(公告)号：US20110199836A1
公开(公告)日：2011-08-18
申请号：US12958726
申请日：2010-12-02
申请人： Cheol Kim , Sang-Kyun Park , Jung-Bae Lee , Jun-Phyo Lee
发明人： Cheol Kim , Sang-Kyun Park , Jung-Bae Lee , Jun-Phyo Lee
IPC分类号： G11C29/12 , G11C7/10
CPC分类号： G11C11/4091 , G11C29/025 , G11C29/12005 , G11C29/1201 , G11C2029/1204
摘要： The bit-line sense amplifier includes a driving-voltage control circuit and an amplifier. The driving-voltage control circuit generates a first test driving voltage having a voltage level of a pre-charge voltage, a second test driving voltage having a voltage level of a pre-charge voltage added by a voltage difference between a bit-line and a complementary bit-line, and a third test driving voltage having a voltage level of a pre-charge voltage subtracted by the voltage difference in a test mode. The amplifier senses and amplifies a voltage difference between the bit-line and the complementary bit-line.
摘要翻译：位线读出放大器包括驱动电压控制电路和放大器。驱动电压控制电路产生具有预充电电压的电压电平的第一测试驱动电压，具有由位线和位线之间的电压差相加的预充电电压的电压电平的第二测试驱动电压以及第三测试驱动电压，其具有在测试模式下被电压差减去的预充电电压的电压电平。放大器感测并放大位线和互补位线之间的电压差。

4. 发明申请

US20090116327A1 Redundancy program circuit and methods thereof 有权
公开(公告)号：US20090116327A1
公开(公告)日：2009-05-07
申请号：US12314970
申请日：2008-12-19
申请人： Jeong-Sik Nam , Sang-Kyun Park , Kwang-Hyun Kim , Byung-Sik Moon , Won-Chang Jung
发明人： Jeong-Sik Nam , Sang-Kyun Park , Kwang-Hyun Kim , Byung-Sik Moon , Won-Chang Jung
IPC分类号： G11C17/16
CPC分类号： G11C29/812 , G11C29/785 , G11C29/787
摘要： A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control fuse circuit outputting an operating status signal for the at least one control fuse and a multiplexing unit configured to multiplex decoding address signal bits based on at least one of the operating status signal and the operation enable signal.

5. 发明授权

US07307910B2 Redundancy program circuit and methods thereof 有权
标题翻译：冗余编程电路及其方法
公开(公告)号：US07307910B2
公开(公告)日：2007-12-11
申请号：US11169831
申请日：2005-06-30
申请人： Jeong-Sik Nam , Sang-Kyun Park , Kwang-Hyun Kim , Byung-Sik Moon , Won-Chang Jung
发明人： Jeong-Sik Nam , Sang-Kyun Park , Kwang-Hyun Kim , Byung-Sik Moon , Won-Chang Jung
IPC分类号： G11C17/18
CPC分类号： G11C29/812 , G11C29/785 , G11C29/787
摘要： A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control fuse circuit outputting an operating status signal for the at least one control fuse and a multiplexing unit configured to multiplex decoding address signal bits based on at least one of the operating status signal and the operation enable signal.
摘要翻译：一种冗余程序电路及其方法。冗余程序电路可以包括具有主熔丝的主熔丝电路，其输出用于指示主熔丝运行状态的操作使能信号，至少一个控制熔丝电路，包括至少一个控制熔丝，所述至少一个控制熔丝电路输出操作用于所述至少一个控制熔丝的状态信号和被配置为基于所述操作状态信号和所述操作使能信号中的至少一个来复用解码地址信号位的复用单元。

6. 发明申请

US20070208902A1 MEMORY EXPANSION STRUCTURE IN MULTI-PATH ACCESSIBLE SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：多路可访问半导体存储器件中的存储器扩展结构
公开(公告)号：US20070208902A1
公开(公告)日：2007-09-06
申请号：US11614877
申请日：2006-12-21
申请人： Sang-Kyun Park , Il-Man Bae , Han-Gu Sohn , Yun-Hee Shin
发明人： Sang-Kyun Park , Il-Man Bae , Han-Gu Sohn , Yun-Hee Shin
IPC分类号： G06F12/00
CPC分类号： G11C7/1075 , G11C5/025 , G11C7/1048 , G11C11/4093
摘要： A multiprocessor system includes a first processor coupled to a first bus, a second processor coupled to a second bus, a first memory coupled to the first bus and the second bus, and a second memory coupled to the second bus. The first processor is configured to access the first memory through the first bus, and the second processor is configured to access the first memory and the second memory through the second bus.
摘要翻译：多处理器系统包括耦合到第一总线的第一处理器，耦合到第二总线的第二处理器，耦合到第一总线和第二总线的第一存储器以及耦合到第二总线的第二存储器。第一处理器被配置为通过第一总线访问第一存储器，并且第二处理器被配置为通过第二总线访问第一存储器和第二存储器。

7. 发明授权

US08027675B2 Apparatus and method for controlling registration of mobile identification number of mobile communication terminals 失效
标题翻译：用于控制移动通信终端的移动识别号码的登记的装置和方法
公开(公告)号：US08027675B2
公开(公告)日：2011-09-27
申请号：US11116867
申请日：2005-04-28
申请人： Sang-Kyun Park
发明人： Sang-Kyun Park
IPC分类号： H04B1/16
CPC分类号： H04W8/26 , H04M2207/18 , H04W88/14 , H04W88/18
摘要： An apparatus and method for controlling registration of a mobile identification number (MIN) of a mobile communication terminal. A memory stores a table in which MIN groups uniquely assigned to common carriers are stored, and a MIN of a mobile communication terminal. An input device inputs a MIN to be stored in the memory. If the MIN stored in the memory is a default MIN, a controller replaces the MIN stored in the memory with the MIN input from the input device. If the MIN stored in the memory is not the default MIN and the input MIN belongs to a MIN group assigned to a common carrier corresponding to the stored MIN, the controller replaces the stored MIN with the input MIN.
摘要翻译：一种用于控制移动通信终端的移动标识号（MIN）的注册的装置和方法。存储器存储其中存储有唯一分配给公共载波的MIN组的表以及移动通信终端的MIN。输入设备输入要存储在存储器中的MIN。如果存储在存储器中的MIN是默认MIN，则控制器使用输入设备的MIN输入替换存储在存储器中的MIN。如果存储在存储器中的MIN不是默认MIN，并且输入MIN属于分配给与存储的MIN相对应的公共载体的MIN组，则控制器用输入的MIN替换存储的MIN。

8. 发明申请

US20110228624A1 SUB-WORD-LINE DRIVING CIRCUIT, SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME, AND METHOD OF CONTROLLING THE SAME 有权
标题翻译：副线驱动电路，具有它们的半导体存储器件及其控制方法
公开(公告)号：US20110228624A1
公开(公告)日：2011-09-22
申请号：US13019858
申请日：2011-02-02
申请人： Cheol Kim , Sang-Kyun Park , Jung-Bae Lee , Jun-Phyo Lee
发明人： Cheol Kim , Sang-Kyun Park , Jung-Bae Lee , Jun-Phyo Lee
IPC分类号： G11C8/08
CPC分类号： G11C8/14 , G11C8/08
摘要： Provided is a semiconductor memory device including a sub-word-line driving circuit capable of reducing an amount of leakage current due to coupling. The semiconductor memory device includes a word-line enable signal generating circuit and a sub-word-line driving circuit. The sub-word-line driving circuit provides a pull-down current path between a selected word line and ground for a pulse type period of time in a precharge mode following an active mode for the selected word line, generates a word line driving signal on the basis of a main word line driving signal, a first sub-word-line control signal, and a second sub-word-line control signal, and provides the word line driving signal to a memory cell array. The semiconductor memory device may reduce an amount of leakage current flowing to a ground through the sub-word-line driving circuit.
摘要翻译：提供了一种半导体存储器件，其包括能够减少由耦合引起的漏电流量的子字线驱动电路。半导体存储器件包括字线使能信号产生电路和子字线驱动电路。子字线驱动电路在所选字线的有效模式之后的预充电模式中的脉冲类型时段期间，在所选字线和地之间提供下拉电流路径，生成字线驱动信号主字线驱动信号的基础，第一子字线控制信号和第二子字线控制信号，并将字线驱动信号提供给存储单元阵列。半导体存储器件可以减少通过子字线驱动电路流向地的漏电流量。

9. 发明授权

US07984261B2 Memory expansion structure in multi-path accessible semiconductor memory device 失效
标题翻译：存储器扩展结构在多路径可访问半导体存储器件中
公开(公告)号：US07984261B2
公开(公告)日：2011-07-19
申请号：US11614877
申请日：2006-12-21
申请人： Sang-Kyun Park , Il-Man Bae , Han-Gu Sohn , Yun-Hee Shin
发明人： Sang-Kyun Park , Il-Man Bae , Han-Gu Sohn , Yun-Hee Shin
IPC分类号： G06F12/00
CPC分类号： G11C7/1075 , G11C5/025 , G11C7/1048 , G11C11/4093
摘要： A multiprocessor system includes a first processor coupled to a first bus, a second processor coupled to a second bus, a first memory coupled to the first bus and the second bus, and a second memory coupled to the second bus. The first processor is configured to access the first memory through the first bus, and the second processor is configured to access the first memory and the second memory through the second bus.
摘要翻译：多处理器系统包括耦合到第一总线的第一处理器，耦合到第二总线的第二处理器，耦合到第一总线和第二总线的第一存储器以及耦合到第二总线的第二存储器。第一处理器被配置为通过第一总线访问第一存储器，并且第二处理器被配置为通过第二总线访问第一存储器和第二存储器。

10. 发明授权

US07495206B2 Image sensor with stacked and bonded photo detection and peripheral circuit substrates 有权
标题翻译：具有堆叠和粘合光电检测和外围电路基板的图像传感器
公开(公告)号：US07495206B2
公开(公告)日：2009-02-24
申请号：US11321772
申请日：2005-12-28
申请人： Sang-Kyun Park
发明人： Sang-Kyun Park
IPC分类号： H01L31/00
CPC分类号： H01L27/14634 , H01L27/1464 , H01L27/1469
摘要： A complementary metal oxide semiconductor (CMOS) device with a three dimensional integration structure and a method for fabricating the same are provided. An image sensor includes a first substrate in which a photo detection device is formed; a second substrate in which a peripheral circuit is formed, wherein the first substrate and the second substrate are bonded through a plurality of bonding pads formed on both the first substrate and the second substrate, and a back side of the first substrate is turned upside down; and a microlens formed on a top portion of the back side of the first substrate.
摘要翻译：提供具有三维积分结构的互补金属氧化物半导体（CMOS）器件及其制造方法。图像传感器包括其中形成有光检测装置的第一基板; 其中形成有外围电路的第二基板，其中第一基板和第二基板通过形成在第一基板和第二基板上的多个接合焊盘接合，并且第一基板的背面被倒置 ; 以及形成在第一基板的背面的顶部上的微透镜。

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