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1. 发明授权

US6114899A Variable voltage driver circuit using current detector 有权
标题翻译：使用电流检测器的可变电压驱动电路
公开(公告)号：US6114899A
公开(公告)日：2000-09-05
申请号：US200450
申请日：1998-11-27
申请人： Ki-Ho Jang , Chang-Woon Choi
发明人： Ki-Ho Jang , Chang-Woon Choi
IPC分类号： G11C11/40 , G05F1/46 , G05F3/02
CPC分类号： G05F1/465
摘要： A variable voltage driver circuit using a current detector is disclosed. The circuit includes a voltage generator, a voltage detector for detecting an output voltage of the voltage generator, a delay unit connected with the voltage detector for feeding back a signal to the voltage generator, a pulse generator for receiving a signal from the voltage generator and generating a pulse, a current-pulse generator for detecting a current in accordance with a signal from the pulse generator, a voltage drop detector for detecting a voltage dropped in the signal from the current-pulse generator, a latch for storing a signal from the voltage drop detector, and an extra-voltage driver for supplying a current in accordance with a latch signal when the current is small. In the present invention, when a normal voltage is generated by the voltage generator, the current supplied from the driver is measured. As a result of the measurement, if the current is small, the current is supplied by driving the extra-voltage driver.
摘要翻译：公开了一种使用电流检测器的可变电压驱动电路。电路包括电压发生器，用于检测电压发生器的输出电压的电压检测器，与电压检测器连接的延迟单元，用于将信号反馈到电压发生器;脉冲发生器，用于接收来自电压发生器的信号;以及产生脉冲，根据来自脉冲发生器的信号检测电流的电流脉冲发生器，用于检测来自电流脉冲发生器的信号中下降的电压的电压降检测器，用于存储来自电流脉冲发生器的信号的锁存器电压降检测器和用于当电流小时根据锁存信号提供电流的额外电压驱动器。在本发明中，当通过电压发生器产生正常电压时，测量从驾驶员提供的电流。作为测量的结果，如果电流较小，则通过驱动超高压驱动器来提供电流。

2. 发明申请

US20070195630A1 Internal power voltage generating circuit in semiconductor memory device 有权
标题翻译：半导体存储器件内部电源电压产生电路
公开(公告)号：US20070195630A1
公开(公告)日：2007-08-23
申请号：US11646543
申请日：2006-12-28
申请人： Hyong-Ryol Hwang , Ki-Ho Jang
发明人： Hyong-Ryol Hwang , Ki-Ho Jang
IPC分类号： G11C5/14
CPC分类号： G11C5/147
摘要： A method and circuit are disclosed for generating an internal power voltage in a semiconductor memory device. The method includes receiving an external power voltage in an internal power voltage generating circuit and activating a power-up signal during a first period in the applied external power voltage rising to a desired level, powering-up the internal power voltage in relation to the external power voltage during the first period, and continuing the power-up of the internal power voltage during a second period following the first period, the second period extending beyond the deactivation of the power-up signal until receipt of an active command signal.
摘要翻译：公开了用于在半导体存储器件中产生内部电源电压的方法和电路。该方法包括在内部电源电压产生电路中接收外部电源电压，并且在施加的外部电源电压上升至期望电平的第一时段期间激活上电信号，将内部电源电压相对于外部电源并且在第一周期之后的第二周期期间继续上电内部电源电压，第二周期延长超过上电信号的去激活，直到接收到有效指令信号为止。

3. 发明申请

US20060164903A1 Semiconductor memory device having self refresh mode and related method of operation 有权
标题翻译：具有自刷新模式和相关操作方法的半导体存储器件
公开(公告)号：US20060164903A1
公开(公告)日：2006-07-27
申请号：US11328237
申请日：2006-01-10
申请人： Jung-Yong Choi , Young-Gu Kang , Ki-Ho Jang
发明人： Jung-Yong Choi , Young-Gu Kang , Ki-Ho Jang
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40615 , G11C2211/4067
摘要： A semiconductor memory device supporting a self refresh operation is disclosed and comprises an address buffer unit and an operation control unit. The address buffer unit may be enabled during the self refresh operation by a first external control signal to generate an internal address signal. The operation control unit controls the start of the self refresh operation in response to the internal address signal.
摘要翻译：公开了一种支持自刷新操作的半导体存储器件，包括地址缓冲器单元和操作控制单元。地址缓冲单元可以在自刷新操作期间由第一外部控制信号使能以产生内部地址信号。操作控制单元响应于内部地址信号控制自刷新操作的开始。

4. 发明授权

US07613063B2 Internal power voltage generating circuit in semiconductor memory device 有权
标题翻译：半导体存储器件内部电源电压产生电路
公开(公告)号：US07613063B2
公开(公告)日：2009-11-03
申请号：US11646543
申请日：2006-12-28
申请人： Hyong-Ryol Hwang , Ki-Ho Jang
发明人： Hyong-Ryol Hwang , Ki-Ho Jang
IPC分类号： G11C5/14
CPC分类号： G11C5/147
摘要： A method and circuit are disclosed for generating an internal power voltage in a semiconductor memory device. The method includes receiving an external power voltage in an internal power voltage generating circuit and activating a power-up signal during a first period in the applied external power voltage rising to a desired level, powering-up the internal power voltage in relation to the external power voltage during the first period, and continuing the power-up of the internal power voltage during a second period following the first period, the second period extending beyond the deactivation of the power-up signal until receipt of an active command signal.
摘要翻译：公开了用于在半导体存储器件中产生内部电源电压的方法和电路。该方法包括在内部电源电压产生电路中接收外部电源电压，并且在施加的外部电源电压上升至期望电平的第一时段期间激活上电信号，将内部电源电压相对于外部电源并且在第一周期之后的第二周期期间继续上电内部电源电压，第二周期延长超过上电信号的去激活，直到接收到有效指令信号为止。

5. 发明授权

US07190628B2 Semiconductor memory device having self refresh mode and related method of operation 有权
标题翻译：具有自刷新模式和相关操作方法的半导体存储器件
公开(公告)号：US07190628B2
公开(公告)日：2007-03-13
申请号：US11328237
申请日：2006-01-10
申请人： Jung-Yong Choi , Young-Gu Kang , Ki-Ho Jang
发明人： Jung-Yong Choi , Young-Gu Kang , Ki-Ho Jang
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40615 , G11C2211/4067
摘要： A semiconductor memory device supporting a self refresh operation is disclosed and comprises an address buffer unit and an operation control unit. The address buffer unit may be enabled during the self refresh operation by a first external control signal to generate an internal address signal. The operation control unit controls the start of the self refresh operation in response to the internal address signal.
摘要翻译：公开了一种支持自刷新操作的半导体存储器件，包括地址缓冲器单元和操作控制单元。地址缓冲单元可以在自刷新操作期间由第一外部控制信号使能以产生内部地址信号。操作控制单元响应于内部地址信号控制自刷新操作的开始。

6. 发明申请

US20050078548A1 Method and memory system in which operating mode is set using address signal 有权
标题翻译：方法和存储系统，其中使用地址信号设置工作模式
公开(公告)号：US20050078548A1
公开(公告)日：2005-04-14
申请号：US10951881
申请日：2004-09-29
申请人： Young-gu Kang , Jong-hyun Choi , Woo-seop Jeong , Ki-ho Jang , Jung-yong Choi
发明人： Young-gu Kang , Jong-hyun Choi , Woo-seop Jeong , Ki-ho Jang , Jung-yong Choi
IPC分类号： G11C11/409 , G11C7/00 , G11C7/10 , G11C29/46
CPC分类号： G11C7/1045 , G11C29/46
摘要： A memory system, memory device, and method for setting an operating mode of a memory device include a memory cell array; row and column decoders which select a row and a column of the memory cell array, respectively, according to a multi-bit address signal; and a mode control circuit which receives at least one bit from the multi-bit address signal used in the selection of the row or the column, and which sets an operating mode of the memory device according to the at least one bit, wherein the operating mode is one of a burst length mode, a DLL reset mode, a test mode, a CAS latency mode, and a burst type mode.
摘要翻译：用于设置存储器件的操作模式的存储器系统，存储器件和方法包括存储器单元阵列; 行和列解码器，其分别根据多位地址信号选择存储单元阵列的行和列; 以及模式控制电路，其从在行或列的选择中使用的多位地址信号接收至少一个位，并且根据至少一个位设置存储器件的操作模式，其中操作模式是突发长度模式，DLL复位模式，测试模式，CAS延迟模式和突发类型模式之一。

7. 发明授权

US5810935A Apparatus for transferring a wafer 失效
标题翻译：用于传送晶片的装置
公开(公告)号：US5810935A
公开(公告)日：1998-09-22
申请号：US564575
申请日：1995-11-29
申请人： Jong-Hyun Lee , Hyung-Joun Yoo , Boo-Yeon Choi , Won-Ick Jang , Ki-Ho Jang
发明人： Jong-Hyun Lee , Hyung-Joun Yoo , Boo-Yeon Choi , Won-Ick Jang , Ki-Ho Jang
IPC分类号： B65G49/07 , B25J15/08 , H01L21/677 , H01L21/68 , H01L21/687 , C23C16/00
CPC分类号： H01L21/68707 , Y10S414/136 , Y10S414/137 , Y10S414/139 , Y10S414/141
摘要： An apparatus for transferring a wafer in a semiconductor manufacturing process, and for carrying a wafer between a cassette and a wafer chuck without an additional tool such as a tripod. The apparatus includes: a holder capable of holding the side of the wafer; a wafer transfer assembly including an actuator of the holder and a detector that detects a malfunction of the holder; and a process reactor having a vacuum exhaust port installed under a wafer chuck so as to guide gas in an axially-symmetric flow pattern. The holder grasps the rounded side of a wafer. Removal of additional tools makes the structure of an overall system more simple and an exhaust port can be installed under the reactor so as to cause processing gas to be guided in an axially-symmetric flow, resulting in an enhancement of the process uniformity.
摘要翻译：一种用于在半导体制造工艺中转移晶片的装置，并且用于在没有诸如三脚架的附加工具之间将晶片携带在盒和晶片卡盘之间。该装置包括：能够保持晶片侧面的保持器; 晶片传送组件，其包括所述保持器的致动器和检测器，所述检测器检测所述保持器的故障; 以及具有安装在晶片卡盘下方的真空排气口以便引导轴向对称流动模式的气体的处理反应器。保持器抓住晶片的圆形侧。除去附加工具使得整个系统的结构更简单，并且排气口可以安装在反应器下方，以便使处理气体以轴向对称的流动被引导，导致工艺均匀性的提高。

8. 发明授权

US07042800B2 Method and memory system in which operating mode is set using address signal 有权
标题翻译：方法和存储系统，其中使用地址信号设置工作模式
公开(公告)号：US07042800B2
公开(公告)日：2006-05-09
申请号：US10951881
申请日：2004-09-29
申请人： Young-gu Kang , Jong-hyun Choi , Woo-seop Jeong , Ki-ho Jang , Jung-yong Choi
发明人： Young-gu Kang , Jong-hyun Choi , Woo-seop Jeong , Ki-ho Jang , Jung-yong Choi
IPC分类号： G11C8/00
CPC分类号： G11C7/1045 , G11C29/46
摘要： A memory system, memory device, and method for setting an operating mode of a memory device include a memory cell array; row and column decoders which select a row and a column of the memory cell array, respectively, according to a multi-bit address signal; and a mode control circuit which receives at least one bit from the multi-bit address signal used in the selection of the row or the column, and which sets an operating mode of the memory device according to the at least one bit, wherein the operating mode is one of a burst length mode, a DLL reset mode, a test mode, a CAS latency mode, and a burst type mode.
摘要翻译：用于设置存储器件的操作模式的存储器系统，存储器件和方法包括存储器单元阵列; 行和列解码器，其分别根据多位地址信号选择存储单元阵列的行和列; 以及模式控制电路，其从在行或列的选择中使用的多位地址信号接收至少一个位，并且根据至少一个位设置存储器件的操作模式，其中操作模式是突发长度模式，DLL复位模式，测试模式，CAS延迟模式和突发类型模式之一。

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