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1. 发明授权

US07777265B2 Semiconductor device having contact barrier and method of manufacturing the same 有权
标题翻译：具有接触屏障的半导体器件及其制造方法
公开(公告)号：US07777265B2
公开(公告)日：2010-08-17
申请号：US11933039
申请日：2007-10-31
申请人： Hyeong-Sun Hong , Jae-Goo Lee , Dong-Hyun Kim , Sung-Un Kwon , Sang-Joon Park , Nam-Jung Kang
发明人： Hyeong-Sun Hong , Jae-Goo Lee , Dong-Hyun Kim , Sung-Un Kwon , Sang-Joon Park , Nam-Jung Kang
IPC分类号： H01L27/108
CPC分类号： H01L27/0207 , H01L21/76802 , H01L27/10808 , H01L27/10855 , H01L27/10885 , Y10S257/905
摘要： A semiconductor device having a contact barrier for insulating contacts with a large aspect ratio and having a fine pitch between adjacent conductive lines and a method of manufacturing the same are provided. The semiconductor device includes a buried contact formed in a region between two adjacent first conductive lines and two adjacent second conductive lines. Insulating lines define a width of the buried contact. To form the contact barrier, an interlayer dielectric layer formed on the second conductive lines is patterned to form a space and an insulating line having an etching ratio different from the interlayer dielectric layer is formed in the space. The interlayer dielectric layer is selectively wet etched relative to an insulating layer covering the second conductive line and the first insulating line to form buried contact hole. The buried contact hole is filled with conductive material to form a buried contact.
摘要翻译：提供一种半导体器件，其具有用于具有大纵横比的绝缘触点的接触屏障，并且在相邻的导线之间具有微细的间距及其制造方法。半导体器件包括形成在两个相邻的第一导电线和两个相邻的第二导电线之间的区域中的掩埋接触。绝缘线限定埋入触点的宽度。为了形成接触屏障，形成在第二导线上的层间电介质层形成空间，并且在该空间中形成具有与层间电介质层不同的蚀刻比的绝缘线。相对于覆盖第二导线和第一绝缘线的绝缘层选择性地湿蚀刻层间电介质层以形成掩埋接触孔。埋入的接触孔填充有导电材料以形成掩埋接触。

2. 发明授权

US08378497B2 Contact structures and semiconductor devices including the same 有权
标题翻译：接触结构和包括其的半导体器件
公开(公告)号：US08378497B2
公开(公告)日：2013-02-19
申请号：US12758946
申请日：2010-04-13
申请人： Seong-Goo Kim , Hyeong-Sun Hong , Dong-Hyun Kim , Nam-Jung Kang
发明人： Seong-Goo Kim , Hyeong-Sun Hong , Dong-Hyun Kim , Nam-Jung Kang
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L29/4236 , H01L21/76829 , H01L21/76897 , H01L27/0207 , H01L27/10855 , H01L27/10876
摘要： Methods of forming a contact structure in a semiconductor device include providing a semiconductor substrate including active regions and word lines crossing the active regions. A first interlayer dielectric layer is formed on the semiconductor substrate. Direct contact plugs are formed extending through the first interlayer dielectric layer to contact selected ones of the active regions. Bit line structures are formed on the first interlayer dielectric layer and crossing the word lines that are coupled to the selected ones of the active regions by the direct contact plugs. A second interlayer dielectric layer is formed on the semiconductor substrate including the bit line structures. Barrier patterns are formed extending in parallel with bit line structures and into the second interlayer dielectric layer. Mask patterns are formed overlying an entirety of top surfaces of the direct contact plugs on the second interlayer dielectric layer and the bit line structures. The second and first interlayer dielectric layers are etched using the mask patterns, the barrier patterns and the bit line structures as an etching mask to form buried contact holes and buried contact plugs are formed in the buried contact holes.
摘要翻译：在半导体器件中形成接触结构的方法包括提供包括有源区和跨越有源区的字线的半导体衬底。在半导体衬底上形成第一层间电介质层。形成延伸穿过第一层间电介质层的直接接触插塞以接触所选择的有源区域。位线结构形成在第一层间电介质层上并且通过直接接触插塞与被选择的有源区域耦合的字线交叉。在包括位线结构的半导体衬底上形成第二层间电介质层。阻挡层图案形成为与位线结构平行延伸并进入第二层间电介质层。掩模图形形成在第二层间介质层上的直接接触插塞的整个顶表面和位线结构上。使用掩模图案蚀刻第二和第一层间电介质层，将掩模图案和位线结构作为蚀刻掩模形成埋入的接触孔，并且在埋入的接触孔中形成掩埋的接触插塞。

3. 发明申请

US20100193966A1 Contact Structures and Semiconductor Devices Including the Same 有权
标题翻译：接触结构和包括其的半导体器件
公开(公告)号：US20100193966A1
公开(公告)日：2010-08-05
申请号：US12758946
申请日：2010-04-13
申请人： Seong-Goo Kim , Hyeong-Sun Hong , Dong-Hyun Kim , Nam-Jung Kang
发明人： Seong-Goo Kim , Hyeong-Sun Hong , Dong-Hyun Kim , Nam-Jung Kang
IPC分类号： H01L23/538
CPC分类号： H01L29/4236 , H01L21/76829 , H01L21/76897 , H01L27/0207 , H01L27/10855 , H01L27/10876
摘要： Methods of forming a contact structure in a semiconductor device include providing a semiconductor substrate including active regions and word lines crossing the active regions. A first interlayer dielectric layer is formed on the semiconductor substrate. Direct contact plugs are formed extending through the first interlayer dielectric layer to contact selected ones of the active regions. Bit line structures are formed on the first interlayer dielectric layer and crossing the word lines that are coupled to the selected ones of the active regions by the direct contact plugs. A second interlayer dielectric layer is formed on the semiconductor substrate including the bit line structures. Barrier patterns are formed extending in parallel with bit line structures and into the second interlayer dielectric layer. Mask patterns are formed overlying an entirety of top surfaces of the direct contact plugs on the second interlayer dielectric layer and the bit line structures. The second and first interlayer dielectric layers are is etched using the mask patterns, the barrier patterns and the bit line structures as an etching mask to form buried contact holes and buried contact plugs are formed in the buried contact holes.
摘要翻译：在半导体器件中形成接触结构的方法包括提供包括有源区和跨越有源区的字线的半导体衬底。在半导体衬底上形成第一层间电介质层。形成延伸穿过第一层间电介质层的直接接触插塞以接触所选择的有源区域。位线结构形成在第一层间电介质层上并且通过直接接触插塞与被选择的有源区域耦合的字线交叉。在包括位线结构的半导体衬底上形成第二层间电介质层。阻挡层图案形成为与位线结构平行延伸并进入第二层间电介质层。掩模图形形成在第二层间介质层上的直接接触插塞的整个顶表面和位线结构上。使用掩模图案蚀刻第二和第一层间电介质层，将掩模图案和位线结构作为蚀刻掩模形成掩埋的接触孔，并且在埋入的接触孔中形成掩埋的接触塞。

4. 发明申请

US20080283957A1 Method of Fabricating Semiconductor Device Having Self-Aligned Contact Plug and Related Device 失效
标题翻译：具有自对准接触插头及相关器件的半导体器件制造方法
公开(公告)号：US20080283957A1
公开(公告)日：2008-11-20
申请号：US12112438
申请日：2008-04-30
申请人： Nam-Jung Kang , Dong-Soo Woo , Hyeong-Sun Hong , Dong-Hyun Kim
发明人： Nam-Jung Kang , Dong-Soo Woo , Hyeong-Sun Hong , Dong-Hyun Kim
IPC分类号： H01L29/00 , H01L21/4763
CPC分类号： H01L27/10888 , H01L21/76897 , H01L27/10855
摘要： Methods of fabricating a semiconductor device having a self-aligned contact plug are provided. Methods include forming a lower insulating layer on a semiconductor substrate, forming a plurality of interconnection patterns parallel to each other on the lower insulating layer; forming an upper insulating layer that is configured to fill between the interconnection patterns, and forming a plurality of first mask patterns crossing the plurality of interconnection patterns, ones of the plurality of first mask patterns parallel to each other on the semiconductor substrate having the upper insulating layer. Methods may include forming a second mask pattern that is self-aligned to the plurality of first mask patterns and that is between ones of the plurality of first mask patterns, etching the upper insulating layer and the lower insulating layer using the first and second mask patterns and the plurality of interconnection patterns as etch masks to form a plurality of contact holes exposing the semiconductor substrate, and forming a plurality of contact plugs in respective ones of the plurality of contact holes. Semiconductor devices are also provided.
摘要翻译：提供制造具有自对准接触插头的半导体器件的方法。方法包括在半导体衬底上形成下绝缘层，在下绝缘层上形成彼此平行的多个互连图案; 形成上部绝缘层，其被构造成填充在所述互连图案之间，并且形成与所述多个互连图案交叉的多个第一掩模图案，所述多个第一掩模图案中的所述第一掩模图案在具有所述上绝缘体的半导体衬底上彼此平行层。方法可以包括形成第二掩模图案，该第二掩模图案与多个第一掩模图案自对准，并且位于多个第一掩模图案之间，使用第一和第二掩模图案蚀刻上绝缘层和下绝缘层以及所述多个互连图案作为蚀刻掩模，以形成暴露所述半导体衬底的多个接触孔，以及在所述多个接触孔中的相应接触孔中形成多个接触插塞。还提供了半导体器件。

5. 发明授权

US07799643B2 Method of fabricating semiconductor device having self-aligned contact plug 失效
标题翻译：制造具有自对准接触插头的半导体器件的方法
公开(公告)号：US07799643B2
公开(公告)日：2010-09-21
申请号：US12112438
申请日：2008-04-30
申请人： Nam-Jung Kang , Dong-Soo Woo , Hyeong-Sun Hong , Dong-Hyun Kim
发明人： Nam-Jung Kang , Dong-Soo Woo , Hyeong-Sun Hong , Dong-Hyun Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/10888 , H01L21/76897 , H01L27/10855
摘要： Methods of fabricating a semiconductor device having a self-aligned contact plug are provided. Methods include forming a lower insulating layer on a semiconductor substrate, forming a plurality of interconnection patterns parallel to each other on the lower insulating layer; forming an upper insulating layer that is configured to fill between the interconnection patterns, and forming a plurality of first mask patterns crossing the plurality of interconnection patterns, ones of the plurality of first mask patterns parallel to each other on the semiconductor substrate having the upper insulating layer. Methods may include forming a second mask pattern that is self-aligned to the plurality of first mask patterns and that is between ones of the plurality of first mask patterns, etching the upper insulating layer and the lower insulating layer using the first and second mask patterns and the plurality of interconnection patterns as etch masks to form a plurality of contact holes exposing the semiconductor substrate, and forming a plurality of contact plugs in respective ones of the plurality of contact holes. Semiconductor devices are also provided.
摘要翻译：提供制造具有自对准接触插头的半导体器件的方法。方法包括在半导体衬底上形成下绝缘层，在下绝缘层上形成彼此平行的多个互连图案; 形成上部绝缘层，其被构造成填充在所述互连图案之间，并且形成与所述多个互连图案交叉的多个第一掩模图案，所述多个第一掩模图案中的所述第一掩模图案在所述半导体衬底上彼此平行，层。方法可以包括形成第二掩模图案，该第二掩模图案与多个第一掩模图案自对准，并且在多个第一掩模图案中的一个之间，使用第一和第二掩模图案蚀刻上绝缘层和下绝缘层以及所述多个互连图案作为蚀刻掩模，以形成暴露所述半导体衬底的多个接触孔，以及在所述多个接触孔中的相应接触孔中形成多个接触插塞。还提供了半导体器件。

6. 发明授权

US07713873B2 Methods of forming contact structures semiconductor devices 有权
标题翻译：形成接触结构半导体器件的方法
公开(公告)号：US07713873B2
公开(公告)日：2010-05-11
申请号：US12151997
申请日：2008-05-12
申请人： Seong-Goo Kim , Hyeong-Sun Hong , Dong-Hyun Kim , Nam-Jung Kang
发明人： Seong-Goo Kim , Hyeong-Sun Hong , Dong-Hyun Kim , Nam-Jung Kang
IPC分类号： H01L21/44
CPC分类号： H01L29/4236 , H01L21/76829 , H01L21/76897 , H01L27/0207 , H01L27/10855 , H01L27/10876
摘要： Methods of forming a contact structure in a semiconductor device include providing a semiconductor substrate including active regions and word lines crossing the active regions. A first interlayer dielectric layer is formed on the semiconductor substrate. Direct contact plugs are formed extending through the first interlayer dielectric layer to contact selected ones of the active regions. Bit line structures are formed on the first interlayer dielectric layer and crossing the word lines that are coupled to the selected ones of the active regions by the direct contact plugs. A second interlayer dielectric layer is formed on the semiconductor substrate including the bit line structures. Barrier patterns are formed extending in parallel with bit line structures and into the second interlayer dielectric layer. Mask patterns are formed overlying an entirety of top surfaces of the direct contact plugs on the second interlayer dielectric layer and the bit line structures. The second and first interlayer dielectric layers are etched using the mask patterns, the barrier patterns and the bit line structures as an etching mask to form buried contact holes and buried contact plugs are formed in the buried contact holes.
摘要翻译：在半导体器件中形成接触结构的方法包括提供包括有源区和跨越有源区的字线的半导体衬底。在半导体衬底上形成第一层间电介质层。形成延伸穿过第一层间电介质层的直接接触插塞以接触所选择的有源区域。位线结构形成在第一层间电介质层上并且通过直接接触插塞与被选择的有源区域耦合的字线交叉。在包括位线结构的半导体衬底上形成第二层间电介质层。阻挡层图案形成为与位线结构平行延伸并进入第二层间电介质层。掩模图形形成在第二层间介质层上的直接接触插塞的整个顶表面和位线结构上。使用掩模图案蚀刻第二和第一层间电介质层，将掩模图案和位线结构作为蚀刻掩模形成埋入的接触孔，并且在埋入的接触孔中形成掩埋的接触插塞。

7. 发明申请

US20080284029A1 Contact structures and semiconductor devices including the same and methods of forming the same 有权
标题翻译：接触结构和包括其的半导体器件及其形成方法
公开(公告)号：US20080284029A1
公开(公告)日：2008-11-20
申请号：US12151997
申请日：2008-05-12
申请人： Seong-Goo Kim , Hyeong-Sun Hong , Dong-Hyun Kim , Nam-Jung Kang
发明人： Seong-Goo Kim , Hyeong-Sun Hong , Dong-Hyun Kim , Nam-Jung Kang
IPC分类号： H01L21/768 , H01L23/522
CPC分类号： H01L29/4236 , H01L21/76829 , H01L21/76897 , H01L27/0207 , H01L27/10855 , H01L27/10876
摘要： Methods of forming a contact structure in a semiconductor device include providing a semiconductor substrate including active regions and word lines crossing the active regions. A first interlayer dielectric layer is formed on the semiconductor substrate. Direct contact plugs are formed extending through the first interlayer dielectric layer to contact selected ones of the active regions. Bit line structures are formed on the first interlayer dielectric layer and crossing the word lines that are coupled to the selected ones of the active regions by the direct contact plugs. A second interlayer dielectric layer is formed on the semiconductor substrate including the bit line structures. Barrier patterns are formed extending in parallel with bit line structures and into the second interlayer dielectric layer. Mask patterns are formed overlying an entirety of top surfaces of the direct contact plugs on the second interlayer dielectric layer and the bit line structures. The second and first interlayer dielectric layers are etched using the mask patterns, the barrier patterns and the bit line structures as an etching mask to form buried contact holes and buried contact plugs are formed in the buried contact holes.
摘要翻译：在半导体器件中形成接触结构的方法包括提供包括有源区和跨越有源区的字线的半导体衬底。在半导体衬底上形成第一层间电介质层。形成延伸穿过第一层间电介质层的直接接触插塞以接触所选择的有源区域。位线结构形成在第一层间电介质层上并且通过直接接触插塞与被选择的有源区域耦合的字线交叉。在包括位线结构的半导体衬底上形成第二层间电介质层。阻挡层图案形成为与位线结构平行延伸并进入第二层间电介质层。掩模图形形成在第二层间介质层上的直接接触插塞的整个顶表面和位线结构上。使用掩模图案蚀刻第二和第一层间电介质层，将掩模图案和位线结构作为蚀刻掩模形成埋入的接触孔，并且在埋入的接触孔中形成掩埋的接触插塞。

8. 发明授权

US08810036B2 Semiconductor device and method forming patterns with spaced pads in trim region 有权
标题翻译：半导体器件和方法在修剪区域中形成具有间隔垫的图案
公开(公告)号：US08810036B2
公开(公告)日：2014-08-19
申请号：US13604723
申请日：2012-09-06
申请人： Jin-Ho Min , Ki-Jeong Kim , Kyoung-Sub Shin , Dong-Hyun Kim
发明人： Jin-Ho Min , Ki-Jeong Kim , Kyoung-Sub Shin , Dong-Hyun Kim
IPC分类号： H01L23/52 , H01L23/48 , H01L23/528 , H01L27/32
CPC分类号： H01L27/11517 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L27/0203 , H01L27/11519 , H01L27/11524 , H01L27/11548 , H01L27/11565 , H01L27/1157 , H01L27/11575 , H01L27/3276
摘要： In a semiconductor device, parallel first and second conductive lines having a unit width extend from a memory cell region into a connection region. A trim region in the connection region includes pads respectively connected to the first and second conductive lines but are separated by a width much greater than the unit width.
摘要翻译：在半导体器件中，具有单位宽度的并行的第一和第二导线从存储单元区域延伸到连接区域。连接区域中的修剪区域包括分别连接到第一和第二导电线但是被分开的宽度远大于单位宽度的焊盘。

9. 发明授权

US08530954B2 Non-volatile memory devices including first and second blocking layer patterns 有权
标题翻译：包括第一和第二阻挡层图案的非易失性存储器件
公开(公告)号：US08530954B2
公开(公告)日：2013-09-10
申请号：US12491529
申请日：2009-06-25
申请人： Dong-Hyun Kim , Chang-Jin Kang
发明人： Dong-Hyun Kim , Chang-Jin Kang
IPC分类号： H01L29/792
CPC分类号： H01L21/28282
摘要： Non-volatile memory devices include a tunnel insulating layer on a channel region of a substrate, a charge-trapping layer pattern on the tunnel insulating layer and a first blocking layer pattern on the charge-trapping layer pattern. Second blocking layer patterns are on the tunnel insulating layer proximate sidewalls of the charge-trapping layer pattern. The second blocking layer patterns are configured to limit lateral diffusion of electrons trapped in the charge-trapping layer pattern. A gate electrode is on the first blocking layer pattern. The second blocking layer patterns may prevent lateral diffusion of the electrons trapped in the charge-trapping layer pattern.
摘要翻译：非易失性存储器件包括在衬底的沟道区上的隧道绝缘层，隧道绝缘层上的电荷俘获层图案和电荷俘获层图案上的第一阻挡层图案。第二阻挡层图案位于邻近电荷俘获层图案侧壁的隧道绝缘层上。第二阻挡层图案被配置为限制捕获在电荷俘获层图案中的电子的横向扩散。栅电极位于第一阻挡层图案上。第二阻挡层图案可以防止捕获在电荷俘获层图案中的电子的横向扩散。

10. 发明授权

US08266080B2 Virtual measuring device and method 有权
标题翻译：虚拟测量装置及方法
公开(公告)号：US08266080B2
公开(公告)日：2012-09-11
申请号：US12354356
申请日：2009-01-15
申请人： Won-Hyouk Jang , Joo-Hwa Lee , Dong-Hyun Kim , Hyo-Jin Han , Kil-Ho Ok , Sung-Hoon Kim
发明人： Won-Hyouk Jang , Joo-Hwa Lee , Dong-Hyun Kim , Hyo-Jin Han , Kil-Ho Ok , Sung-Hoon Kim
IPC分类号： G06F15/18
CPC分类号： G01B11/0641 , G01B11/0683 , H01L22/12 , H01L22/20
摘要： A virtual measuring device and a method for measuring the deposition thickness of amorphous silicon being deposited on a substrate is disclosed, where the method of measuring the deposition thickness of amorphous silicon includes predicting and adapting operations. In the predicting operation, during a process of depositing the amorphous silicon to a substrate, the deposition thickness is predicted by multiplying a predicted deposition speed to a deposition time by using a prediction model expressing a relationship between a deposition speed and a plurality of process factors that are correlated with the deposition speed obtained from the deposition thickness and the deposition time, and the predicted deposition thickness is compared with the measured deposition thickness, so that the relationship between the plurality of process factors and the deposition speed in the prediction model is compensated according to the comparison difference.
摘要翻译：公开了一种用于测量沉积在衬底上的非晶硅的沉积厚度的虚拟测量装置和方法，其中测量非晶硅的沉积厚度的方法包括预测和适应操作。在预测操作中，在将非晶硅沉积到衬底的过程中，通过使用表示沉积速度和多个工艺因素之间的关系的预测模型将预测的沉积速度乘以沉积时间来预测沉积厚度与从沉积厚度和沉积时间获得的沉积速度相关联，并将预测的沉积厚度与测量的沉积厚度进行比较，使得多个工艺因素之间的关系和预测模型中的沉积速度被补偿根据比较差异。

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