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1. 发明申请

US20110186923A1 SEMICONDUCTOR MEMORY DEVICE HAVING VERTICAL CHANNEL TRANSISTOR AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：具有垂直通道晶体管的半导体存储器件及其制造方法
公开(公告)号：US20110186923A1
公开(公告)日：2011-08-04
申请号：US13085898
申请日：2011-04-13
申请人： Hyeoung-won Seo , Bong-soo Kim , Dong-gun Park , Kang-yoon Lee , Jae-man Yoon , Seong-goo Kim , Seung-bae Park
发明人： Hyeoung-won Seo , Bong-soo Kim , Dong-gun Park , Kang-yoon Lee , Jae-man Yoon , Seong-goo Kim , Seung-bae Park
IPC分类号： H01L29/78
CPC分类号： H01L27/0207 , H01L27/10814 , H01L27/10823 , H01L27/10876 , H01L27/10888 , H01L27/10891
摘要： Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated
摘要翻译：两个晶体管的沟道垂直地形成在一个有源区的两个相对的侧表面的部分上，并且栅极垂直地形成在与有源区的沟道接触的器件隔离层上。在有源区域的中心部分形成共同的位线接触插塞，在位线接触插塞的两侧形成两个存储节点接触插塞，并且在位线接触插头的侧面上形成绝缘间隔件。像现有的半导体存储器件一样，在半导体衬底上顺序层叠字线，位线和电容器。因此，存储单元的有效空间布置是可能的，使得构成4F2结构，并且可以应用常规的线和接触形成工艺，使得容易制造高度集成的半导体存储器件

2. 发明授权

US07439581B2 Transistors, semiconductor integrated circuit interconnections and methods of forming the same 有权
公开(公告)号：US07439581B2
公开(公告)日：2008-10-21
申请号：US11704364
申请日：2007-02-09
申请人： Seong-Goo Kim , Kang-Yoon Lee , Yun-Gi Kim , Bong-Soo Kim
发明人： Seong-Goo Kim , Kang-Yoon Lee , Yun-Gi Kim , Bong-Soo Kim
IPC分类号： H01L29/76
CPC分类号： H01L23/485 , H01L21/823437 , H01L21/823462 , H01L21/823475 , H01L29/42336 , H01L29/4236 , H01L29/66621 , H01L2924/0002 , H01L2924/00
摘要： Provided are transistors, semiconductor integrated circuit interconnections and methods of forming the same. The transistors, semiconductor integrated circuit interconnections and methods of forming the same may improve electrical characteristics between gate electrodes or interconnection electrodes and simplify a semiconductor fabrication process related to gate electrodes or interconnection electrodes. A material layer having first and second regions may be prepared. A trench may be formed in a selected portion of the first region. Transistors or semiconductor integrated circuit interconnections may be in the first and second regions, respectively. One of the transistors or the semiconductor integrated circuit interconnections may be formed in the trench. The transistors or the semiconductor integrated circuit interconnections may be electrically insulated from each other.

3. 发明授权

US07411240B2 Integrated circuits including spacers that extend beneath a conductive line 有权
标题翻译：集成电路包括在导电线下方延伸的间隔物
公开(公告)号：US07411240B2
公开(公告)日：2008-08-12
申请号：US11170820
申请日：2005-06-30
申请人： Sung-Joon Park , Seong-Goo Kim
发明人： Sung-Joon Park , Seong-Goo Kim
IPC分类号： H01L21/8242
CPC分类号： H01L27/10855 , H01L21/76885 , H01L21/76897 , H01L23/53295 , H01L27/10814 , H01L27/10885 , H01L27/10888 , H01L2924/0002 , Y10S257/906 , H01L2924/00
摘要： Integrated circuit devices are fabricated by fabricating a conductive line on an insulating layer on an integrated circuit substrate. The conductive line includes a bottom adjacent the insulating layer, a top remote from the insulating layer and first and second sidewalls therebetween. An insulating spacer is formed to extend along the first and second sidewalls and to also extend along at least a portion of the bottom between the conductive line and the insulating layer. By providing an insulating spacer beneath at least a portion of the conductive line, insulation reliability may be improved even as the spacer may become narrower and/or the contact area may be enlarged.
摘要翻译：通过在集成电路基板上的绝缘层上制造导电线来制造集成电路器件。导线包括邻近绝缘层的底部，远离绝缘层的顶部以及它们之间的第一和第二侧壁。绝缘间隔件形成为沿着第一和第二侧壁延伸并且还沿着导电线和绝缘层之间的底部的至少一部分延伸。通过在导电线的至少一部分之下设置绝缘间隔物，即使间隔物变窄并且/或接触面积可能增大，绝缘可靠性也可以提高。

4. 发明申请

US20080179647A1 SEMICONDUCTOR DEVICE COMPRISING A BARRIER INSULATING LAYER AND RELATED METHOD 审中-公开
标题翻译：包含障壁绝缘层的半导体器件及相关方法
公开(公告)号：US20080179647A1
公开(公告)日：2008-07-31
申请号：US11964146
申请日：2007-12-26
申请人： Hyeoung-won Seo , Dong-hyun Kim , Kang-yoon Lee , Seong-goo Kim
发明人： Hyeoung-won Seo , Dong-hyun Kim , Kang-yoon Lee , Seong-goo Kim
IPC分类号： H01L27/108 , H01L21/8239
CPC分类号： H01L27/10885 , H01L27/10814 , H01L27/10823 , H01L27/10876
摘要： A semiconductor device comprising a barrier insulating layer and a related method of fabrication is disclosed. The semiconductor device semiconductor substrate includes a plurality of active regions, wherein active regions are defined by a device isolation layer and are disposed along a first direction; a plurality of bit line electrodes connected to the active regions, wherein each of the bit line electrodes extends along a second direction; and a plurality of first barrier insulating layers. Each of the first barrier insulating layers extends along a third direction, at least one of the first barrier insulating layers is disposed on a corresponding first portion of the device isolation layer disposed between two of the active regions, the two of the active regions are adjacent along the first direction, and the first direction and the second direction differ from one another.
摘要翻译：公开了一种包括阻挡绝缘层和相关制造方法的半导体器件。半导体器件半导体衬底包括多个有源区，其中有源区由器件隔离层限定，并沿着第一方向设置; 连接到有源区的多个位线电极，其中每个位线电极沿着第二方向延伸; 以及多个第一阻挡绝缘层。每个第一阻挡绝缘层沿着第三方向延伸，至少一个第一阻挡绝缘层设置在设置在两个有源区之间的器件隔离层的对应的第一部分上，两个有源区相邻沿第一方向，第一方向和第二方向彼此不同。

5. 发明授权

US07387931B2 Semiconductor memory device with vertical channel transistor and method of fabricating the same 有权
标题翻译：具有垂直沟道晶体管的半导体存储器件及其制造方法
公开(公告)号：US07387931B2
公开(公告)日：2008-06-17
申请号：US11546581
申请日：2006-10-11
申请人： Hyeoung-won Seo , Jae-man Yoon , Kang-yoon Lee , Dong-gun Park , Bong-soo Kim , Seong-goo Kim
发明人： Hyeoung-won Seo , Jae-man Yoon , Kang-yoon Lee , Dong-gun Park , Bong-soo Kim , Seong-goo Kim
IPC分类号： H01L21/8242 , H01L21/336
CPC分类号： H01L29/66666 , H01L27/0207 , H01L27/10814 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L27/10891 , H01L29/7827
摘要： In a semiconductor memory device having a vertical channel transistor a body of which is connected to a substrate and a method of fabricating the same, the semiconductor memory device includes a semiconductor substrate including a plurality of pillars arranged spaced apart from one another, and each of the pillars includes a body portion and a pair of pillar portions extending from the body portion and spaced apart from each other. A gate electrode is formed to surround each of the pillar portions. A bitline is disposed on the body portion to penetrate a region between a pair of the pillar portions of each of the first pillars arranged to extend in a first direction. A wordline is disposed over the bitline, arranged to extend in a second direction intersecting the first direction, and configured to contact the side surface of the gate electrode. A first doped region is formed in the upper surface of each of the pillar portions of the pillar. A second doped region is formed on the body portion of the pillar and connected electrically to the bitline. Storage node electrodes are connected electrically to the first doped region and disposed on each of the pillar portions.
摘要翻译：在具有其主体连接到基板的垂直沟道晶体管的半导体存储器件及其制造方法中，半导体存储器件包括：半导体衬底，其包括彼此间隔布置的多个柱，并且每个支柱包括主体部分和从主体部分延伸并彼此间隔开的一对柱部分。形成围绕每个支柱部分的栅电极。位于所述主体部分上的位线穿过所述第一支柱中的所述第一支柱的一对支柱之间的区域，所述第一支柱布置成沿第一方向延伸。字线布置在位线之外，布置成沿与第一方向相交的第二方向延伸，并且被配置为接触栅电极的侧表面。第一掺杂区域形成在柱的每个柱部分的上表面中。第二掺杂区形成在柱的主体部分上并与电位线连接。存储节点电极与第一掺杂区域电连接并设置在每个柱部分上。

6. 发明申请

US20080067697A1 INTEGRATED CIRCUIT WIRE PATTERNS INCLUDING INTEGRAL PLUG PORTIONS AND METHODS OF FABRICATING THE SAME 有权
标题翻译：集成电路图案，包括整体插拔方式及其制作方法
公开(公告)号：US20080067697A1
公开(公告)日：2008-03-20
申请号：US11675829
申请日：2007-02-16
申请人： Seong-Goo Kim , Yung-Gi Kim , Jae-Man Yoon , Hyeoung-Won Seo
发明人： Seong-Goo Kim , Yung-Gi Kim , Jae-Man Yoon , Hyeoung-Won Seo
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L29/4236 , H01L21/28123 , H01L21/76834 , H01L21/76883 , H01L21/76897 , H01L23/52 , H01L29/66621 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit device includes a substrate including a trench therein and a conductive plug wire pattern in the trench. The conductive plug wire pattern includes a recessed portion that exposes portions of opposing sidewalls of the trench, and an integral plug portion that protrudes from a surface of the recessed portion to provide an electrical connection to at least one other conductive wire pattern on a different level of metallization. A surface of the plug portion may protrude to a substantially same level as a surface of the substrate adjacent to and outside the trench, and the surface of the recessed portion may be below the surface of the substrate outside the trench. Related fabrication methods are also discussed.
摘要翻译：集成电路器件包括其中包括沟槽的衬底和沟槽中的导电插头线图案。导电插头线图案包括露出沟槽的相对侧壁的部分的凹陷部分和从凹陷部分的表面突出的整体插塞部分，以提供与不同层级上的至少一个其它导电线图案的电连接的金属化。插塞部分的表面可以突出到与沟槽相邻并且在沟槽外部的衬底的表面基本相同的水平面，并且凹部的表面可以在沟槽外部的衬底的表面下方。还讨论了相关的制造方法。

7. 发明授权

US07297998B2 Semiconductor devices having a buried and enlarged contact hole and methods of fabricating the same 有权
标题翻译：具有埋入和扩大的接触孔的半导体器件及其制造方法
公开(公告)号：US07297998B2
公开(公告)日：2007-11-20
申请号：US11419719
申请日：2006-05-22
申请人： Seong-Goo Kim , Sang-Moo Jeong
发明人： Seong-Goo Kim , Sang-Moo Jeong
IPC分类号： H01L27/108 , H01L29/76
CPC分类号： H01L21/76895 , H01L21/76804 , H01L21/76831 , H01L21/76897 , H01L23/485 , H01L27/10814 , H01L27/10855 , H01L2924/0002 , H01L2924/00
摘要： According to embodiments of the invention, a bit line interlayer insulating layer is placed over a semiconductor substrate. Two adjacent bit line patterns are placed in parallel on the bit line interlayer insulating layer and each of the two adjacent bit line patterns includes a bit line and a bit line capping layer pattern stacked thereon. A buried contact interlayer insulating layer covers a surface of the semiconductor substrate having the two adjacent bit line patterns. A contact hole is placed in a portion between the bit line patterns to penetrate the buried contact interlayer insulating layer and the bit line interlayer insulating layer and to expose at least one side wall of the bit line patterns. A contact hole spacer covers side wall of the contact hole. A contact hole plug is placed on the contact hole spacer to fill the contact hole.
摘要翻译：根据本发明的实施例，将位线层间绝缘层放置在半导体衬底上。两个相邻位线图案并联放置在位线层间绝缘层上，并且两个相邻位线图案中的每一个都包括位线和位线叠层层图案。掩埋接触层间绝缘层覆盖具有两个相邻位线图案的半导体衬底的表面。接触孔放置在位线图案之间的部分中，以穿透埋入层间绝缘层和位线层间绝缘层，并露出位线图案的至少一个侧壁。接触孔间隔件覆盖接触孔的侧壁。接触孔插头放置在接触孔间隔件上以填充接触孔。

8. 发明申请

US20050239279A1 Integrated circuits including spacers that extend beneath a conductive line and methods of fabricating the same 有权
标题翻译：包括在导电线下方延伸的间隔物的集成电路及其制造方法
公开(公告)号：US20050239279A1
公开(公告)日：2005-10-27
申请号：US11170820
申请日：2005-06-30
申请人： Sung-Joon Park , Seong-Goo Kim
发明人： Sung-Joon Park , Seong-Goo Kim
IPC分类号： H01L21/3205 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L23/532 , H01L27/108 , H01L21/4763
CPC分类号： H01L27/10855 , H01L21/76885 , H01L21/76897 , H01L23/53295 , H01L27/10814 , H01L27/10885 , H01L27/10888 , H01L2924/0002 , Y10S257/906 , H01L2924/00
摘要： Integrated circuit devices are fabricated by fabricating a conductive line on an insulating layer on an integrated circuit substrate. The conductive line includes a bottom adjacent the insulating layer, a top remote from the insulating layer and first and second sidewalls therebetween. An insulating spacer is formed to extend along the first and second sidewalls and to also extend along at least a portion of the bottom between the conductive line and the insulating layer. By providing an insulating spacer beneath at least a portion of the conductive line, insulation reliability may be improved even as the spacer may become narrower and/or the contact area may be enlarged.
摘要翻译：通过在集成电路基板上的绝缘层上制造导电线来制造集成电路器件。导线包括邻近绝缘层的底部，远离绝缘层的顶部以及它们之间的第一和第二侧壁。绝缘间隔件形成为沿着第一和第二侧壁延伸并且还沿着导电线和绝缘层之间的底部的至少一部分延伸。通过在导电线的至少一部分之下设置绝缘间隔物，即使间隔物变窄并且/或接触面积可能增大，绝缘可靠性也可以提高。

9. 发明授权

US08378497B2 Contact structures and semiconductor devices including the same 有权
标题翻译：接触结构和包括其的半导体器件
公开(公告)号：US08378497B2
公开(公告)日：2013-02-19
申请号：US12758946
申请日：2010-04-13
申请人： Seong-Goo Kim , Hyeong-Sun Hong , Dong-Hyun Kim , Nam-Jung Kang
发明人： Seong-Goo Kim , Hyeong-Sun Hong , Dong-Hyun Kim , Nam-Jung Kang
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L29/4236 , H01L21/76829 , H01L21/76897 , H01L27/0207 , H01L27/10855 , H01L27/10876
摘要： Methods of forming a contact structure in a semiconductor device include providing a semiconductor substrate including active regions and word lines crossing the active regions. A first interlayer dielectric layer is formed on the semiconductor substrate. Direct contact plugs are formed extending through the first interlayer dielectric layer to contact selected ones of the active regions. Bit line structures are formed on the first interlayer dielectric layer and crossing the word lines that are coupled to the selected ones of the active regions by the direct contact plugs. A second interlayer dielectric layer is formed on the semiconductor substrate including the bit line structures. Barrier patterns are formed extending in parallel with bit line structures and into the second interlayer dielectric layer. Mask patterns are formed overlying an entirety of top surfaces of the direct contact plugs on the second interlayer dielectric layer and the bit line structures. The second and first interlayer dielectric layers are etched using the mask patterns, the barrier patterns and the bit line structures as an etching mask to form buried contact holes and buried contact plugs are formed in the buried contact holes.
摘要翻译：在半导体器件中形成接触结构的方法包括提供包括有源区和跨越有源区的字线的半导体衬底。在半导体衬底上形成第一层间电介质层。形成延伸穿过第一层间电介质层的直接接触插塞以接触所选择的有源区域。位线结构形成在第一层间电介质层上并且通过直接接触插塞与被选择的有源区域耦合的字线交叉。在包括位线结构的半导体衬底上形成第二层间电介质层。阻挡层图案形成为与位线结构平行延伸并进入第二层间电介质层。掩模图形形成在第二层间介质层上的直接接触插塞的整个顶表面和位线结构上。使用掩模图案蚀刻第二和第一层间电介质层，将掩模图案和位线结构作为蚀刻掩模形成埋入的接触孔，并且在埋入的接触孔中形成掩埋的接触插塞。

10. 发明申请

US20120273898A1 SEMICONDUCTOR MEMORY DEVICE HAVING VERTICAL CHANNEL TRANSISTOR AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：具有垂直通道晶体管的半导体存储器件及其制造方法
公开(公告)号：US20120273898A1
公开(公告)日：2012-11-01
申请号：US13549648
申请日：2012-07-16
申请人： Hyeoung-won Seo , Bong-soo Kim , Dong-gun Park , Kang-yoon Lee , Jae-man Yoon , Seong-goo Kim , Seung-bae Park
发明人： Hyeoung-won Seo , Bong-soo Kim , Dong-gun Park , Kang-yoon Lee , Jae-man Yoon , Seong-goo Kim , Seung-bae Park
IPC分类号： H01L27/088
CPC分类号： H01L27/0207 , H01L27/10814 , H01L27/10823 , H01L27/10876 , H01L27/10888 , H01L27/10891
摘要： Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated
摘要翻译：两个晶体管的沟道垂直地形成在一个有源区的两个相对的侧表面的部分上，并且栅极垂直地形成在与有源区的沟道接触的器件隔离层上。在有源区域的中心部分形成共同的位线接触插塞，在位线接触插塞的两侧形成两个存储节点接触插塞，并且在位线接触插头的侧面上形成绝缘间隔件。像现有的半导体存储器件一样，在半导体衬底上顺序层叠字线，位线和电容器。因此，存储单元的有效空间布置是可能的，使得构成4F2结构，并且可以应用常规的线和接触形成工艺，使得容易制造高度集成的半导体存储器件

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