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1. 发明授权

US06500766B2 Post-cleaning method of a via etching process 有权
公开(公告)号：US06500766B2
公开(公告)日：2002-12-31
申请号：US09832267
申请日：2001-04-11
申请人： Hungyueh Lu , Hong-Long Chang , Fang-Fei Liu
发明人： Hungyueh Lu , Hong-Long Chang , Fang-Fei Liu
IPC分类号： H01L21302
CPC分类号： H01L21/02054 , H01L21/02046 , Y10S438/906
摘要： A post-cleaning method of a via etching process for cleaning a wafer, the wafer having a tungsten (W) layer, an oxide layer covered on the tungsten layer, a photoresist layer patterned on the oxide layer, and a via passing through the photoresist layer and the oxide layer until a predetermined area of the tungsten layer is exposed, the cleaning method has the steps of: (a) performing a photoresist strip process to remove the photoresist layer; (b) performing a dry cleaning process which uses CF4 and N2H2 as the main reactive gas; and (c) performing a water-rinsing process.

2. 发明授权

US06526996B1 Dry clean method instead of traditional wet clean after metal etch 有权
公开(公告)号：US06526996B1
公开(公告)日：2003-03-04
申请号：US09591848
申请日：2000-06-12
申请人： Hong-Long Chang , Ming-Li Kung , Hungyueh Lu , Fang-Fei Liu
发明人： Hong-Long Chang , Ming-Li Kung , Hungyueh Lu , Fang-Fei Liu
IPC分类号： C25F500
CPC分类号： H01L21/02071 , H01L21/32136 , Y10S134/902 , Y10S438/906
摘要： A dry cleaning method for use in semiconductor fabrication, including the following steps. An etched metallization structure is provided and placed in a processing chamber. The etched metallization structure is cleaned by introducing a fluorine containing gas/oxygen containing gas mixture into the processing chamber proximate the etched metallization structure without the use of a downstream microwave while applying a magnetic field proximate the etched metallization structure and maintaining a pressure of less than about 50 millitorr within the processing chamber for a predetermined time.

3. 发明申请

US20070131649A1 ETCHING METHOD 审中-公开
标题翻译：蚀刻方法
公开(公告)号：US20070131649A1
公开(公告)日：2007-06-14
申请号：US11308656
申请日：2006-04-19
申请人： Hong-Long Chang , Kai-Mu Hsiao
发明人： Hong-Long Chang , Kai-Mu Hsiao
IPC分类号： H01B13/00 , H01L21/461 , C03C25/68 , B44C1/22 , H01L21/302
CPC分类号： H01L21/3065 , H01L21/76802
摘要： The invention is directed to an etching method. The etching method comprises steps of providing a material layer having a patterned hard mask layer formed thereon and then performing a first dry etching process by using the patterned hard mask layer as a mask, wherein a first power mode of the first dry etching process is a pulse mode and the first dry etching process is performed for a first process time. A second dry etching process is performed by using the patterned hard mask layer as a mask, wherein a second power mode of the second dry etching process is a continued wave mode and the second dry etching process is performed for a second process time, and the ratio of the first process time to the second process time is about 0.1˜2.0.
摘要翻译：本发明涉及一种蚀刻方法。蚀刻方法包括以下步骤：提供具有形成在其上的图案化硬掩模层的材料层，然后通过使用图案化硬掩模层作为掩模进行第一干蚀刻工艺，其中第一干蚀刻工艺的第一功率模式为并且在第一处理时间执行第一干蚀刻处理。通过使用图案化的硬掩模层作为掩模来执行第二干蚀刻工艺，其中第二干蚀刻工艺的第二电源模式是连续波模式，并且在第二处理时间执行第二干蚀刻工艺，第一处理时间与第二处理时间的比率为约0.1〜2.0。

4. 发明授权

US06410417B1 Method of forming tungsten interconnect and vias without tungsten loss during wet stripping of photoresist polymer 有权
标题翻译：在光致抗蚀剂聚合物的湿剥离过程中形成钨互连和通孔而不发生钨损的方法
公开(公告)号：US06410417B1
公开(公告)日：2002-06-25
申请号：US09186757
申请日：1998-11-05
申请人： Nien-Yu Tsai , Hong-Long Chang , Chun-Wei Chen , Ming-Li Kung
发明人： Nien-Yu Tsai , Hong-Long Chang , Chun-Wei Chen , Ming-Li Kung
IPC分类号： H01L214763
CPC分类号： H01L21/31138
摘要： A method of forming a metal interconnect structure and via plugs over a dielectric layer having a plurality of vias formed therein is disclosed. The method comprises the steps of: forming tungsten via plugs in the plurality of vias; depositing a metal layer over the dielectric layer and the plurality of tungsten via plugs; patterning and etching the metal layer using a photoresist layer to form the metal interconnect structure; removing the photoresist layer in an asher using a combination of oxygen plasma and water vapor, the ratio of oxygen plasma and water vapor being less than one; and performing a wet strip on the metal interconnect structure.
摘要翻译：公开了一种在其上形成有多个通孔的电介质层上形成金属互连结构和通孔塞的方法。该方法包括以下步骤：通过多个通孔中的插塞形成钨; 在所述电介质层和所述多个钨通过插塞上沉积金属层; 使用光致抗蚀剂层图案化和蚀刻金属层以形成金属互连结构; 使用氧等离子体和水蒸气的组合去除灰浆中的光致抗蚀剂层，氧等离子体和水蒸汽的比例小于1; 并在金属互连结构上执行湿条。

5. 发明申请

US20080124935A1 Two-step process for manufacturing deep trench 审中-公开
标题翻译：制造深沟的两步法
公开(公告)号：US20080124935A1
公开(公告)日：2008-05-29
申请号：US11641573
申请日：2006-12-19
申请人： Hong-Long Chang , Yi-Hsiung Lin , Chris Shyu
发明人： Hong-Long Chang , Yi-Hsiung Lin , Chris Shyu
IPC分类号： H01L21/71
CPC分类号： H01L29/66181 , H01L21/3065 , H01L21/3081 , H01L27/1087
摘要： A two-step process for manufacturing a deep trench in a semiconductor device that prevents shorts and leakages between neighboring capacitors due to over etching is disclosed. The process comprises conducting a first etching step to remove a portion of a substrate to form a trench with a first determined depth therein; conducting a thermal oxidation to form an oxide film on the sidewall of the trench; and conducting a second etching step to remove a portion of the substrate under the trench to form a deep trench with a second determined depth.
摘要翻译：公开了用于制造半导体器件中的深沟槽的两步法，其防止由于过蚀刻引起的相邻电容器之间的短路和泄漏。该方法包括进行第一蚀刻步骤以去除衬底的一部分以形成其中具有第一确定深度的沟槽; 进行热氧化以在沟槽的侧壁上形成氧化膜; 以及进行第二蚀刻步骤以去除所述沟槽下方的所述衬底的一部分以形成具有第二确定深度的深沟槽。

6. 发明授权

US07241659B2 Volatile memory devices and methods for forming same 失效
标题翻译：易失性存储器件及其形成方法
公开(公告)号：US07241659B2
公开(公告)日：2007-07-10
申请号：US10983664
申请日：2004-11-09
申请人： Chin-Long Hung , Hong-Long Chang , Yueh-Chuan Lee
发明人： Chin-Long Hung , Hong-Long Chang , Yueh-Chuan Lee
IPC分类号： H01L21/8242
CPC分类号： H01L27/10867
摘要： A method for forming a volatile memory device. A substrate comprising a pair of neighboring trenches is provided, each trench comprising a capacitor. A collar insulating layer is formed on an upper sidewall of each trench. The collar insulating layer comprises a low level portion and a high level portion adjacent to a predetermined active area of the volatile memory device.
摘要翻译：一种用于形成易失性存储器件的方法。提供了包括一对相邻沟槽的衬底，每个沟槽包括电容器。在每个沟槽的上侧壁上形成轴环绝缘层。轴环绝缘层包括与易失性存储装置的预定有效区域相邻的低电平部分和高电平部分。

7. 发明申请

US20050067648A1 Volatile memory devices and methods for forming same 失效
标题翻译：易失性存储器件及其形成方法
公开(公告)号：US20050067648A1
公开(公告)日：2005-03-31
申请号：US10983664
申请日：2004-11-09
申请人： Chin-Long Hung , Hong-Long Chang , Yueh-Chuan Lee
发明人： Chin-Long Hung , Hong-Long Chang , Yueh-Chuan Lee
IPC分类号： H01L21/8242 , H01L21/8244 , H01L29/76
CPC分类号： H01L27/10867
摘要： A method for forming a volatile memory device. A substrate comprising a pair of neighboring trenches is provided, each trench comprising a capacitor. A collar insulating layer is formed on an upper sidewall of each trench. The collar insulating layer comprises a low level portion and a high level portion adjacent to a predetermined active area of the volatile memory device.
摘要翻译：一种用于形成易失性存储器件的方法。提供了包括一对相邻沟槽的衬底，每个沟槽包括电容器。在每个沟槽的上侧壁上形成轴环绝缘层。轴环绝缘层包括与易失性存储装置的预定有效区域相邻的低电平部分和高电平部分。

8. 发明授权

US06399509B1 Defects reduction for a metal etcher 有权
标题翻译：金属蚀刻机的缺陷减少
公开(公告)号：US06399509B1
公开(公告)日：2002-06-04
申请号：US09664426
申请日：2000-09-18
申请人： Hung-Yueh Lu , Ray C. Lee , Hong-Long Chang
发明人： Hung-Yueh Lu , Ray C. Lee , Hong-Long Chang
IPC分类号： H01L21302
CPC分类号： H01L21/02071 , H01L21/32136
摘要： A method of patterning a metal line and removing the polymer layer that forms on the metal lines sidewalls in an important post etch-polymer removal step (e.g., step 4). A semiconductor structure and an overlying dielectric layer, a first barrier layer, a metal layer; a second barrier layer and resist pattern are provided. A four step etch process is performed in sequence in the same etch chamber. In a first etch step (A), we etch through the second barrier layer using a B and Cl containing gas and a Cl containing gas in a reactive ion etch to form a first polymer layer over the sidewall of the second barrier layer. In a second etch step (B), the metal layer is etched exposing the first barrier layer to form a second polymer over the first polymer and the sidewall of the metal layer; the second etch step performed using a B and Cl containing gas and a Cl containing gas. In a third etch step (C), the first barrier layer is etched to form a third polymer layer over the first and second polymer layers. The third etch step is performed using a B and Cl containing gas and a Cl containing gas. In an important fourth etch step (D), we remove the first, second and third polymers; the fourth etch step performed using only chlorine containing gas (Cl2) gas and a fluorocarbon containing gas.
摘要翻译：图案化金属线并去除在重要的后蚀刻 - 聚合物去除步骤（例如，步骤4）中在金属线侧壁上形成的聚合物层的方法。半导体结构和上覆电介质层，第一阻挡层，金属层; 提供第二阻挡层和抗蚀剂图案。在相同的蚀刻室中依次执行四步蚀刻工艺。在第一蚀刻步骤（A）中，我们在反应离子蚀刻中使用含有B和Cl的气体和含Cl的气体蚀刻穿过第二阻挡层，以在第二阻挡层的侧壁上形成第一聚合物层。在第二蚀刻步骤（B）中，金属层被蚀刻，暴露第一阻挡层以在第一聚合物和金属层的侧壁上形成第二聚合物; 使用含有B和Cl的气体和含Cl的气体进行第二蚀刻步骤。在第三蚀刻步骤（C）中，蚀刻第一阻挡层以在第一和第二聚合物层上形成第三聚合物层。使用含有B和Cl的气体和含Cl的气体进行第三蚀刻步骤。在重要的第四蚀刻步骤（D）中，我们除去第一，第二和第三聚合物; 仅使用含氯气体（Cl2）气体和含碳氟化合物的气体进行第四蚀刻步骤。

9. 发明授权

US6143653A Method of forming tungsten interconnect with tungsten oxidation to prevent tungsten loss 有权
标题翻译：用钨氧化形成钨互连以防止钨损失的方法
公开(公告)号：US6143653A
公开(公告)日：2000-11-07
申请号：US186303
申请日：1998-10-04
申请人： Nien-Yu Tsai , Hong-Long Chang , Chun-Wei Chen , Ming-Li Kung
发明人： Nien-Yu Tsai , Hong-Long Chang , Chun-Wei Chen , Ming-Li Kung
IPC分类号： H01L21/311 , H01L21/768 , H01L21/44
CPC分类号： H01L21/31133 , H01L21/76888
摘要： A method of forming a metal interconnect structure and via plugs over a dielectric layer having a plurality of vias formed therein is disclosed. The method comprises the steps of: forming tungsten via plugs in the plurality of vias; depositing a metal layer over the dielectric layer and the plurality of tungsten via plugs; patterning and etching the metal layer using a photoresist layer to form the metal interconnect structure; oxidizing the metal interconnect structure and the tungsten via plugs to form a metal oxide layer over the metal interconnect structure and tungsten via plugs; and performing a wet strip on the metal interconnect structure.
摘要翻译：公开了一种在其上形成有多个通孔的电介质层上形成金属互连结构和通孔塞的方法。该方法包括以下步骤：通过多个通孔中的插塞形成钨; 在所述电介质层和所述多个钨通过插塞上沉积金属层; 使用光致抗蚀剂层图案化和蚀刻金属层以形成金属互连结构; 通过插塞氧化金属互连结构和钨，以在金属互连结构和钨通孔上形成金属氧化物层; 并在金属互连结构上执行湿条。

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