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1. 发明授权

US07678586B2 Structure and method to prevent charge damage from e-beam curing process 有权
标题翻译：防止电子束固化过程中电荷损伤的结构和方法
公开(公告)号：US07678586B2
公开(公告)日：2010-03-16
申请号：US11297485
申请日：2005-12-08
申请人： Huang Liu , Bei Chao Zhang , Wuping Liu , John Leonard Sudijono , Liang Choo Hsia
发明人： Huang Liu , Bei Chao Zhang , Wuping Liu , John Leonard Sudijono , Liang Choo Hsia
IPC分类号： H01L21/00
CPC分类号： H01L21/31058 , B05D3/068 , H01J2237/04735 , H01J2237/3156 , H01L21/02112 , H01L21/02274 , H01L21/02351 , H01L21/3105 , H01L21/312 , H01L21/31633 , H01L21/76825 , H01L21/76834
摘要： An example embodiment is a method of curing a film over a semiconductor structure. We provide a semiconductor structure comprised of a substrate and an interconnect structure. We provide a film over the semiconductor structure. We provide an electron source, an anode grid between the electron source and the semiconductor structure. We cure the film by exposing the film to an electron beam from the electron source that passes through the anode grid. We control the electron beam by controlling the bias voltage between the anode grid and the semiconductor structure. Another embodiment is a tool for curing a film.
摘要翻译：示例性实施例是在半导体结构上固化膜的方法。我们提供由衬底和互连结构组成的半导体结构。我们提供半导体结构的电影。我们提供电子源，电子源和半导体结构之间的阳极栅极。我们通过将膜暴露于电子源通过阳极栅格的电子束来固化膜。我们通过控制阳极栅极和半导体结构之间的偏置电压来控制电子束。另一个实施例是用于固化膜的工具。

2. 发明授权

US07276440B2 Method of fabrication of a die oxide ring 有权
标题翻译：芯片氧化物环的制造方法
公开(公告)号：US07276440B2
公开(公告)日：2007-10-02
申请号：US10734423
申请日：2003-12-12
申请人： Fan Zhang , Bei Chao Zhang , Wuping Liu , Kho Liep Chok , Liang Choo Hsia , Tae Jong Lee , Juan Boon Tan , Xian Bin Wang
发明人： Fan Zhang , Bei Chao Zhang , Wuping Liu , Kho Liep Chok , Liang Choo Hsia , Tae Jong Lee , Juan Boon Tan , Xian Bin Wang
IPC分类号： H01L23/04
CPC分类号： H01L23/562 , H01L23/3178 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： In accordance with the objectives of the invention a new design and method for the implementation thereof is provided in the form of an “oxide ring”. A conventional die is provided with a guard ring or sealing ring, which surrounds and isolates the active surface area of an individual semiconductor die. The “oxide ring” of the invention surrounds the guard ring or sealing ring and forms in this manner a mechanical stress release buffer between the sawing paths of the die and the active surface area of the singulated individual semiconductor die.
摘要翻译：根据本发明的目的，以“氧化物环”的形式提供了一种用于实施本发明的新设计和方法。传统的模具设置有保护环或密封环，其围绕并隔离单个半导体管芯的有源表面积。本发明的“氧化物环”围绕保护环或密封环，并以这种方式形成在管芯的锯切路径和单个化的半导体管芯的有源表面区域之间的机械应力释放缓冲器。

3. 发明授权

US07012022B2 Self-patterning of photo-active dielectric materials for interconnect isolation 失效
公开(公告)号：US07012022B2
公开(公告)日：2006-03-14
申请号：US10697745
申请日：2003-10-30
申请人： Wuping Liu , Bei Chao Zhang , Liang Choo Hsia
发明人： Wuping Liu , Bei Chao Zhang , Liang Choo Hsia
IPC分类号： H01L21/4763
CPC分类号： H01L21/76814 , H01L21/4846 , H01L21/76802 , H01L21/76807 , H01L21/76828 , H01L23/5329 , H01L2221/1026 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： In accordance with the objectives of the invention a new method is provided for the creation of an interconnect pattern. The invention provides for a layer of Photo-Active Dielectric (PAD) to be used for the insulation material in which the interconnect pattern is created, this without the use of an overlying exposure mask of photoresist.

4. 发明授权

US07256136B2 Self-patterning of photo-active dielectric materials for interconnect isolation 有权
标题翻译：用于互连隔离的光电介质材料的自构图
公开(公告)号：US07256136B2
公开(公告)日：2007-08-14
申请号：US11345890
申请日：2006-02-02
申请人： Wuping Liu , Bei Chao Zhang , Liang Choo Hsia
发明人： Wuping Liu , Bei Chao Zhang , Liang Choo Hsia
IPC分类号： H01L21/64
CPC分类号： H01L21/76814 , H01L21/4846 , H01L21/76802 , H01L21/76807 , H01L21/76828 , H01L23/5329 , H01L2221/1026 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： In accordance with the objectives of the invention a new method is provided for the creation of an interconnect pattern. The invention provides for a layer of Photo-Active Dielectric (PAD) to be used for the insulation material in which the interconnect pattern is created, this without the use of an overlying exposure mask of photoresist.
摘要翻译：根据本发明的目的，提供了一种用于创建互连图案的新方法。本发明提供了一种用于产生互连图案的绝缘材料的光电介质（PAD）层，不需要使用光致抗蚀剂的上覆曝光掩模。

5. 发明授权

US07601607B2 Protruded contact and insertion of inter-layer-dielectric material to match damascene hardmask to improve undercut for low-k interconnects 有权
标题翻译：突出接触和插入层间介电材料以匹配镶嵌硬掩模，以改善低k互连的底切
公开(公告)号：US07601607B2
公开(公告)日：2009-10-13
申请号：US11434318
申请日：2006-05-15
申请人： Wuping Liu , Raymond Joy , Beichao Zhang , Liang Choo Hsia , Boon Meng Seah , Shyam Pal
发明人： Wuping Liu , Raymond Joy , Beichao Zhang , Liang Choo Hsia , Boon Meng Seah , Shyam Pal
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/02063 , H01L21/31111 , H01L21/31116 , H01L21/31133 , H01L21/31138 , H01L21/31144 , H01L21/76814
摘要： An embodiment of the invention shows a process to form a damascene opening preferably without hardmask overhang or dielectric layer undercut/void. The low-k dielectric material can be sandwiched in two hardmask films to form the dielectric film through which an interconnect opening is etched. A first example embodiment comprises the following. We form a lower interconnect and an insulating layer over a semiconductor structure. We form a first hardmask a dielectric layer, and a second hardmask layer, over the lower interconnect and insulating layer. We etch a first interconnect opening in the first hardmask, the dielectric layer and the second hardmask layer. Lastly, we form an interconnect in the first interconnect opening.
摘要翻译：本发明的一个实施例示出了一种形成镶嵌开口的方法，优选地不具有硬掩模悬垂或电介质层底切/空隙。低k电介质材料可以被夹在两个硬掩模膜中以形成蚀刻互连开口的电介质膜。第一示例性实施例包括以下。我们在半导体结构上形成下互连和绝缘层。我们在下互连和绝缘层上形成第一硬掩模介电层和第二硬掩模层。我们蚀刻第一硬掩模，电介质层和第二硬掩模层中的第一互连开口。最后，我们在第一个互连开口中形成互连。

6. 发明授权

US07323408B2 Metal barrier cap fabrication by polymer lift-off 有权
标题翻译：通过聚合物剥离制造金属阻挡帽
公开(公告)号：US07323408B2
公开(公告)日：2008-01-29
申请号：US11299457
申请日：2005-12-12
申请人： Beichao Zhang , Wuping Liu , Liang-Choo Hsia
发明人： Beichao Zhang , Wuping Liu , Liang-Choo Hsia
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76834 , H01L21/76849 , H01L21/76865 , H01L21/76883 , H01L23/53295 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A new method is provided for the creation of copper interconnects. A pattern of copper interconnects is created, a protective layer of semiconductor material is deposited over the surface of the created copper interconnects. The protective layer is patterned and etched, exposing the surface of the pattern of copper interconnects. The exposed copper surface is Ar sputtered after which a first barrier layer is deposited. The patterned and etched layer of protective material is removed, leaving in place overlying the pattern of copper interconnects a protective layer of first barrier material. A dielectric barrier layer, in the form of a layer of etch stop material, is deposited after which additional layers of dielectric interspersed with layers of etch stop material are deposited. Via and trench patterns are etched aligned with a copper pattern to which an electrical contact is to be established, the copper pattern being protected by the first layer of barrier material. A second barrier layer is deposited, the via and trench pattern is filled with copper after which excess copper is removed by polishing the surface of the deposited layer of copper.
摘要翻译：提供了一种用于创建铜互连的新方法。产生铜互连的图案，半导体材料的保护层沉积在所产生的铜互连的表面上。保护层被图案化和蚀刻，暴露铜互连图案的表面。暴露的铜表面是Ar溅射，之后沉积第一势垒层。去除保护材料的图案化和蚀刻层，留在覆盖铜图案的位置使第一阻挡材料的保护层互连。沉积了一层蚀刻停止材料形式的电介质阻挡层，之后沉积了分层的蚀刻停止材料层。通孔和沟槽图案被蚀刻成与将要建立电接触的铜图案对齐，铜图案被第一层屏障材料保护。沉积第二阻挡层，通孔和沟槽图案填充有铜，之后通过抛光沉积的铜层的表面去除多余的铜。

7. 发明授权

US07153766B2 Metal barrier cap fabrication by polymer lift-off 有权
公开(公告)号：US07153766B2
公开(公告)日：2006-12-26
申请号：US10339188
申请日：2003-01-09
申请人： Beichao Zhang , Wuping Liu , Liang-Choo Hsia
发明人： Beichao Zhang , Wuping Liu , Liang-Choo Hsia
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76834 , H01L21/76849 , H01L21/76865 , H01L21/76883 , H01L23/53295 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A new method is provided for the creation of copper interconnects. A pattern of copper interconnects is created, a protective layer of semiconductor material is deposited over the surface of the created copper interconnects. The protective layer is patterned and etched, exposing the surface of the pattern of copper interconnects. The exposed copper surface is Ar sputtered after which a first barrier layer is deposited. The patterned and etched layer of protective material is removed, leaving in place overlying the pattern of copper interconnects a protective layer of first barrier material. A dielectric barrier layer, in the form of a layer of etch stop material, is deposited after which additional layers of dielectric interspersed with layers of etch stop material are deposited. Via and trench patterns are etched aligned with a copper pattern to which an electrical contact is to be established, the copper pattern being protected by the first layer of barrier material. A second barrier layer is deposited, the via and trench pattern is filled with copper after which excess copper is removed by polishing the surface of the deposited layer of copper.

8. 发明申请

US20060088995A1 Metal barrier cap fabrication by polymer lift-off 有权
标题翻译：通过聚合物剥离制造金属阻挡帽
公开(公告)号：US20060088995A1
公开(公告)日：2006-04-27
申请号：US11299457
申请日：2005-12-12
申请人： Beichao Zhang , Wuping Liu , Liang-Choo Hsia
发明人： Beichao Zhang , Wuping Liu , Liang-Choo Hsia
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76834 , H01L21/76849 , H01L21/76865 , H01L21/76883 , H01L23/53295 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A new method is provided for the creation of copper interconnects. A pattern of copper interconnects is created, a protective layer of semiconductor material is deposited over the surface of the created copper interconnects. The protective layer is patterned and etched, exposing the surface of the pattern of copper interconnects. The exposed copper surface is Ar sputtered after which a first barrier layer is deposited. The patterned and etched layer of protective material is removed, leaving in place overlying the pattern of copper interconnects a protective layer of first barrier material. A dielectric barrier layer, in the form of a layer of etch stop material, is deposited after which additional layers of dielectric interspersed with layers of etch stop material are deposited. Via and trench patterns are etched aligned with a copper pattern to which an electrical contact is to be established, the copper pattern being protected by the first layer of barrier material. A second barrier layer is deposited, the via and trench pattern is filled with copper after which excess copper is removed by polishing the surface of the deposited layer of copper.
摘要翻译：提供了一种用于创建铜互连的新方法。产生铜互连的图案，半导体材料的保护层沉积在所产生的铜互连的表面上。保护层被图案化和蚀刻，暴露铜互连图案的表面。暴露的铜表面是Ar溅射，之后沉积第一势垒层。去除保护材料的图案化和蚀刻层，留在覆盖铜图案的位置使第一阻挡材料的保护层互连。沉积了一层蚀刻停止材料形式的电介质阻挡层，之后沉积了分层的蚀刻停止材料层。通孔和沟槽图案被蚀刻成与将要建立电接触的铜图案对齐，铜图案被第一层屏障材料保护。沉积第二阻挡层，通孔和沟槽图案填充有铜，之后通过抛光沉积的铜层的表面去除多余的铜。

9. 发明授权

US08358007B2 Integrated circuit system employing low-k dielectrics and method of manufacture thereof 有权
标题翻译：采用低k电介质的集成电路系统及其制造方法
公开(公告)号：US08358007B2
公开(公告)日：2013-01-22
申请号：US12796610
申请日：2010-06-08
申请人： Dong Kyun Sohn , Wuping Liu , Fan Zhang , Juan Boon Tan , Jing Hui Li , Bei Chao Zhang , Luying Du , Wei Liu , Yeow Kheng Lim
发明人： Dong Kyun Sohn , Wuping Liu , Fan Zhang , Juan Boon Tan , Jing Hui Li , Bei Chao Zhang , Luying Du , Wei Liu , Yeow Kheng Lim
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/5329 , H01L21/3105 , H01L21/31155 , H01L21/76825 , H01L21/76828 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L21/76859 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A method of manufacture of an integrated circuit system includes: fabricating a substrate having an integrated circuit; applying a low-K dielectric layer over the integrated circuit; forming a via and a trench, in the low-K dielectric layer, over the integrated circuit; forming a structure surface by a chemical-mechanical planarization (CMP) process; and applying a direct implant to the structure surface for forming an implant layer and a metal passivation layer including repairing damage, to the low-K dielectric layer, caused by the CMP process.
摘要翻译：集成电路系统的制造方法包括：制造具有集成电路的基板; 在集成电路上施加低K电介质层; 在低K电介质层中形成通孔和沟槽，在集成电路上; 通过化学机械平面化（CMP）工艺形成结构表面; 以及对由CMP工艺引起的用于形成植入层和金属钝化层的直接植入物施加到包括修复损伤的低K电介质层。

10. 发明授权

US06995087B2 Integrated circuit with simultaneous fabrication of dual damascene via and trench 有权
标题翻译：集成电路，同时制造双镶嵌通孔和沟槽
公开(公告)号：US06995087B2
公开(公告)日：2006-02-07
申请号：US10328512
申请日：2002-12-23
申请人： Wuping Liu , Juan Boon Tan , Bei Chao Zhang , Alan Cuthbertson
发明人： Wuping Liu , Juan Boon Tan , Bei Chao Zhang , Alan Cuthbertson
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/76811 , H01L21/76813
摘要： An integrated circuit manufacturing method includes providing a base, forming a first conductor, forming a first barrier layer, forming a first dielectric layer, and forming a masking layer. The method further including forming a first via opening in the masking layer, forming a first trench opening in the masking layer, and simultaneously forming a second via opening in a layer under the masking layer, and forming a second trench opening through the masking layer and in the layer under the masking layer and simultaneously forming a third via opening in another layer under the masking layer. The method further including removing the first barrier layer using the third via opening and the masking layer to form a trench and a via, and filling the trench and the via with a conductor to form a trench and via conductor in contact with the first conductor.
摘要翻译：集成电路制造方法包括提供基底，形成第一导体，形成第一阻挡层，形成第一介电层，形成掩模层。该方法还包括在掩模层中形成第一通孔，在掩模层中形成第一沟槽开口，同时在掩模层下方的层中形成第二通孔，并形成穿过掩模层的第二沟槽开口，在掩模层下面的层中并且同时在掩模层下方的另一层中形成第三通孔。该方法还包括使用第三通孔开口和掩模层去除第一阻挡层以形成沟槽和通孔，以及用导体填充沟槽和通孔以形成与第一导体接触的沟槽和通孔导体。

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