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1. 发明授权

US6001694A Manufacturing method for integrated circuit dielectric layer 失效
标题翻译：集成电路介质层的制造方法
公开(公告)号：US6001694A
公开(公告)日：1999-12-14
申请号：US059752
申请日：1998-04-14
申请人： Hsueh-Hao Shih , Juan-Yuan Wu , Water Lur
发明人： Hsueh-Hao Shih , Juan-Yuan Wu , Water Lur
IPC分类号： H01L21/28 , H01L29/51 , H01L21/331 , H01L21/31 , H01L21/3205 , H01L21/469 , H01L21/4763
CPC分类号： H01L21/28202 , H01L29/518
摘要： A method for adjusting the amount of doped nitride ions in a dielectric layer so that the nitride ions form bonds with silicon to increase the quality of an oxide layer. The method comprises the step of providing a silicon substrate. Next, a rapid thermal oxidation or furnace oxidation method is used to form an oxide layer over the silicon substrate. Gaseous mixtures having different ratios of nitrogen monoxide, nitrous oxide or ammonia to oxygen are concocted and then allowed to react at different reacting temperatures for controlling the nitride concentration level in the oxide layer. The nitride-doped oxide layer not only can stop the penetration of boron ions, but can also provide a stabilizing effect on the oxide layer/silicon substrate interface without degradation of electrical property, thereby improving the quality of a transistor.
摘要翻译：一种用于调节介电层中的掺杂氮化物离子的量使得氮化物离子与硅键合以提高氧化物层的质量的方法。该方法包括提供硅衬底的步骤。接下来，使用快速热氧化或炉氧化方法在硅衬底上形成氧化物层。将具有不同比例的一氧化氮，一氧化二氮或氨与氧的气态混合物混合，然后在不同的反应温度下反应，以控制氧化物层中的氮化物浓度水平。氮化物掺杂氧化物层不仅可以阻止硼离子的渗透，而且还可以在氧化物层/硅衬底界面上提供稳定效果，而不会降低电性能，从而提高晶体管的质量。

2. 发明授权

US5959311A Structure of an antenna effect monitor 失效
标题翻译：天线效果监视器的结构
公开(公告)号：US5959311A
公开(公告)日：1999-09-28
申请号：US172459
申请日：1998-10-14
申请人： Hsueh-Hao Shih , Mu-Chun Wang , Juan-Yuan Wu , Water Lur
发明人： Hsueh-Hao Shih , Mu-Chun Wang , Juan-Yuan Wu , Water Lur
IPC分类号： H01L23/485 , H01L23/544 , H01L23/58
CPC分类号： H01L24/05 , H01L22/34 , H01L23/58 , H01L2224/05556 , H01L2924/00014 , H01L2924/01033 , H01L2924/13091 , H01L2924/3011
摘要： An antenna effect monitor includes a transistor formed on a semiconductor substrate. The transistor gate is coupled to a doped polysilicon interconnect layer which is also coupled to an antenna effect monitoring unit. Several metal bonding pads float in an orderly fashion above the doped polysilicon interconnect layer without coupling with each other. Several small metal layers are formed in an orderly fashion above the doped polysilicon interconnect layer but are electrically coupled together by several via plugs in between. The top small metal layer is coupled to the top bonding pad. The bottom small metal layer is electrically coupled to the doped polysilicon interconnect layer. Then a passivation layer covers the substrate but leaves a pad opening to expose the top bonding pad.
摘要翻译：天线效应监视器包括形成在半导体衬底上的晶体管。晶体管栅极耦合到掺杂的多晶硅互连层，其也耦合到天线效应监测单元。几个金属接合焊盘在掺杂多晶硅互连层上方有序地浮动，而不会彼此耦合。几个小金属层以有序的方式形成在掺杂多晶硅互连层上方，但是通过其间的几个通孔电连接在一起。顶部小金属层耦合到顶部焊盘。底部小金属层电耦合到掺杂多晶硅互连层。然后钝化层覆盖衬底，但留下衬垫开口以露出顶部焊盘。

3. 发明授权

US06319861B1 Method of improving deposition 有权
标题翻译：改善沉积的方法
公开(公告)号：US06319861B1
公开(公告)日：2001-11-20
申请号：US09562529
申请日：2000-05-02
申请人： Hsueh-Hao Shih , Alan Cheng , Juan-Yuan Wu
发明人： Hsueh-Hao Shih , Alan Cheng , Juan-Yuan Wu
IPC分类号： H01L2131
CPC分类号： H01L21/02046 , H01L21/02049
摘要： A method for improving the quality of a deposited layer over a silicon substrate in a selective deposition where the silicon substrate has a native oxide layer thereon. A plasma reaction using a halogen compound as a reactive agent is performed so that the native oxide layer is transformed into a silicon halide layer and then removed at low pressure. A layer of the desired material is formed over the native oxide free silicon substrate surface by selective deposition.
摘要翻译：一种用于在选择性沉积中提高硅衬底上的沉积层的质量的方法，其中硅衬底上具有自然氧化物层。进行使用卤素化合物作为反应剂的等离子体反应，使得天然氧化物层转变成卤化硅层，然后在低压下除去。通过选择性沉积在所述自然无氧化物硅衬底表面上形成所需材料层。

4. 发明授权

US06221744B1 Method for forming a gate 失效
标题翻译：栅极形成方法
公开(公告)号：US06221744B1
公开(公告)日：2001-04-24
申请号：US09234618
申请日：1999-01-20
申请人： Hsueh-Hao Shih , Juan-Yuan Wu , Tri-Rung Yew
发明人： Hsueh-Hao Shih , Juan-Yuan Wu , Tri-Rung Yew
IPC分类号： H02L21305
CPC分类号： H01L21/28035 , H01L29/4925
摘要： A method for forming a gate on a substrate for manufacturing semiconductor devices is described. The present method comprises the step of providing a gate oxide layer on top of a substrate. A polysilicon layer is overlaid on the gate oxide layer and then, a amorphous silicon layer is formed thereon. The stack of amorphous and polysilicon layers is defined to form a gate structure on gate oxide layer. Next, a thermal treatment is performed on the gate structure.
摘要翻译：描述了一种用于在用于制造半导体器件的衬底上形成栅极的方法。本方法包括在衬底的顶部上提供栅氧化层的步骤。在栅氧化层上重叠多晶硅层，然后在其上形成非晶硅层。限定非晶和多晶硅层的堆叠以在栅极氧化物层上形成栅极结构。接下来，对栅极结构进行热处理。

5. 发明授权

US08062536B2 High density plasma chemical vapor deposition process 有权
标题翻译：高密度等离子体化学气相沉积工艺
公开(公告)号：US08062536B2
公开(公告)日：2011-11-22
申请号：US12729234
申请日：2010-03-22
申请人： Chih-Chien Liu , Ta-Shan Tseng , Wen-Bin Shieh , Juan-Yuan Wu , Water Lur , Shih-Wei Sun
发明人： Chih-Chien Liu , Ta-Shan Tseng , Wen-Bin Shieh , Juan-Yuan Wu , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/467 , H01L21/32 , H01L21/308 , H01L21/762
CPC分类号： H01L21/02112 , H01L21/02164 , H01L21/02274 , H01L21/0276 , H01L21/31612 , H01L21/32136 , H01L21/32139 , H01L21/76834 , H01L21/76837 , H01L21/76838
摘要： A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.
摘要翻译：在形成半导体器件时，将介电材料沉积在布线之间的间隙中的方法包括形成盖层并形成间隙，沉积高密度等离子体化学气相沉积（HDPCVD）电介质材料。第一和第二抗反射涂层可以形成在布线层上，第一和第二抗反射涂层由不同的材料制成。防反射涂层和布线层都被蚀刻通过以形成由间隙分开的布线。可以使用高密度等离子体化学气相沉积来填充布线之间的间隙。

6. 发明申请

US20060009005A1 CHEMICAL MECHANICAL POLISHING FOR FORMING A SHALLOW TRENCH ISOLATION STRUCTURE 有权
标题翻译：用于形成浅层隔离结构的化学机械抛光
公开(公告)号：US20060009005A1
公开(公告)日：2006-01-12
申请号：US10984045
申请日：2004-11-09
申请人： Coming Chen , Juan-Yuan Wu , Water Lur
发明人： Coming Chen , Juan-Yuan Wu , Water Lur
IPC分类号： H01L21/76 , H01L21/302
CPC分类号： H01L21/31144 , H01L21/31053 , H01L21/31056 , H01L21/76229 , Y10S438/942
摘要： A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relatively large active regions and a number of relatively small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is first formed. A number of shallow trenches are formed between the active regions. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial reverse active mask has an opening at a central part of each relatively large active region. The opening exposes a portion of the oxide layer. The opening has at least a dummy pattern. The oxide layer on the central part of each large active region is removed to expose the silicon nitride layer. The partial reverse active mask is removed. The oxide layer is planarized to expose the silicon nitride layer.
摘要翻译：公开了用于形成浅沟槽隔离的化学机械抛光的方法。提供具有多个有源区的基板，包括多个相对较大的有源区和多个相对小的有源区。该方法包括以下步骤。首先形成衬底上的氮化硅层。在活性区域之间形成多个浅沟槽。在衬底上形成氧化物层，使得浅沟槽被氧化物层填充。在氧化物层上形成部分反向有源掩模。部分反向有源掩模在每个相对大的有效区域的中心部分具有开口。开口暴露氧化物层的一部分。开口至少有一个虚拟图案。去除每个大的有源区的中心部分的氧化物层，以露出氮化硅层。去除部分反向主动掩模。将氧化物层平坦化以暴露氮化硅层。

7. 发明授权

US06810511B2 Method of designing active region pattern with shift dummy pattern 有权
标题翻译：用移动虚拟图案设计有源区域图案的方法
公开(公告)号：US06810511B2
公开(公告)日：2004-10-26
申请号：US10284683
申请日：2002-10-30
申请人： Coming Chen , Juan-Yuan Wu , Water Lur
发明人： Coming Chen , Juan-Yuan Wu , Water Lur
IPC分类号： G06F1750
CPC分类号： H01L21/31053 , H01L21/76229 , H01L23/528 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： A method of designing an active region pattern with a shifted dummy pattern, wherein an integrated circuit having an original active region pattern thereon is provided. The original active region pattern is expanded with a first parameter of line width to obtain a first pattern. By subtracting the first pattern, a second pattern is obtained. A dummy pattern which comprises an array of a plurality of elements is provided. By shifting the elements, a shifted dummy pattern is obtained. The second pattern and the shifted dummy pattern are combined, so that an overlapped region thereof is extracted as a combined dummy pattern. The combined dummy pattern is expanded with a second parameter of line width, so that a resultant dummy pattern is obtained. The resultant dummy pattern is added to the first pattern, so that the active region pattern with a shifted dummy pattern is obtained.
摘要翻译：一种设计具有偏移的虚设图案的有源区域图案的方法，其中提供其上具有原始有源区域图案的集成电路。原始活动区域图案用线宽的第一参数展开以获得第一图案。通过减去第一图案，获得第二图案。提供了包括多个元件的阵列的虚拟图案。通过移动元件，获得移动的虚拟图案。第二图案和移位的虚拟图案被组合，使得其重叠区域被提取为组合的虚拟图案。组合的虚拟图案用线宽的第二参数扩展，从而获得合成的虚拟图案。将所得到的虚拟图案添加到第一图案，从而获得具有偏移的虚设图案的有源区域图案。

8. 发明授权

US06790742B2 Chemical mechanical polishing in forming semiconductor device 有权
标题翻译：化学机械抛光成型半导体器件
公开(公告)号：US06790742B2
公开(公告)日：2004-09-14
申请号：US10293243
申请日：2002-11-13
申请人： Ming-Sheng Yang , Juan-Yuan Wu , Water Lur
发明人： Ming-Sheng Yang , Juan-Yuan Wu , Water Lur
IPC分类号： H01L2176
CPC分类号： H01L21/76229
摘要： A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relatively large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is formed. A number of shallow trenches are formed between the active regions one or more of which may constitute an alignment mark. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial reverse active mask exposes a portion of the oxide layer over the large active area and over the alignment mark. The oxide layer of each large active region and the alignment mark is removed. The partial reverse active mask is removed. The oxide layer is planarized.
摘要翻译：公开了用于形成浅沟槽隔离的化学机械抛光的方法。提供了具有多个有效区域的基板，包括多个相对较大的有源区域和多个相对小的有源区域。该方法包括以下步骤。形成衬底上的氮化硅层。在有源区域之间形成多个浅沟槽，其中一个或多个可以构成对准标记。在衬底上形成氧化物层，使得浅沟槽被氧化物层填充。在氧化物层上形成部分反向有源掩模。部分反向有源掩模将氧化物层的一部分暴露在大的有效区域上方和对准标记之上。去除每个大活性区域的氧化物层和对准标记。去除部分反向主动掩模。氧化层平坦化。

9. 发明授权

US6024106A Post-CMP wafer clean process 有权
标题翻译： CMP后晶圆清洁工艺
公开(公告)号：US6024106A
公开(公告)日：2000-02-15
申请号：US195794
申请日：1998-11-19
申请人： Ming-Sheng Yang , Juan-Yuan Wu , Water Lur
发明人： Ming-Sheng Yang , Juan-Yuan Wu , Water Lur
IPC分类号： B08B3/12 , C11D7/26 , C11D7/32 , C11D11/00 , H01L21/00 , B08B6/00 , C11D9/04
CPC分类号： H01L21/67057 , B08B3/12 , C11D11/0047 , C11D11/007 , C11D7/3218
摘要： A post-CMP wafer clean process. A post-CMP wafer is provided. A portion of particles and slurry are removed from the wafer by double side scrubber. The residual particles and slurry are then removed from the wafer in a solvent tank by magasonic and a solvent in the solvent tank includes an amine-based compound.
摘要翻译：后CMP晶圆清洁工艺。提供了后CMP晶片。通过双面洗涤器将一部分颗粒和浆料从晶片上除去。然后通过磁共振在溶剂罐中从晶片上除去残留的颗粒和浆料，溶剂槽中的溶剂包括胺类化合物。

10. 发明申请

US20100173490A1 HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION PROCESS 有权
标题翻译：高密度等离子体化学气相沉积工艺
公开(公告)号：US20100173490A1
公开(公告)日：2010-07-08
申请号：US12729234
申请日：2010-03-22
申请人： Chih-Chien Liu , Ta-Shan Tseng , Wen-Bin Shieh , Juan-Yuan Wu , Water Lur , Shih-Wei Sun
发明人： Chih-Chien Liu , Ta-Shan Tseng , Wen-Bin Shieh , Juan-Yuan Wu , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/768
CPC分类号： H01L21/02112 , H01L21/02164 , H01L21/02274 , H01L21/0276 , H01L21/31612 , H01L21/32136 , H01L21/32139 , H01L21/76834 , H01L21/76837 , H01L21/76838
摘要： A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.
摘要翻译：在形成半导体器件时，将介电材料沉积在布线之间的间隙中的方法包括形成盖层并形成间隙，沉积高密度等离子体化学气相沉积（HDPCVD）电介质材料。第一和第二抗反射涂层可以形成在布线层上，第一和第二抗反射涂层由不同的材料制成。防反射涂层和布线层都被蚀刻通过以形成由间隙分开的布线。可以使用高密度等离子体化学气相沉积来填充布线之间的间隙。

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