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1. 发明申请

US20090303792A1 METHOD FOR PROGRAMMING A MULTILEVEL MEMORY 有权
标题翻译：编程多个存储器的方法
公开(公告)号：US20090303792A1
公开(公告)日：2009-12-10
申请号：US12544025
申请日：2009-08-19
申请人： Hsin-Yi Ho , Nian-Kai Zous , I-Jen Huang , Yung-Feng Lin
发明人： Hsin-Yi Ho , Nian-Kai Zous , I-Jen Huang , Yung-Feng Lin
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5671 , G11C2211/5621
摘要： A method for programming a MLC memory is provided. The MLC memory has a number of bits, and each bit has a number of programmed states. Each programmed state has a first PV level. The method comprises (a) programming the bits of the memory having a Vt level lower than the PV level of a targeted programmed state into programmed bits by using a Vd bias BL; (b) ending this method if each bit of the memory has a Vt level not lower than the PV level of the targeted programmed state, otherwise, continuing the step (c); and (c) setting BL=BL+K1 and repeating the step (a) if each of the programmed bits has a Vt level lower than the PV level, while setting BL=BL−K2, and repeating the step (a) if at least one of the programmed bits has a Vt level not lower than the PV level.
摘要翻译：提供了一种用于编程MLC存储器的方法。 MLC存储器有多个位，每个位都有多个编程状态。每个编程状态具有第一PV级别。该方法包括（a）通过使用Vd偏置BL将具有低于目标编程状态的PV电平的Vt电平的存储器的位编程为编程位; （b）如果存储器的每个位的Vt电平不低于目标编程状态的PV电平，则结束该方法，否则继续步骤（c）; 以及（c）设定BL = BL + K1，并且如果每个编程的比特都具有低于PV水平的Vt级别，而设置BL = BL-K2，并重复步骤（a），如果在至少一个编程位的Vt电平不低于PV电平。

2. 发明申请

US20080310223A1 Method for programming a multilevel memory 有权
标题翻译：多级存储器编程方法
公开(公告)号：US20080310223A1
公开(公告)日：2008-12-18
申请号：US11812033
申请日：2007-06-14
申请人： Hsin-Yi Ho , Nian-Kai Zous , I-Jen Huang , Yung-Feng Lin
发明人： Hsin-Yi Ho , Nian-Kai Zous , I-Jen Huang , Yung-Feng Lin
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5671 , G11C2211/5621
摘要： A method for programming a MLC memory is provided. The MLC memory has a number of bits, and each bit has a number of programmed states. Each programmed state has a first PV level. The method comprises (a) programming the bits of the memory having a Vt level lower than the PV level of a targeted programmed state into programmed bits by using a Vd bias BL; (b) ending this method if each bit of the memory has a Vt level not lower than the PV level of the targeted programmed state, otherwise, continuing the step (c); and (c) setting BL=BL+K1 and repeating the step (a) if each of the programmed bits has a Vt level lower than the PV level, while setting BL=BL−K2, and repeating the step (a) if at least one of the programmed bits has a Vt level not lower than the PV level.
摘要翻译：提供了一种用于编程MLC存储器的方法。 MLC存储器有多个位，每个位都有多个编程状态。每个编程状态具有第一PV级别。该方法包括（a）通过使用Vd偏置BL将具有低于目标编程状态的PV电平的Vt电平的存储器的位编程为编程位; （b）如果存储器的每个位的Vt电平不低于目标编程状态的PV电平，则结束该方法，否则继续步骤（c）; 以及（c）设定BL = BL + K1，并且如果每个编程的比特都具有低于PV水平的Vt级别，而设置BL = BL-K2，并重复步骤（a），如果在至少一个编程位的Vt电平不低于PV电平。

3. 发明授权

US07961513B2 Method for programming a multilevel memory 有权
标题翻译：多级存储器编程方法
公开(公告)号：US07961513B2
公开(公告)日：2011-06-14
申请号：US12544025
申请日：2009-08-19
申请人： Hsin-Yi Ho , Nian-Kai Zous , I-Jen Huang , Yung-Feng Lin
发明人： Hsin-Yi Ho , Nian-Kai Zous , I-Jen Huang , Yung-Feng Lin
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5671 , G11C2211/5621
摘要： A method for programming a MLC memory includes (a) programming the bits of the memory having a Vt level lower than the PV level of a targeted programmed state into programmed bits by using a Vd bias BL; (b) ending this method if each bit of the memory has a Vt level not lower than the PV level of the targeted programmed state, otherwise, continuing the step (c); and (c) setting BL=BL+K1 and repeating the step (a) if each of the programmed bits has a Vt level lower than the PV level, while setting BL=BL−K2, and repeating the step (a) if at least one of the programmed bits has a Vt level not lower than the PV level.
摘要翻译：用于编程MLC存储器的方法包括（a）通过使用Vd偏置BL将具有低于目标编程状态的PV电平的Vt电平的存储器的位编程为编程位; （b）如果存储器的每个位的Vt电平不低于目标编程状态的PV电平，则结束该方法，否则继续步骤（c）; 以及（c）设定BL = BL + K1，并且如果每个编程的比特都具有低于PV水平的Vt级别，而设置BL = BL-K2，并重复步骤（a），如果在至少一个编程位的Vt电平不低于PV电平。

4. 发明授权

US07580292B2 Method for programming a multilevel memory 有权
标题翻译：多级存储器编程方法
公开(公告)号：US07580292B2
公开(公告)日：2009-08-25
申请号：US11812033
申请日：2007-06-14
申请人： Hsin-Yi Ho , Nian-Kai Zous , I-Jen Huang , Yung-Feng Lin
发明人： Hsin-Yi Ho , Nian-Kai Zous , I-Jen Huang , Yung-Feng Lin
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5671 , G11C2211/5621
摘要： A method for programming a MLC memory is provided. The MLC memory has a number of bits, and each bit has a number of programmed states. Each programmed state has a first PV level. The method includes (a) programming the bits of the memory having a Vt level lower than the PV level of a targeted programmed state into programmed bits by using a Vd bias BL; (b) ending this method if each bit of the memory has a Vt level not lower than the PV level of the targeted programmed state, otherwise, continuing the step (c); and (c) setting BL=BL+K1 and repeating the step (a) if each of the programmed bits has a Vt level lower than the PV level, while setting BL=BL−K2, and repeating the step (a) if at least one of the programmed bits has a Vt level not lower than the PV level.
摘要翻译：提供了一种用于编程MLC存储器的方法。 MLC存储器有多个位，每个位都有多个编程状态。每个编程状态具有第一PV级别。该方法包括（a）通过使用Vd偏置BL将具有低于目标编程状态的PV电平的Vt电平的存储器的位编程为编程位; （b）如果存储器的每个位的Vt电平不低于目标编程状态的PV电平，则结束该方法，否则继续步骤（c）; 以及（c）设定BL = BL + K1，并且如果每个编程的比特都具有低于PV水平的Vt级别，而设置BL = BL-K2，并重复步骤（a），如果在至少一个编程位的Vt电平不低于PV电平。

5. 发明授权

US07643337B2 Multi-bit flash memory and reading method thereof 有权
标题翻译：多位闪存及其读取方法
公开(公告)号：US07643337B2
公开(公告)日：2010-01-05
申请号：US11826574
申请日：2007-07-17
申请人： Yung-Feng Lin , Nian-Kai Zous , I-Jen Huang , Yin-Jen Chen
发明人： Yung-Feng Lin , Nian-Kai Zous , I-Jen Huang , Yin-Jen Chen
IPC分类号： G11C7/00
CPC分类号： G11C11/5642 , G11C2211/5634
摘要： A multi-bit flash memory and a reading method thereof. Multiple reference memory cells for saving reserved data are provided to operate together with multiple data memory cells. Before the data memory cells are read, data stored in the reference memory cell is sensed based on a present reference current. Then, a value of a new reference current for reading the data memory cells is determined according to a difference between the sensed data and the reserved data.
摘要翻译：一种多位闪存及其读取方法。提供用于保存预留数据的多个参考存储器单元以与多个数据存储单元一起操作。在读取数据存储单元之前，基于当前的参考电流感测存储在参考存储器单元中的数据。然后，根据感测数据和保留数据之间的差异来确定读取数据存储单元的新参考电流的值。

6. 发明申请

US20100085809A1 MULTI-BIT FLASH MEMORY AND READING METHOD THEREOF 有权
标题翻译：多位闪存及其读取方法
公开(公告)号：US20100085809A1
公开(公告)日：2010-04-08
申请号：US12636095
申请日：2009-12-11
申请人： Yung-Feng LIN , Nian-Kai Zous , I-Jen Huang , Yin-Jen Chen
发明人： Yung-Feng LIN , Nian-Kai Zous , I-Jen Huang , Yin-Jen Chen
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5642 , G11C2211/5634
摘要： A multi-bit flash memory and a reading method thereof. Multiple reference memory cells for saving reserved data are provided to operate together with multiple data memory cells. Before the data memory cells are read, data stored in the reference memory cell is sensed based on a present reference current. Then, a value of a new reference current for reading the data memory cells is determined according to a difference between the sensed data and the reserved data.
摘要翻译：一种多位闪存及其读取方法。提供用于保存预留数据的多个参考存储器单元以与多个数据存储单元一起操作。在读取数据存储单元之前，基于当前的参考电流感测存储在参考存储器单元中的数据。然后，根据感测数据和保留数据之间的差异来确定读取数据存储单元的新参考电流的值。

7. 发明授权

US08111547B2 Multi-bit flash memory and reading method thereof 有权
标题翻译：多位闪存及其读取方法
公开(公告)号：US08111547B2
公开(公告)日：2012-02-07
申请号：US12636095
申请日：2009-12-11
申请人： Yung-Feng Lin , Nian-Kai Zous , I-Jen Huang , Yin-Jen Chen
发明人： Yung-Feng Lin , Nian-Kai Zous , I-Jen Huang , Yin-Jen Chen
IPC分类号： G11C11/34
CPC分类号： G11C11/5642 , G11C2211/5634
摘要： A multi-bit flash memory and a reading method thereof. Multiple reference memory cells for saving reserved data are provided to operate together with multiple data memory cells. Before the data memory cells are read, data stored in the reference memory cell is sensed based on a present reference current. Then, a value of a new reference current for reading the data memory cells is determined according to a difference between the sensed data and the reserved data.
摘要翻译：一种多位闪存及其读取方法。提供用于保存预留数据的多个参考存储器单元以与多个数据存储单元一起操作。在读取数据存储单元之前，基于当前的参考电流感测存储在参考存储器单元中的数据。然后，根据感测数据和保留数据之间的差异来确定读取数据存储单元的新参考电流的值。

8. 发明申请

US20090021978A1 Multi-bit flash memory and reading method thereof 有权
标题翻译：多位闪存及其读取方法
公开(公告)号：US20090021978A1
公开(公告)日：2009-01-22
申请号：US11826574
申请日：2007-07-17
申请人： Yung-Feng Lin , Nian-Kai Zous , I-Jen Huang , Yin-Jen Chen
发明人： Yung-Feng Lin , Nian-Kai Zous , I-Jen Huang , Yin-Jen Chen
IPC分类号： G11C16/28
CPC分类号： G11C11/5642 , G11C2211/5634
摘要： A multi-bit flash memory and a reading method thereof. Multiple reference memory cells for saving reserved data are provided to operate together with multiple data memory cells. Before the data memory cells are read, data stored in the reference memory cell is sensed based on a present reference current. Then, a value of a new reference current for reading the data memory cells is determined according to a difference between the sensed data and the reserved data.
摘要翻译：一种多位闪存及其读取方法。提供用于保存预留数据的多个参考存储器单元以与多个数据存储单元一起操作。在读取数据存储单元之前，基于当前的参考电流感测存储在参考存储器单元中的数据。然后，根据感测数据和保留数据之间的差异来确定读取数据存储单元的新参考电流的值。

9. 发明申请

US20080158966A1 Variable Program and Program Verification Methods for a Virtual Ground Memory in Easing Buried Drain Contacts 有权
标题翻译：虚拟接地存储器可变程序和程序验证方法
公开(公告)号：US20080158966A1
公开(公告)日：2008-07-03
申请号：US11617007
申请日：2006-12-28
申请人： Ming-Shiang Chen , Wen-Pin Lu , I-Jen Huang , Chi Yuan Chin , Nian-Kai Zous
发明人： Ming-Shiang Chen , Wen-Pin Lu , I-Jen Huang , Chi Yuan Chin , Nian-Kai Zous
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/10 , G11C16/3454 , G11C16/3459
摘要： Methods for programming and program verification of a flash memory are described that ease the buried drain contact induced operation and increase the retention window. In a first aspect of the invention, a program operation method provides varying program biases which are applied to different groups of memory cells. The program biases can be supplied as drain bias voltages or gate bias voltages. The program biases vary depending on which group of memory cells is programmed. In one embodiment, a first drain voltage VD1 is applied to the first group of memory cells M0 and Mn. A second drain voltage VD2 is applied to the second group of memory cells M1 and Mn-1, where VD2=VD1+ΔVD. In a second aspect of the invention, a plurality of program verification voltage levels are selected to verify that the memory cells pass the program voltage levels.
摘要翻译：描述了用于快速存储器的编程和程序验证的方法，其易于埋入漏极接触引起的操作并增加保持窗口。在本发明的第一方面，一种程序操作方法提供了应用于不同组的存储单元的变化的程序偏移。程序偏置可以作为漏极偏置电压或栅极偏置电压提供。程序偏移根据编程的哪组存储单元而有所不同。在一个实施例中，第一漏极电压V SUB D1被施加到第一组存储器单元M 0和M N n。第二漏极电压V SUB D2被施加到第二组存储器单元M 1和M N-1 N，其中V D2 = V D1 + +ΔVD D 在本发明的第二方面中，选择多个程序验证电压电平以验证存储单元是否通过编程电压电平。

10. 发明授权

US07596028B2 Variable program and program verification methods for a virtual ground memory in easing buried drain contacts 有权
标题翻译：用于虚拟接地存储器的可变程序和程序验证方法，以缓解埋地漏接点
公开(公告)号：US07596028B2
公开(公告)日：2009-09-29
申请号：US11617007
申请日：2006-12-28
申请人： Ming Shiang Chen , Wen Pin Lu , I-Jen Huang , Chi Yuan Chin , Nian-Kai Zous
发明人： Ming Shiang Chen , Wen Pin Lu , I-Jen Huang , Chi Yuan Chin , Nian-Kai Zous
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C16/3454 , G11C16/3459
摘要： Methods for programming and program verification of a flash memory are described that ease the buried drain contact induced operation and increase the retention window. In a first aspect of the invention, a program operation method provides varying program biases which are applied to different groups of memory cells. The program biases can be supplied as drain bias voltages or gate bias voltages. The program biases vary depending on which group of memory cells is programmed. In one embodiment, a first drain voltage VD1 is applied to the first group of memory cells M0 and Mn. A second drain voltage VD2 is applied to the second group of memory cells M1 and Mn-1, where VD2=VD1+ΔVD. In a second aspect of the invention, a plurality of program verification voltage levels are selected to verify that the memory cells pass the program voltage levels.
摘要翻译：描述了用于快速存储器的编程和程序验证的方法，其易于埋入漏极接触引起的操作并增加保持窗口。在本发明的第一方面，一种程序操作方法提供了应用于不同组的存储单元的变化的程序偏移。程序偏置可以作为漏极偏置电压或栅极偏置电压提供。程序偏移根据编程的哪组存储单元而有所不同。在一个实施例中，将第一漏极电压VD1施加到第一组存储器单元M0和Mn。第二漏极电压VD2被施加到第二组存储器单元M1和Mn-1，其中VD2 = VD1 + DeltaVD。在本发明的第二方面中，选择多个程序验证电压电平以验证存储单元是否通过编程电压电平。

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