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1. 发明申请

US20100085809A1 MULTI-BIT FLASH MEMORY AND READING METHOD THEREOF 有权
标题翻译：多位闪存及其读取方法
公开(公告)号：US20100085809A1
公开(公告)日：2010-04-08
申请号：US12636095
申请日：2009-12-11
申请人： Yung-Feng LIN , Nian-Kai Zous , I-Jen Huang , Yin-Jen Chen
发明人： Yung-Feng LIN , Nian-Kai Zous , I-Jen Huang , Yin-Jen Chen
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5642 , G11C2211/5634
摘要： A multi-bit flash memory and a reading method thereof. Multiple reference memory cells for saving reserved data are provided to operate together with multiple data memory cells. Before the data memory cells are read, data stored in the reference memory cell is sensed based on a present reference current. Then, a value of a new reference current for reading the data memory cells is determined according to a difference between the sensed data and the reserved data.
摘要翻译：一种多位闪存及其读取方法。提供用于保存预留数据的多个参考存储器单元以与多个数据存储单元一起操作。在读取数据存储单元之前，基于当前的参考电流感测存储在参考存储器单元中的数据。然后，根据感测数据和保留数据之间的差异来确定读取数据存储单元的新参考电流的值。

2. 发明授权

US07643337B2 Multi-bit flash memory and reading method thereof 有权
标题翻译：多位闪存及其读取方法
公开(公告)号：US07643337B2
公开(公告)日：2010-01-05
申请号：US11826574
申请日：2007-07-17
申请人： Yung-Feng Lin , Nian-Kai Zous , I-Jen Huang , Yin-Jen Chen
发明人： Yung-Feng Lin , Nian-Kai Zous , I-Jen Huang , Yin-Jen Chen
IPC分类号： G11C7/00
CPC分类号： G11C11/5642 , G11C2211/5634
摘要： A multi-bit flash memory and a reading method thereof. Multiple reference memory cells for saving reserved data are provided to operate together with multiple data memory cells. Before the data memory cells are read, data stored in the reference memory cell is sensed based on a present reference current. Then, a value of a new reference current for reading the data memory cells is determined according to a difference between the sensed data and the reserved data.
摘要翻译：一种多位闪存及其读取方法。提供用于保存预留数据的多个参考存储器单元以与多个数据存储单元一起操作。在读取数据存储单元之前，基于当前的参考电流感测存储在参考存储器单元中的数据。然后，根据感测数据和保留数据之间的差异来确定读取数据存储单元的新参考电流的值。

3. 发明授权

US08111547B2 Multi-bit flash memory and reading method thereof 有权
标题翻译：多位闪存及其读取方法
公开(公告)号：US08111547B2
公开(公告)日：2012-02-07
申请号：US12636095
申请日：2009-12-11
申请人： Yung-Feng Lin , Nian-Kai Zous , I-Jen Huang , Yin-Jen Chen
发明人： Yung-Feng Lin , Nian-Kai Zous , I-Jen Huang , Yin-Jen Chen
IPC分类号： G11C11/34
CPC分类号： G11C11/5642 , G11C2211/5634
摘要： A multi-bit flash memory and a reading method thereof. Multiple reference memory cells for saving reserved data are provided to operate together with multiple data memory cells. Before the data memory cells are read, data stored in the reference memory cell is sensed based on a present reference current. Then, a value of a new reference current for reading the data memory cells is determined according to a difference between the sensed data and the reserved data.
摘要翻译：一种多位闪存及其读取方法。提供用于保存预留数据的多个参考存储器单元以与多个数据存储单元一起操作。在读取数据存储单元之前，基于当前的参考电流感测存储在参考存储器单元中的数据。然后，根据感测数据和保留数据之间的差异来确定读取数据存储单元的新参考电流的值。

4. 发明申请

US20090021978A1 Multi-bit flash memory and reading method thereof 有权
标题翻译：多位闪存及其读取方法
公开(公告)号：US20090021978A1
公开(公告)日：2009-01-22
申请号：US11826574
申请日：2007-07-17
申请人： Yung-Feng Lin , Nian-Kai Zous , I-Jen Huang , Yin-Jen Chen
发明人： Yung-Feng Lin , Nian-Kai Zous , I-Jen Huang , Yin-Jen Chen
IPC分类号： G11C16/28
CPC分类号： G11C11/5642 , G11C2211/5634
摘要： A multi-bit flash memory and a reading method thereof. Multiple reference memory cells for saving reserved data are provided to operate together with multiple data memory cells. Before the data memory cells are read, data stored in the reference memory cell is sensed based on a present reference current. Then, a value of a new reference current for reading the data memory cells is determined according to a difference between the sensed data and the reserved data.
摘要翻译：一种多位闪存及其读取方法。提供用于保存预留数据的多个参考存储器单元以与多个数据存储单元一起操作。在读取数据存储单元之前，基于当前的参考电流感测存储在参考存储器单元中的数据。然后，根据感测数据和保留数据之间的差异来确定读取数据存储单元的新参考电流的值。

5. 发明授权

US08593850B2 Diode-less array for one-time programmable memory 有权
公开(公告)号：US08593850B2
公开(公告)日：2013-11-26
申请号：US12346706
申请日：2008-12-30
申请人： Kuan-Fu Chen , Yin-Jen Chen , Tzung-Ting Han , Ming-Shang Chen
发明人： Kuan-Fu Chen , Yin-Jen Chen , Tzung-Ting Han , Ming-Shang Chen
IPC分类号： G11C17/00 , G11C17/06 , G11C17/18
CPC分类号： G11C17/16 , H01L21/8221 , H01L27/0688 , H01L27/101
摘要： A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.

6. 发明申请

US20090116274A1 DIODE-LESS ARRAY FOR ONE-TIME PROGRAMMABLE MEMORY 有权
标题翻译：一次性可编程存储器的二极管阵列
公开(公告)号：US20090116274A1
公开(公告)日：2009-05-07
申请号：US12346706
申请日：2008-12-30
申请人： Kuan-Fu Chen , Yin-Jen Chen , Tzung-Ting Han , Ming-Shang Chen
发明人： Kuan-Fu Chen , Yin-Jen Chen , Tzung-Ting Han , Ming-Shang Chen
IPC分类号： G11C17/00 , H01L29/66
CPC分类号： G11C17/16 , H01L21/8221 , H01L27/0688 , H01L27/101
摘要： A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.
摘要翻译：一次可编程存储器阵列包括在第一行方向上延伸并且设置在第一高度的第一行导体，在第二行方向上延伸并设置在第二高度的第二行导体和沿列方向延伸的列导体并且设置成与第一行导体相邻并且与第二行导体相邻。阵列还包括覆盖列导体的至少一部分的电介质层，耦合在列导体上的电介质层和第二行导体之间的熔丝链。

7. 发明申请

US20070269947A1 Method for manufacturing NAND flash memory 有权
标题翻译：制造NAND闪存的方法
公开(公告)号：US20070269947A1
公开(公告)日：2007-11-22
申请号：US11435459
申请日：2006-05-16
申请人： Kuei-Yun Chen , Chun-Lien Su , Yin-Jen Chen , Ming-Shang Chen
发明人： Kuei-Yun Chen , Chun-Lien Su , Yin-Jen Chen , Ming-Shang Chen
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521
摘要： A method for manufacturing a NAND flash memory is provided. First, a substrate is provided. Next, a tunneling dielectric layer, a first conductive layer and a mask layer are sequentially formed on the substrate. Next, a plurality of isolation structures is formed in the mask layer, the first conductive layer, the tunneling dielectric layer and the substrate. Next, the mask layer is removed, so that the top surface of each isolation structure is higher than that of the first conductive layer. Next, a second conductive layer is formed on the exposed sidewalls of the isolation structures. Next, an inter-gate dielectric layer and a third conductive layer are sequentially formed on the substrate.
摘要翻译：提供一种制造NAND闪速存储器的方法。首先，提供基板。接下来，在衬底上依次形成隧穿介质层，第一导电层和掩模层。接下来，在掩模层，第一导电层，隧道电介质层和基板中形成多个隔离结构。接下来，去除掩模层，使得每个隔离结构的顶表面高于第一导电层的顶表面。接下来，在隔离结构的暴露的侧壁上形成第二导电层。接下来，在衬底上依次形成栅极间电介质层和第三导电层。

8. 发明授权

US08552528B2 Diode-less array for one-time programmable memory 失效
公开(公告)号：US08552528B2
公开(公告)日：2013-10-08
申请号：US13240589
申请日：2011-09-22
申请人： Kuan-Fu Chen , Yin-Jen Chen , Tzung-Ting Han , Ming Shang Chen
发明人： Kuan-Fu Chen , Yin-Jen Chen , Tzung-Ting Han , Ming Shang Chen
IPC分类号： H01L23/52 , H01L29/40 , G11C5/06 , G11C17/00
CPC分类号： G11C17/16 , H01L21/8221 , H01L27/0688 , H01L27/101
摘要： A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.

9. 发明申请

US20120008363A1 Diode-Less Array for One-Time Programmable Memory 失效
标题翻译：一次性可编程存储器的二极管阵列
公开(公告)号：US20120008363A1
公开(公告)日：2012-01-12
申请号：US13240589
申请日：2011-09-22
申请人： Kuan-Fu Chen , Yin-Jen Chen , Tzung-Ting Han , Ming Shang Chen
发明人： Kuan-Fu Chen , Yin-Jen Chen , Tzung-Ting Han , Ming Shang Chen
IPC分类号： G11C17/16 , G11C17/00
CPC分类号： G11C17/16 , H01L21/8221 , H01L27/0688 , H01L27/101
摘要： A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.
摘要翻译：一次可编程存储器阵列包括在第一行方向上延伸并且设置在第一高度的第一行导体，在第二行方向上延伸并设置在第二高度的第二行导体和沿列方向延伸的列导体并且设置成与第一行导体相邻并且与第二行导体相邻。阵列还包括覆盖列导体的至少一部分的电介质层，耦合在列导体上的电介质层和第二行导体之间的熔丝链。

10. 发明授权

US07592036B2 Method for manufacturing NAND flash memory 有权
标题翻译：制造NAND闪存的方法
公开(公告)号：US07592036B2
公开(公告)日：2009-09-22
申请号：US11435459
申请日：2006-05-16
申请人： Kuei-Yun Chen , Chun-Lien Su , Yin-Jen Chen , Ming-Shang Chen
发明人： Kuei-Yun Chen , Chun-Lien Su , Yin-Jen Chen , Ming-Shang Chen
IPC分类号： B05D5/12
CPC分类号： H01L27/115 , H01L27/11521
摘要： A method for manufacturing a NAND flash memory is provided. First, a substrate is provided. Next, a tunneling dielectric layer, a first conductive layer and a mask layer are sequentially formed on the substrate. Next, a plurality of isolation structures is formed in the mask layer, the first conductive layer, the tunneling dielectric layer and the substrate. Next, the mask layer is removed, so that the top surface of each isolation structure is higher than that of the first conductive layer. Next, a second conductive layer is formed on the exposed sidewalls of the isolation structures. Next, an inter-gate dielectric layer and a third conductive layer are sequentially formed on the substrate.
摘要翻译：提供一种制造NAND闪速存储器的方法。首先，提供基板。接下来，在衬底上依次形成隧穿介质层，第一导电层和掩模层。接下来，在掩模层，第一导电层，隧道电介质层和基板中形成多个隔离结构。接下来，去除掩模层，使得每个隔离结构的顶表面高于第一导电层的顶表面。接下来，在隔离结构的暴露的侧壁上形成第二导电层。接下来，在衬底上依次形成栅极间电介质层和第三导电层。

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