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1. 发明申请

US20090303792A1 METHOD FOR PROGRAMMING A MULTILEVEL MEMORY 有权
标题翻译：编程多个存储器的方法
公开(公告)号：US20090303792A1
公开(公告)日：2009-12-10
申请号：US12544025
申请日：2009-08-19
申请人： Hsin-Yi Ho , Nian-Kai Zous , I-Jen Huang , Yung-Feng Lin
发明人： Hsin-Yi Ho , Nian-Kai Zous , I-Jen Huang , Yung-Feng Lin
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5671 , G11C2211/5621
摘要： A method for programming a MLC memory is provided. The MLC memory has a number of bits, and each bit has a number of programmed states. Each programmed state has a first PV level. The method comprises (a) programming the bits of the memory having a Vt level lower than the PV level of a targeted programmed state into programmed bits by using a Vd bias BL; (b) ending this method if each bit of the memory has a Vt level not lower than the PV level of the targeted programmed state, otherwise, continuing the step (c); and (c) setting BL=BL+K1 and repeating the step (a) if each of the programmed bits has a Vt level lower than the PV level, while setting BL=BL−K2, and repeating the step (a) if at least one of the programmed bits has a Vt level not lower than the PV level.
摘要翻译：提供了一种用于编程MLC存储器的方法。 MLC存储器有多个位，每个位都有多个编程状态。每个编程状态具有第一PV级别。该方法包括（a）通过使用Vd偏置BL将具有低于目标编程状态的PV电平的Vt电平的存储器的位编程为编程位; （b）如果存储器的每个位的Vt电平不低于目标编程状态的PV电平，则结束该方法，否则继续步骤（c）; 以及（c）设定BL = BL + K1，并且如果每个编程的比特都具有低于PV水平的Vt级别，而设置BL = BL-K2，并重复步骤（a），如果在至少一个编程位的Vt电平不低于PV电平。

2. 发明申请

US20080310223A1 Method for programming a multilevel memory 有权
标题翻译：多级存储器编程方法
公开(公告)号：US20080310223A1
公开(公告)日：2008-12-18
申请号：US11812033
申请日：2007-06-14
申请人： Hsin-Yi Ho , Nian-Kai Zous , I-Jen Huang , Yung-Feng Lin
发明人： Hsin-Yi Ho , Nian-Kai Zous , I-Jen Huang , Yung-Feng Lin
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5671 , G11C2211/5621
摘要： A method for programming a MLC memory is provided. The MLC memory has a number of bits, and each bit has a number of programmed states. Each programmed state has a first PV level. The method comprises (a) programming the bits of the memory having a Vt level lower than the PV level of a targeted programmed state into programmed bits by using a Vd bias BL; (b) ending this method if each bit of the memory has a Vt level not lower than the PV level of the targeted programmed state, otherwise, continuing the step (c); and (c) setting BL=BL+K1 and repeating the step (a) if each of the programmed bits has a Vt level lower than the PV level, while setting BL=BL−K2, and repeating the step (a) if at least one of the programmed bits has a Vt level not lower than the PV level.
摘要翻译：提供了一种用于编程MLC存储器的方法。 MLC存储器有多个位，每个位都有多个编程状态。每个编程状态具有第一PV级别。该方法包括（a）通过使用Vd偏置BL将具有低于目标编程状态的PV电平的Vt电平的存储器的位编程为编程位; （b）如果存储器的每个位的Vt电平不低于目标编程状态的PV电平，则结束该方法，否则继续步骤（c）; 以及（c）设定BL = BL + K1，并且如果每个编程的比特都具有低于PV水平的Vt级别，而设置BL = BL-K2，并重复步骤（a），如果在至少一个编程位的Vt电平不低于PV电平。

3. 发明授权

US07961513B2 Method for programming a multilevel memory 有权
标题翻译：多级存储器编程方法
公开(公告)号：US07961513B2
公开(公告)日：2011-06-14
申请号：US12544025
申请日：2009-08-19
申请人： Hsin-Yi Ho , Nian-Kai Zous , I-Jen Huang , Yung-Feng Lin
发明人： Hsin-Yi Ho , Nian-Kai Zous , I-Jen Huang , Yung-Feng Lin
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5671 , G11C2211/5621
摘要： A method for programming a MLC memory includes (a) programming the bits of the memory having a Vt level lower than the PV level of a targeted programmed state into programmed bits by using a Vd bias BL; (b) ending this method if each bit of the memory has a Vt level not lower than the PV level of the targeted programmed state, otherwise, continuing the step (c); and (c) setting BL=BL+K1 and repeating the step (a) if each of the programmed bits has a Vt level lower than the PV level, while setting BL=BL−K2, and repeating the step (a) if at least one of the programmed bits has a Vt level not lower than the PV level.
摘要翻译：用于编程MLC存储器的方法包括（a）通过使用Vd偏置BL将具有低于目标编程状态的PV电平的Vt电平的存储器的位编程为编程位; （b）如果存储器的每个位的Vt电平不低于目标编程状态的PV电平，则结束该方法，否则继续步骤（c）; 以及（c）设定BL = BL + K1，并且如果每个编程的比特都具有低于PV水平的Vt级别，而设置BL = BL-K2，并重复步骤（a），如果在至少一个编程位的Vt电平不低于PV电平。

4. 发明授权

US07580292B2 Method for programming a multilevel memory 有权
标题翻译：多级存储器编程方法
公开(公告)号：US07580292B2
公开(公告)日：2009-08-25
申请号：US11812033
申请日：2007-06-14
申请人： Hsin-Yi Ho , Nian-Kai Zous , I-Jen Huang , Yung-Feng Lin
发明人： Hsin-Yi Ho , Nian-Kai Zous , I-Jen Huang , Yung-Feng Lin
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5671 , G11C2211/5621
摘要： A method for programming a MLC memory is provided. The MLC memory has a number of bits, and each bit has a number of programmed states. Each programmed state has a first PV level. The method includes (a) programming the bits of the memory having a Vt level lower than the PV level of a targeted programmed state into programmed bits by using a Vd bias BL; (b) ending this method if each bit of the memory has a Vt level not lower than the PV level of the targeted programmed state, otherwise, continuing the step (c); and (c) setting BL=BL+K1 and repeating the step (a) if each of the programmed bits has a Vt level lower than the PV level, while setting BL=BL−K2, and repeating the step (a) if at least one of the programmed bits has a Vt level not lower than the PV level.
摘要翻译：提供了一种用于编程MLC存储器的方法。 MLC存储器有多个位，每个位都有多个编程状态。每个编程状态具有第一PV级别。该方法包括（a）通过使用Vd偏置BL将具有低于目标编程状态的PV电平的Vt电平的存储器的位编程为编程位; （b）如果存储器的每个位的Vt电平不低于目标编程状态的PV电平，则结束该方法，否则继续步骤（c）; 以及（c）设定BL = BL + K1，并且如果每个编程的比特都具有低于PV水平的Vt级别，而设置BL = BL-K2，并重复步骤（a），如果在至少一个编程位的Vt电平不低于PV电平。

5. 发明授权

US07643337B2 Multi-bit flash memory and reading method thereof 有权
标题翻译：多位闪存及其读取方法
公开(公告)号：US07643337B2
公开(公告)日：2010-01-05
申请号：US11826574
申请日：2007-07-17
申请人： Yung-Feng Lin , Nian-Kai Zous , I-Jen Huang , Yin-Jen Chen
发明人： Yung-Feng Lin , Nian-Kai Zous , I-Jen Huang , Yin-Jen Chen
IPC分类号： G11C7/00
CPC分类号： G11C11/5642 , G11C2211/5634
摘要： A multi-bit flash memory and a reading method thereof. Multiple reference memory cells for saving reserved data are provided to operate together with multiple data memory cells. Before the data memory cells are read, data stored in the reference memory cell is sensed based on a present reference current. Then, a value of a new reference current for reading the data memory cells is determined according to a difference between the sensed data and the reserved data.
摘要翻译：一种多位闪存及其读取方法。提供用于保存预留数据的多个参考存储器单元以与多个数据存储单元一起操作。在读取数据存储单元之前，基于当前的参考电流感测存储在参考存储器单元中的数据。然后，根据感测数据和保留数据之间的差异来确定读取数据存储单元的新参考电流的值。

6. 发明授权

US08111547B2 Multi-bit flash memory and reading method thereof 有权
标题翻译：多位闪存及其读取方法
公开(公告)号：US08111547B2
公开(公告)日：2012-02-07
申请号：US12636095
申请日：2009-12-11
申请人： Yung-Feng Lin , Nian-Kai Zous , I-Jen Huang , Yin-Jen Chen
发明人： Yung-Feng Lin , Nian-Kai Zous , I-Jen Huang , Yin-Jen Chen
IPC分类号： G11C11/34
CPC分类号： G11C11/5642 , G11C2211/5634
摘要： A multi-bit flash memory and a reading method thereof. Multiple reference memory cells for saving reserved data are provided to operate together with multiple data memory cells. Before the data memory cells are read, data stored in the reference memory cell is sensed based on a present reference current. Then, a value of a new reference current for reading the data memory cells is determined according to a difference between the sensed data and the reserved data.
摘要翻译：一种多位闪存及其读取方法。提供用于保存预留数据的多个参考存储器单元以与多个数据存储单元一起操作。在读取数据存储单元之前，基于当前的参考电流感测存储在参考存储器单元中的数据。然后，根据感测数据和保留数据之间的差异来确定读取数据存储单元的新参考电流的值。

7. 发明申请

US20090021978A1 Multi-bit flash memory and reading method thereof 有权
标题翻译：多位闪存及其读取方法
公开(公告)号：US20090021978A1
公开(公告)日：2009-01-22
申请号：US11826574
申请日：2007-07-17
申请人： Yung-Feng Lin , Nian-Kai Zous , I-Jen Huang , Yin-Jen Chen
发明人： Yung-Feng Lin , Nian-Kai Zous , I-Jen Huang , Yin-Jen Chen
IPC分类号： G11C16/28
CPC分类号： G11C11/5642 , G11C2211/5634
摘要： A multi-bit flash memory and a reading method thereof. Multiple reference memory cells for saving reserved data are provided to operate together with multiple data memory cells. Before the data memory cells are read, data stored in the reference memory cell is sensed based on a present reference current. Then, a value of a new reference current for reading the data memory cells is determined according to a difference between the sensed data and the reserved data.
摘要翻译：一种多位闪存及其读取方法。提供用于保存预留数据的多个参考存储器单元以与多个数据存储单元一起操作。在读取数据存储单元之前，基于当前的参考电流感测存储在参考存储器单元中的数据。然后，根据感测数据和保留数据之间的差异来确定读取数据存储单元的新参考电流的值。

8. 发明授权

US08624981B2 Testing method for camera 失效
标题翻译：相机测试方法
公开(公告)号：US08624981B2
公开(公告)日：2014-01-07
申请号：US13585853
申请日：2012-08-15
申请人： Yung-Feng Lin
发明人： Yung-Feng Lin
IPC分类号： H04N17/00 , H04N17/02
CPC分类号： H04N17/002 , H04N5/2253
摘要： A testing method includes: providing a camera under test and a planar light source having a first mark, wherein the camera includes a voice coil motor (VCM) and a lens module is fixed on the VCM by glue, the VCM moves the lens module, the VCM includes an elastic tab for limiting and restoring the movement of the lens module; taking an image of a light source using the camera during the movement of the VCM; displaying the image having the first mark; determining if the first mark tilts using a detector; displaying a first message indicating that the tab is not stuck by glue when the detector determines the first mark does not tilt; and displaying a second message indicating that the tab is stuck by glue when the detector determines the first mark tilts.
摘要翻译：一种测试方法，包括：提供被测相机和具有第一标记的平面光源，其中相机包括音圈电机（VCM），透镜模块通过胶水固定在VCM上，VCM移动透镜模块， VCM包括用于限制和恢复透镜模块的运动的弹性片; 在VCM运动期间使用相机拍摄光源的图像; 显示具有第一标记的图像; 确定第一标记是否使用检测器倾斜; 当检测器确定第一标记不倾斜时，显示指示标签不被胶水粘住的第一消息; 以及当所述检测器确定所述第一标记倾斜时，显示指示所述标签被粘合的第二消息。

9. 发明授权

US08453006B2 Command decoding method and circuit of the same 有权
标题翻译：命令解码方法与电路相同
公开(公告)号：US08453006B2
公开(公告)日：2013-05-28
申请号：US12820443
申请日：2010-06-22
申请人： Yung-Feng Lin
发明人： Yung-Feng Lin
IPC分类号： G06F1/04
CPC分类号： G06F1/04 , G06F13/161
摘要： A decoding circuit for decoding a command is provided. The received command is transmitted during at least two clock periods of a clock signal, and the received command is divided to a former encoded data and a latter encoded data. The decoding circuit includes a pre-trigger signal generating unit, a comparing unit, and a starting signal generating unit. The pre-trigger signal generating unit receives the former encoded data and generates a pre-trigger signal when the former encoded data of the received command matches the corresponding former encoded data of a predetermined command. The comparing unit generates a match signal when the latter encoded data of the received command is the same with the latter encoded data of the predetermined command. The starting signal generating unit outputs a starting signal according to the pre-trigger signal and the match signal. The starting signal starts a corresponding operation of the predetermined command.
摘要翻译：提供了一种用于解码命令的解码电路。接收到的命令在时钟信号的至少两个时钟周期期间被发送，并且所接收的命令被划分成前一个编码数据和后面的编码数据。解码电路包括预触发信号生成单元，比较单元和起始信号生成单元。预触发信号产生单元接收先前的编码数据，并且当接收到的命令的前一编码数据与预定命令的对应的先前编码数据匹配时，产生预触发信号。当所接收的命令的后一编码数据与预定命令的后一个编码数据相同时，比较单元产生匹配信号。启动信号生成单元根据预触发信号和匹配信号输出起始信号。启动信号开始相应的预定命令的操作。

10. 发明授权

US08264900B2 Data sensing arrangement using first and second bit lines 有权
标题翻译：使用第一和第二位线的数据传感装置
公开(公告)号：US08264900B2
公开(公告)日：2012-09-11
申请号：US13300141
申请日：2011-11-18
申请人： Yung-Feng Lin , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Yung-Feng Lin , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G11C7/00
CPC分类号： G11C7/1048 , G11C16/28
摘要： Over-erasure induced noise on a data line in a nonvolatile memory that couples into an adjacent data line is mitigated by using twisted data lines and differential sensing amplifiers. Noise coupled into data lines is compensated by similar noise coupled into reference data lines and cancelled in the differential sensing amplifiers.
摘要翻译：通过使用扭曲的数据线和差分感测放大器来减轻耦合到相邻数据线的非易失性存储器中的数据线上的过度擦除感应噪声。耦合到数据线中的噪声由耦合到参考数据线中的相似噪声补偿并在差分感测放大器中被消除。

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