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1. 发明授权

US07093206B2 Computer aided design method and apparatus for modeling and analyzing on-chip interconnect structures 失效
标题翻译：用于对片上互连结构进行建模和分析的计算机辅助设计方法和装置
公开(公告)号：US07093206B2
公开(公告)日：2006-08-15
申请号：US10690238
申请日：2003-10-21
申请人： Minakshisundaran B. Anand , Matthew S. Angyal , Alina Deutsch , Ibrahim M. Elfadel , Gerard V. Kopcsay , Barry J. Rubin , Howard H. Smith
发明人： Minakshisundaran B. Anand , Matthew S. Angyal , Alina Deutsch , Ibrahim M. Elfadel , Gerard V. Kopcsay , Barry J. Rubin , Howard H. Smith
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A computer aided design (CAD) system. A template generation engine generates templates from interconnect configuration files. A field solver generates high frequency passive element relationships from the templates. A circuit builder generates circuit description files from device technology models and from high frequency passive element relationships. Parameterized circuit description models may be generated for large range of sensitivity analyses. A simulator simulates circuit responses for transmission line models from the circuit description files. Interconnect configuration files may be generated by a geometry and material definition module that receives process description data from a designer.
摘要翻译：计算机辅助设计（CAD）系统。模板生成引擎从互连配置文件生成模板。场解算器从模板生成高频无源元件关系。电路构建器从器件技术模型和高频无源元件关系生成电路描述文件。可以为大范围的灵敏度分析生成参数化电路描述模型。模拟器模拟来自电路描述文件的传输线模型的电路响应。互连配置文件可以由接收来自设计者的过程描述数据的几何和材料定义模块生成。

2. 发明授权

US06418401B1 Efficient method for modeling three-dimensional interconnect structures for frequency-dependent crosstalk simulation 失效
标题翻译：针对频率相关串扰模拟的三维互连结构建模的高效方法
公开(公告)号：US06418401B1
公开(公告)日：2002-07-09
申请号：US09248667
申请日：1999-02-11
申请人： Allan H. Dansky , Alina Deutsch , Gerard V. Kopcsay , Phillip J. Restle , Howard H. Smith
发明人： Allan H. Dansky , Alina Deutsch , Gerard V. Kopcsay , Phillip J. Restle , Howard H. Smith
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A method for reducing the computation time and improving the productivity in designing high-performance microprocessor chips that have no failures—due to crosstalk noise. The technique allows a very fast calculation of tables of frequency-dependent circuit parameters needed for accurate crosstalk prediction on lossy on-chip interconnections. These tables of parameters are the basis for CAD tools that perform crosstalk checking on >10K critical nets on typical microprocessor chips. A fast table generation allows for rapid incorporation of design or processing changes and transition to more advanced technologies.
摘要翻译：一种减少计算时间并提高设计高性能微处理器芯片的生产率的方法，这些微处理器芯片由于串扰噪声而无故障。该技术允许非常快速地计算在有损片上互连上精确串扰预测所需的频率相关电路参数表。这些参数表是在典型微处理器芯片上对> 10K关键网进行串扰检查的CAD工具的基础。快速表生成允许快速结合设计或处理更改并转换到更先进的技术。

3. 发明授权

US06323050B1 Method for evaluating decoupling capacitor placement for VLSI chips 失效
标题翻译：评估VLSI芯片去耦电容放置的方法
公开(公告)号：US06323050B1
公开(公告)日：2001-11-27
申请号：US09677285
申请日：2000-10-02
申请人： Allan H. Dansky , Wiren D. Becker , Howard H. Smith , Peter J. Camporese , Kwok Fai Eng , Dale E. Hoffman , Bhupindra Singh
发明人： Allan H. Dansky , Wiren D. Becker , Howard H. Smith , Peter J. Camporese , Kwok Fai Eng , Dale E. Hoffman , Bhupindra Singh
IPC分类号： H01L2166
CPC分类号： G06F17/5072 , G06F17/5036
摘要： A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.
摘要翻译：公开了一种评估超大规模集成芯片（VLSI）的去耦电容放置的方法。该方法中包括对每个去耦电容器的使用情况，与器件的距离以及器件和去耦电容器的位置的分析。还解决了组件的方向和尺寸。

4. 发明授权

US4054073A Jeweler's tool 失效
标题翻译：珠宝商{3 s工具
公开(公告)号：US4054073A
公开(公告)日：1977-10-18
申请号：US743564
申请日：1976-11-22
申请人： Howard H. Smith , Glenn E. Christensen
发明人： Howard H. Smith , Glenn E. Christensen
IPC分类号： A44C9/00 , B26D1/30 , B26D3/00
CPC分类号： A44C9/0084 , B26D1/30 , Y10S83/917 , Y10S83/935 , Y10T83/0596 , Y10T83/8801 , Y10T83/8809
摘要： A cutting tool is provided with a plurality of circular cutting blades of varying predetermined thicknesses to shear sections from rings made of precious metals. Each blade is formed with a notched perimeter to provide a pair of blade cutting edges. The blades are mounted on a spindle for rotation therewith, while the spindle is rotatably mounted in a plurality of cutting blocks which are affixed to a base in an alternating arrangement with the aforesaid blades. The cutting blocks define cutting edges so that rotation of the spindle causes the blade cutting edges formed by the notched perimeter to come into a simultaneous shearing relation with the cutting edges of the two adjacent cutting blocks. Further rotation of the spindle will shear out a section of a ring interposed in the notched perimeter of the blade. The tool is further provided with removable trays to catch sheared pieces of precious metals. Rotation of the spindle is accomplished through a conventional crank handle.
摘要翻译：切割工具设置有多个具有预定厚度的圆形切割刀片，其具有由贵金属制成的环的剪切部分。每个叶片形成有切口周边以提供一对刀片切割刃。刀片安装在主轴上以与其一起旋转，而主轴可旋转地安装在多个切割块中，该多个切割块以与上述刀片交替布置的方式固定到基座。切割块限定切割边缘，使得主轴的旋转导致由切口周边形成的叶片切割边缘与两个相邻切割块的切割边缘同时剪切关系。主轴的进一步旋转将剪切插入在叶片的切口周边中的环的一部分。该工具还提供有可拆卸的托盘，以捕获剪切的贵金属件。主轴的旋转通过传统的曲柄手柄实现。

5. 发明授权

US07269806B2 Decoupling capacitance analysis method 失效
标题翻译：去耦电容分析方法
公开(公告)号：US07269806B2
公开(公告)日：2007-09-11
申请号：US11408228
申请日：2006-04-20
申请人： Christopher J. Berry , Howard H. Smith , Richard P. Underwood , Alan P. Wagstaff
发明人： Christopher J. Berry , Howard H. Smith , Richard P. Underwood , Alan P. Wagstaff
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： This method for decoupling capacitance analysis improves upon existing techniques to attempt to give a more accurate representation of the power supply fluctuations on a chip while keeping runtime comparable. This method employs the following techniques; a) a method for descending through hierarchy and dividing the design into a variable sized grid; b) an algorithm to determine which grid locations of a design don't have enough decoupling capacitors for all of the devices in that grid location; c) an algorithm to determine which grid locations are subject to harmful neighboring effects; and d) a method to display the results of the calculations in a graphical manor to allow easy identification of problem areas.
摘要翻译：用于去耦电容分析的这种方法改进了现有技术，以试图给出对芯片上的电源波动的更准确的表示，同时保持运行时可比性。该方法采用以下技术; a）通过层级降级并将设计划分为可变尺寸网格的方法; b）确定设计的哪些网格位置对于该网格位置中的所有设备没有足够的去耦电容器的算法; c）确定哪些网格位置受到有害的相邻影响的算法; 以及d）以图形方式显示计算结果的方法，以便容易地识别问题区域。

6. 发明授权

US07086026B2 Decoupling capacitance analysis method 失效
标题翻译：去耦电容分析方法
公开(公告)号：US07086026B2
公开(公告)日：2006-08-01
申请号：US10436393
申请日：2003-05-12
申请人： Christopher J. Berry , Howard H. Smith , Richard P. Underwood , Alan P. Wagstaff
发明人： Christopher J. Berry , Howard H. Smith , Richard P. Underwood , Alan P. Wagstaff
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： This method for decoupling capacitance analysis improves upon existing techniques to attempt to give a more accurate representation of the power supply fluctuations on a chip while keeping runtime comparable. This method employs the following techniques: 1. A method for descending through hierarchy and dividing the design into a variable sized grid. 2. An algorithm to determine which grid locations of a design don't have enough decoupling capacitors for all of the devices in that grid location. 3. An algorithm to determine which grid locations are subject to harmful neighboring effects. 4. A method to display the results of the calculations in a graphical manor to allow easy identification of problem areas.
摘要翻译：用于去耦电容分析的这种方法改进了现有技术，以试图给出对芯片上的电源波动的更准确的表示，同时保持运行时可比性。该方法采用以下技术：1.一种通过层级降级并将设计划分为可变尺寸网格的方法。 2.一种用于确定设计的哪些网格位置对于该网格位置中的所有设备没有足够的去耦电容的算法。 3.确定哪些网格位置受到有害的相邻影响的算法。 4.以图形方式显示计算结果的方法，以便轻松识别问题区域。

7. 发明授权

US06415428B1 Minimal length method for positioning unit pins in a hierarchically designed VLSI chip 失效
标题翻译：用于在分层设计的VLSI芯片中定位单元引脚的最小长度方法
公开(公告)号：US06415428B1
公开(公告)日：2002-07-02
申请号：US09422287
申请日：1999-10-21
申请人： Peter J. Camporese , Allan H. Dansky , Howard H. Smith
发明人： Peter J. Camporese , Allan H. Dansky , Howard H. Smith
IPC分类号： G06F1750
CPC分类号： G06F17/5072
摘要： A method for identifying and positioning sub-optimally positioned unit pins in a hierarchically designed VSLI chip without modifying unit placement, comprising: generating a flat data file, generating a first pin log using the flat data file including data for unit pins and for macro pins of a net, generating a second pin log using the flat data file including data for macro pins of the net, determining a minimal net length using the first pin log and determining a minimum net length using the second pin log, calculating the difference between the minimal net length determined using the first ping log and the minimal net length determmed using the second pin log, identifying sub-optimally positioned unit pins by comparing the calculated difference to a threshold, and repositioning the identified sub-optimally positioned unit pins.
摘要翻译：一种用于在不改变单元布置的情况下，将次优定位单元引脚识别和定位在分层设计的VSLI芯片中的方法，包括：生成平坦数据文件，使用包括用于单元引脚和宏引脚的数据的平面数据文件生成第一引脚日志使用包括网的宏引脚的数据的平坦数据文件生成第二引脚对数，使用第一引脚对数确定最小净长度，并使用第二引脚对数确定最小净长度，计算第使用第一引脚对数确定的最小净长度和使用第二引脚对数确定的最小净长度，通过将计算出的差异与阈值进行比较来重新定位所识别的次优定位单元引脚，从而识别次优定位单元引脚。

8. 外观设计

USD893625S1 Ink refill cartridge for writing instrument 有权
公开(公告)号：USD893625S1
公开(公告)日：2020-08-18
申请号：US29679284
申请日：2019-02-04
申请人： Howard H. Smith
设计人： Howard H. Smith
摘要： FIG. 1 is a top, left, rear perspective view of an ink refill cartridge for writing instrument showing my new design;
FIG. 2 is a left side elevational view thereof;
FIG. 3 is a right side elevational view thereof;
FIG. 4 is a top plan view thereof;
FIG. 5 is a bottom plan view thereof;
FIG. 6 is a rear elevational view thereof;
FIG. 7 is a front elevational view thereof; and,
FIG. 8 is a bottom, left, rear perspective view of thereof.

9. 发明授权

US07346877B2 Decoupling capacitance analysis method 有权
标题翻译：去耦电容分析方法
公开(公告)号：US07346877B2
公开(公告)日：2008-03-18
申请号：US11408217
申请日：2006-04-20
申请人： Christopher J. Berry , Howard H. Smith , Richard P. Underwood , Alan P. Wagstaff
发明人： Christopher J. Berry , Howard H. Smith , Richard P. Underwood , Alan P. Wagstaff
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： This method for decoupling capacitance analysis improves upon existing techniques to attempt to give a more accurate representation of the power supply fluctuations on a chip while keeping runtime comparable. This method employs the following techniques; a) a method for descending through hierarchy and dividing the design into a variable sized grid; b) an algorithm to determine which grid locations of a design don't have enough decoupling capacitors for all of the devices in that grid location; c) an algorithm to determine which grid locations are subject to harmful neighboring effects; and d) a method to display the results of the calculations in a graphical manor to allow easy identification of problem areas.
摘要翻译：用于去耦电容分析的这种方法改进了现有技术，以试图给出对芯片上的电源波动的更准确的表示，同时保持运行时可比性。该方法采用以下技术; a）通过层级降级并将设计划分为可变尺寸网格的方法; b）确定设计的哪些网格位置对于该网格位置中的所有设备没有足够的去耦电容器的算法; c）确定哪些网格位置受到有害的相邻影响的算法; 以及d）以图形方式显示计算结果的方法，以便容易地识别问题区域。

10. 发明授权

US07319946B2 Method for on-chip signal integrity and noise verification using frequency dependent RLC extraction and modeling techniques 有权
标题翻译：使用频率相关RLC提取和建模技术的片上信号完整性和噪声验证方法
公开(公告)号：US07319946B2
公开(公告)日：2008-01-15
申请号：US10274861
申请日：2002-10-21
申请人： Michael A. Bowen , Alina Deutsch , Gerard V. Kopcsay , Byron L. Krauter , Barry J. Rubin , Howard H. Smith , David J. Widiger
发明人： Michael A. Bowen , Alina Deutsch , Gerard V. Kopcsay , Byron L. Krauter , Barry J. Rubin , Howard H. Smith , David J. Widiger
IPC分类号： G06F17/50 , G06G7/62 , G06G7/48
CPC分类号： G06F17/5036
摘要： New Frequency dependent RLC extraction and modeling for on chip integrity and noise verification employs: A) 2D scan line algorithm for the collection of adjacent signal and power conductor coordinates; B) In core pair-wise frequency Dependent RL extraction; C) In core equivalent circuit synthesis; D) caching and partitioning RL extraction techniques for run time efficiency; and E) Techniques for synthesizing stable circuits to represent frequency dependent RL circuits for non-mono tonic R12.
摘要翻译：新的频率相关RLC提取和片上完整性和噪声验证的建模采用：A）用于收集相邻信号和电源导体坐标的2D扫描线算法; B）在核心配对频率从属RL提取中; C）在核心等效电路合成中; D）缓存和分区RL提取技术，用于运行时效率; 和E）用于合成稳定电路以表示用于非单音增益R 12的频率相关RL电路的技术。

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