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1. 发明授权

US4551634A Multiplexing input circuit 失效
标题翻译：复用输入电路
公开(公告)号：US4551634A
公开(公告)日：1985-11-05
申请号：US480581
申请日：1983-03-30
申请人： Hitoshi Takahashi , Satoru Yamaguchi , Hideo Nunokawa
发明人： Hitoshi Takahashi , Satoru Yamaguchi , Hideo Nunokawa
IPC分类号： G06F3/05 , H03K17/693 , H03K17/60 , H04J3/02
CPC分类号： H03K17/693
摘要： An input circuit having a plurality of channels, each channel includes a conductor line, first and second transistors inserted in series into the conductor line and a third transistor.When a channel is not selected, the first and second transistors are turned off and the third transistor is turned on to clamp the conductor line at a predetermined constant voltage. When a channel is selected, the third transistor is turned off and first and second transistors are turned on to transfer the corresponding information input therethrough.
摘要翻译：一种具有多个通道的输入电路，每个通道包括导体线，串联插入导体线的第一和第二晶体管以及第三晶体管。当未选择通道时，第一和第二晶体管截止，第三晶体管导通，将导体线夹在预定的恒定电压。当选择通道时，第三晶体管截止，第一和第二晶体管导通，以传输从其输入的相应信息。

2. 发明授权

US4550264A Boosting circuit 失效
标题翻译：升压电路
公开(公告)号：US4550264A
公开(公告)日：1985-10-29
申请号：US480585
申请日：1983-03-30
申请人： Hitoshi Takahaski , Satoru Yamaguchi , Hideo Nunokawa
发明人： Hitoshi Takahaski , Satoru Yamaguchi , Hideo Nunokawa
IPC分类号： H03K5/02 , H03K17/0412 , H03K17/06 , H03K17/687 , H03K17/693 , H03K19/094 , H03K19/096 , H03K3/57
CPC分类号： H03K17/693 , H03K17/04123 , H03K17/06 , H03K19/096
摘要： A boosting circuit includes a plurality of variable capacitors with controllable capacitance values in accordance with the voltage level at first and second terminals of each of the variable capicitors A plurality of first buffer circuits is located at the first terminal side, each acting to increase the voltage level at the corresponding first terminal to a first level. A single second buffer circuit located at the second terminal side cooperating commonly with the variable capacitors, to increase the voltage level at each second terminal. The first level is thus boosted to a second level which results in an output of the circuit concerned. Each variable capacitor is fabricated by a MOS transistor capacitor.
摘要翻译：升压电路包括具有可变电容值的多个可变电容器，其根据每个可变标识符的第一和第二端子处的电压电平。多个第一缓冲电路位于第一端子侧，每个起作用以增加电压在相应的第一终端处的电平达到第一级。位于第二端子侧的单个第二缓冲电路与可变电容器共同配合，以增加每个第二端子处的电压电平。因此，第一电平被提升到第二电平，这导致有关电路的输出。每个可变电容器由MOS晶体管电容器制成。

3. 发明授权

US07554305B2 Linear regulator with discharging gate driver 有权
标题翻译：带放电栅极驱动器的线性稳压器
公开(公告)号：US07554305B2
公开(公告)日：2009-06-30
申请号：US10985905
申请日：2004-11-12
申请人： Hideo Nunokawa , Tatsuo Kato , Miki Suzuki , Tomonari Morishita
发明人： Hideo Nunokawa , Tatsuo Kato , Miki Suzuki , Tomonari Morishita
IPC分类号： G05F1/56
CPC分类号： G05F1/575
摘要： Even when, for example, electric charge is injected into the output transistor due to external factor such as a noise from the outside, to prevent the step-down voltage from rising, the step-down circuit is comprised of an N channel type output transistor which controls the voltage at the control end, a booster, which is connected to the control end of the output transistor and raises the voltage at the control end and a discharge circuit, which discharges the electric charge at the control end of the output transistor so that the power supply voltage inputted from the input end is stepped down to a desired step-down voltage and outputted from the output end.
摘要翻译：即使例如，由于诸如来自外部的噪声等外部因素将电荷注入到输出晶体管中，为了防止降压电压上升，降压电路由N沟道型输出晶体管其控制控制端的电压，升压器，其连接到输出晶体管的控制端并提高控制端的电压，以及放电电路，其在输出晶体管的控制端放电电从输入端输入的电源电压被降低到期望的降压电压并从输出端输出。

4. 发明授权

US06867723B1 AD converter with reduced current consumption 有权
标题翻译： AD转换器，降低电流消耗
公开(公告)号：US06867723B1
公开(公告)日：2005-03-15
申请号：US10774525
申请日：2004-02-10
申请人： Suguru Tachibana , Tatsuo Kato , Hideo Nunokawa
发明人： Suguru Tachibana , Tatsuo Kato , Hideo Nunokawa
IPC分类号： H03M1/38 , H03K5/08 , H03M1/00 , H03M1/46 , H03M1/12
CPC分类号： H03M1/002 , H03M1/468
摘要： An AD converter includes a sample-&-hold circuit which samples and holds an input analog potential in a first period, and generates a signal indicative of a magnitude relation between the held input analog potential and a reference potential in a second period, a plurality of amplifiers connected in series which amplify an output of the sample-&-hold circuit, and a control circuit which controls operating timing of the amplifiers so as to make at least one of the amplifiers start operating in a middle of the first period.
摘要翻译： AD转换器包括采样保持电路，其在第一周期中采样并保持输入模拟电位，并且产生指示在第二周期中保持的输入模拟电位与参考电位之间的大小关系的信号，多个放大器连接的放大器，其放大采样保持电路的输出;以及控制电路，其控制放大器的工作时序，以使至少一个放大器在第一周期的中间开始工作。

5. 发明授权

US07429900B2 Oscillator and semiconductor device 有权
标题翻译：振荡器和半导体器件
公开(公告)号：US07429900B2
公开(公告)日：2008-09-30
申请号：US11238954
申请日：2005-09-30
申请人： Hideo Nunokawa , Fukuji Kihara , Tomonari Morishita , Shunichi Ko , Hiroshi Ookawa
发明人： Hideo Nunokawa , Fukuji Kihara , Tomonari Morishita , Shunichi Ko , Hiroshi Ookawa
IPC分类号： H03B5/32
CPC分类号： H03B5/32 , H03K3/0307
摘要： An object is not only to contribute to reduction in current consumption but also to advance actuation of a system required in a camera, an on-vehicle electric component, etc. by shortening a waiting time for stabilization of oscillation. An oscillator having an inverting amplifier inverting and amplifying an input signal and outputting it, a resonator connected to between an input and an output terminals of the inverting amplifier, a feedback resistance connected in parallel to the resonator, and an output circuit outputting a first clock signal based on a signal of an on-load parallel resonance frequency or a parallel resonance frequency oscillated by the resonator, the inverting amplifier and the feedback resistance to a function block is provided.
摘要翻译：目的不仅在于减少电流消耗，而且通过缩短振荡的稳定等待时间来提高照相机，车载电气部件等所需的系统的动作。一种具有反相放大器的反相放大器，其反相并放大输入信号并输出;振荡器，连接到反相放大器的输入端和输出端之间，与谐振器并联连接的反馈电阻，以及输出电路，输出第一时钟基于谐振器振荡的负载并联谐振频率或并联谐振频率的信号，提供反相放大器和对功能块的反馈电阻的信号。

6. 发明授权

US07218145B2 Level conversion circuit 失效
标题翻译：电平转换电路
公开(公告)号：US07218145B2
公开(公告)日：2007-05-15
申请号：US11166255
申请日：2005-06-27
申请人： Hideo Nunokawa
发明人： Hideo Nunokawa
IPC分类号： H03K19/094 , H03K19/0175 , H03K19/20 , H03K19/086
CPC分类号： H03K3/35613
摘要： An input circuit (a first transistor pair) that receives complementary input signals is connected to a latch circuit (a second transistor pair) that converts the amplitude of an input signal into second amplitude higher than first amplitude. A current mirror circuit (a third transistor pair) is disposed between the latch circuit and a high-level power supply line. The current mirror circuit makes a source voltage of the second transistors being turned on lower than the source voltage of the second transistors being turned off. The second transistors being turned on are likely to be turned off although the on-current of corresponding first transistors is low. To the contrary, the second transistors being turned off are likely to be turned on. Accordingly, even when a voltage of a high logic level of an input signal is low, the level conversion circuit can surely operate without malfunction.
摘要翻译：接收互补输入信号的输入电路（第一晶体管对）连接到将输入信号的幅度转换为高于第一幅度的第二幅度的锁存电路（第二晶体管对）。电流镜电路（第三晶体管对）设置在锁存电路和高电平电源线之间。电流镜电路使第二晶体管的源极电压接通低于第二晶体管的源极电压截止。导通的第二晶体管可能被关断，尽管对应的第一晶体管的导通电流低。相反，关闭的第二晶体管很可能导通。因此，即使当输入信号的高逻辑电平的电压低时，电平转换电路也可以无故障地运行。

7. 发明申请

US20060012354A1 Step-down circuit 有权
标题翻译：降压电路
公开(公告)号：US20060012354A1
公开(公告)日：2006-01-19
申请号：US10985905
申请日：2004-11-12
申请人： Hideo Nunokawa , Tatsuo Kato , Miki Suzuki , Tomonari Morishita
发明人： Hideo Nunokawa , Tatsuo Kato , Miki Suzuki , Tomonari Morishita
IPC分类号： G05F1/56
CPC分类号： G05F1/575
摘要： Even when, for example, electric charge is injected into the output transistor due to external factor such as a noise from the outside, to prevent the step-down voltage from rising, the step-down circuit is comprised of an N channel type output transistor which controls the voltage at the control end, a booster, which is connected to the control end of the output transistor and raises the voltage at the control end and a discharge circuit, which discharges the electric charge at the control end of the output transistor so that the power supply voltage inputted from the input end is stepped down to a desired step-down voltage and outputted from the output end.
摘要翻译：即使例如，由于诸如来自外部的噪声等外部因素将电荷注入到输出晶体管中，为了防止降压电压上升，降压电路由N沟道型输出晶体管其控制控制端的电压，升压器，其连接到输出晶体管的控制端并提高控制端的电压，以及放电电路，其在输出晶体管的控制端放电电从输入端输入的电源电压被降低到期望的降压电压并从输出端输出。

8. 发明申请

US20060071725A1 Oscillator and semiconductor device 有权
标题翻译：振荡器和半导体器件
公开(公告)号：US20060071725A1
公开(公告)日：2006-04-06
申请号：US11238954
申请日：2005-09-30
申请人： Hideo Nunokawa , Fukuji Kihara , Tomonari Morishita , Shunichi Ko , Hiroshi Ookawa
发明人： Hideo Nunokawa , Fukuji Kihara , Tomonari Morishita , Shunichi Ko , Hiroshi Ookawa
IPC分类号： H03B1/00
CPC分类号： H03B5/32 , H03K3/0307
摘要： An object is not only to contribute to reduction in current consumption but also to advance actuation of a system required in a camera, an on-vehicle electric component, etc. by shortening a waiting time for stabilization of oscillation. An oscillator having an inverting amplifier inverting and amplifying an input signal and outputting it, a resonator connected to between an input and an output terminals of the inverting amplifier, a feedback resistance connected in parallel to the resonator, and an output circuit outputting a first clock signal based on a signal of an on-load parallel resonance frequency or a parallel resonance frequency oscillated by the resonator, the inverting amplifier and the feedback resistance to a function block is provided.
摘要翻译：目的不仅在于减少电流消耗，而且通过缩短振荡的稳定等待时间来提高照相机，车载电气部件等所需的系统的动作。一种具有反相放大器的反相放大器，其反相并放大输入信号并输出;振荡器，连接到反相放大器的输入端和输出端之间，与谐振器并联连接的反馈电阻，以及输出电路，输出第一时钟基于谐振器振荡的负载并联谐振频率或并联谐振频率的信号，提供反相放大器和对功能块的反馈电阻的信号。

9. 发明申请

US20050280084A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20050280084A1
公开(公告)日：2005-12-22
申请号：US10965856
申请日：2004-10-18
申请人： Tomonari Morishita , Hideo Nunokawa , Suguru Tachibana , Fukuji Kihara
发明人： Tomonari Morishita , Hideo Nunokawa , Suguru Tachibana , Fukuji Kihara
IPC分类号： H01L27/08 , H01L29/76
CPC分类号： H01L27/0811
摘要： A semiconductor device in which a dielectric breakdown of a gate oxide in a MOS capacitor can be prevented and in which a circuit area can be reduced. The semiconductor device comprises an NMOS transistor a gate of which is connected to a terminal VDD on a high potential side and a PMOS transistor a gate of which is connected to a terminal GND on a low potential side, source/drain (S/D) regions of the NMOS transistor and source/drain (S/D) regions of the PMOS transistor being electrically connected.
摘要翻译：可以防止MOS电容器中的栅极氧化物的电介质击穿并且可以减小电路面积的半导体器件。半导体器件包括NMOS晶体管，栅极连接到高电位侧的端子VDD和PMOS晶体管，其栅极连接到低电位侧的端子GND，源极/漏极（S / D） NMOS晶体管的区域和PMOS晶体管的源极/漏极（S / D）区域电连接。

10. 发明授权

US06791127B2 Semiconductor device having a condenser chip for reducing a noise 失效
标题翻译：具有用于降低噪声的电容器芯片的半导体器件
公开(公告)号：US06791127B2
公开(公告)日：2004-09-14
申请号：US10073316
申请日：2002-02-13
申请人： Hideo Nunokawa
发明人： Hideo Nunokawa
IPC分类号： H01L2710
CPC分类号： H01L24/06 , H01L23/50 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/05556 , H01L2224/05599 , H01L2224/16 , H01L2224/45144 , H01L2224/48011 , H01L2224/48091 , H01L2224/48227 , H01L2224/48463 , H01L2224/48599 , H01L2224/49113 , H01L2224/49171 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01079 , H01L2924/014 , H01L2924/07802 , H01L2924/10162 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19104 , H01L2924/30105 , H01L2924/30107 , H01L2924/00
摘要： A semiconductor chip has a circuit block, a power supply line and a ground line. A condenser chip in which a noise reduction condenser connected to the circuit block is stacked on the semiconductor chip. Because the condenser chip is stacked on the semiconductor chip, it is not necessary to provide a noise reduction condenser on the semiconductor chip and also not to provide a noise reduction condenser on a substrate on which the semiconductor chip is mounted.
摘要翻译：半导体芯片具有电路块，电源线和接地线。连接到电路块的降噪电容器堆叠在半导体芯片上的电容器芯片。由于在半导体芯片上层叠有电容器芯片，所以不需要在半导体芯片上设置降噪电容器，也不需要在安装有半导体芯片的基板上设置降噪电容器。

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