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1. 发明专利

JP2003330907A Microcomputer system 审中-公开
标题翻译：微型计算机系统
公开(公告)号：JP2003330907A
公开(公告)日：2003-11-21
申请号：JP2003113567
申请日：2003-04-18
申请人： Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： MASUMURA SHIGEKI , NAKAMURA HIDEO , NOGUCHI YOSHIKI , KAWASAKI SHUNPEI , FUKADA KAORU , AKAO YASUSHI
IPC分类号： G06F15/78 , G06F13/38
摘要： PROBLEM TO BE SOLVED: To provide a bus operating method capable of easily changing a bus interface specification by increasing effective operation speeds of a bus, and a memory and peripheral function units connected to the bus, in a microcomputer system. SOLUTION: An access operation through buses 113 and 114 with bus masters 101 and 102 connected is executed in a pipeline manner, and control of the pipeline execution is carried out by an exclusive bus controller 111. An access delaying the pipeline operation is executed by buses 123 and 124 of a lower tier connected through a buffer means 112, and by a bus controller 121 exclusively used for the lower tier. Therefore, the bus band for access is improved, and bus interfaces having various specifications, and buses allowing parallel execution can easily be structured. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种总线操作方法，其能够通过在微计算机系统中增加总线的有效操作速度以及连接到总线的存储器和外围功能单元来容易地改变总线接口规范。解决方案：以流水线方式执行通过连接有总线主机101和102的总线113和114的访问操作，并且由专用总线控制器111执行流水线执行的控制。延迟流水线操作的访问是由通过缓冲装置112连接的下层的总线123和124执行，并且由专用于下层的总线控制器121执行。因此，改善了用于访问的总线频带，并且可以容易地构造具有各种规格的总线接口和允许并行执行的总线。版权所有（C）2004，JPO

2. 发明专利

DE69232232T2 未知
公开(公告)号：DE69232232T2
公开(公告)日：2002-08-29
申请号：DE69232232
申请日：1992-06-22
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KAWASAKI SHUMPEI , SAKAKIBARA EIJI , FUKADA KAORU , YAMAZAKI TAKANAGA , AKAO YASUSHI , BABA SHIRO , KIHARA TOSHIMASA , KURAKAZU KEIICHI , TSUKAMOTO TAKASHI , MASUMURA SHIGEKI , TAWARA YASUHIRO , KASHIWAGI YUGO , FUJITA SHUYA , ISHIDA KATSUHIKO , SAWA NORIKO , ASANO YOICHI , CHAKI HIDEAKI , SUGAWARA TADAHIKO , KAINAGA MASAHIRO , NOGUCHI KOUKI , WATABE MITSURU
IPC分类号： G06F9/28 , G06F7/483 , G06F7/52 , G06F7/527 , G06F7/535 , G06F7/537 , G06F9/30 , G06F9/302 , G06F9/305 , G06F9/318 , G06F9/32 , G06F9/38
摘要： A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting an instruction format of a fixed length of 2 n bits which is smaller than the length of the maximum data word fed to instruction execution means. The control of the coded division is executed by noting the code bits.

3. 发明专利

HK1011101A1 MICROCOMPUTER 未知
公开(公告)号：HK1011101A1
公开(公告)日：1999-07-02
申请号：HK98111668
申请日：1998-10-30
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： AKAO YASUSHI , KAWASAKI SHUMPEI , SAKAKIBARA EIJI , FUKADA KAORU , YAMAZAKI TAKANAGA , BABA SHIRO , KIHARA TOSHIMASA , KURAKAZU KEIICHI , TSUKAMOTO TAKASHI , MASUMURA SHIGEKI , TAWARA YASUHIRO , KASHIWAGI YUGO , FUJITA SHUYA , ISHIDA KATSUHIKO , SAWA NORIKO , ASANO YOICHI , CHAKI HIDEAKI , SUGAWARA TADAHIKO , KAINAGA MASAHIRO , NOGUCHI KOUKI , WATABE MITSURU
IPC分类号： G06F9/28 , G06F7/483 , G06F7/52 , G06F7/527 , G06F7/535 , G06F7/537 , G06F9/30 , G06F9/302 , G06F9/305 , G06F9/318 , G06F9/32 , G06F9/38 , G06F
摘要： A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting an instruction format of a fixed length of 2 n bits which is smaller than the length of the maximum data word fed to instruction execution means. The control of the coded division is executed by noting the code bits.

4. 发明专利

DE69233361D1 未知
公开(公告)号：DE69233361D1
公开(公告)日：2004-07-08
申请号：DE69233361
申请日：1992-06-22
申请人： HITACHI LTD , HITACHI ULSI SYSTEMS CO
发明人： KAWASAKI SHUMPEI , SAKAKIBARA EIJI , FUKADA KAORU , YAMAZAKI TAKANAGA , AKAO YASUSHI , BABA SHIRO , KIHARA TOSHIMASA , KURAKAZU KEIICHI , TSUKAMOTO TAKASHI , MASUMURA SHIGEKI , TAWARA YASUHIRO , KASHIWAGI YUGO , FUJITA SHUYA , ISHIDA KATSUHIKO , SAWA NORIKO , ASANO YOICHI , CHAKI HIDEAKI , SUGAWARA TADAHIKO , KAINAGA MASAHIRO , NOGUCHI KOUKI , WATABE
IPC分类号： G06F9/28 , G06F7/483 , G06F7/52 , G06F7/527 , G06F7/535 , G06F7/537 , G06F9/30 , G06F9/302 , G06F9/305 , G06F9/318 , G06F9/32 , G06F9/38 , G06F15/78
摘要： A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting an instruction format of a fixed length of 2 n bits which is smaller than the length of the maximum data word fed to instruction execution means. The control of the coded division is executed by noting the code bits.

5. 发明专利

DE69232232D1 未知
公开(公告)号：DE69232232D1
公开(公告)日：2002-01-10
申请号：DE69232232
申请日：1992-06-22
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KAWASAKI SHUMPEI , SAKAKIBARA EIJI , FUKADA KAORU , YAMAZAKI TAKANAGA , AKAO YASUSHI , BABA SHIRO , KIHARA TOSHIMASA , KURAKAZU KEIICHI , TSUKAMOTO TAKASHI , MASUMURA SHIGEKI , TAWARA YASUHIRO , KASHIWAGI YUGO , FUJITA SHUYA , ISHIDA KATSUHIKO , SAWA NORIKO , ASANO YOICHI , CHAKI HIDEAKI , SUGAWARA TADAHIKO , KAINAGA MASAHIRO , NOGUCHI KOUKI , WATABE MITSURU
IPC分类号： G06F9/28 , G06F7/483 , G06F7/52 , G06F7/527 , G06F7/535 , G06F7/537 , G06F9/30 , G06F9/302 , G06F9/305 , G06F9/318 , G06F9/32 , G06F9/38
摘要： A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting an instruction format of a fixed length of 2 n bits which is smaller than the length of the maximum data word fed to instruction execution means. The control of the coded division is executed by noting the code bits.

6. 发明专利

DE69324651T2 未知
公开(公告)号：DE69324651T2
公开(公告)日：1999-12-30
申请号：DE69324651
申请日：1993-10-25
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： KAWASAKI SHUMPEI , FUKADA KAORU , WATABE MITSURU , NOGUCHI KOUKI , MATSUBARA KIYOSHI , MOCHIZUKI ISAMU , SUZUKAWA KAZUFUMI , MASUMURA SHIGEKI , AKAO YASUSHI , SAKAKIBARA EIJI
IPC分类号： G06F12/00 , G06F12/06 , G06F13/42 , G06F15/78
摘要： A microcomputer that is easy to use and connected direct to such memories as dynamic and static RAM's and to other peripheral circuits. The microcomputer has strobe signal output terminals CASH*, CASL* and RAS* for direct connection to a dynamic RAM, and chip select signal output terminals CS0* through CS6* for outputting a chip select signal in parallel with the output from the strobe signal output terminals. The microcomputer further includes address output terminals for outputting a non-multiplexed or multiplexed address signal as needed, and data I/O terminals for selectively outputting the address signal to comply with a multiple-bus interface scheme.

7. 发明专利

DE69233361T2 未知
公开(公告)号：DE69233361T2
公开(公告)日：2005-06-02
申请号：DE69233361
申请日：1992-06-22
申请人： HITACHI LTD , HITACHI ULSI SYSTEMS CO
发明人： KAWASAKI SHUMPEI , SAKAKIBARA EIJI , FUKADA KAORU , YAMAZAKI TAKANAGA , AKAO YASUSHI , BABA SHIRO , KIHARA TOSHIMASA , KURAKAZU KEIICHI , TSUKAMOTO TAKASHI , MASUMURA SHIGEKI , TAWARA YASUHIRO , KASHIWAGI YUGO , FUJITA SHUYA , ISHIDA KATSUHIKO , SAWA NORIKO , ASANO YOICHI , CHAKI HIDEAKI , SUGAWARA TADAHIKO , KAINAGA MASAHIRO , NOGUCHI KOUKI , WATABE
IPC分类号： G06F9/28 , G06F7/483 , G06F7/52 , G06F7/527 , G06F7/535 , G06F7/537 , G06F9/30 , G06F9/302 , G06F9/305 , G06F9/318 , G06F9/32 , G06F9/38 , G06F15/78
摘要： A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting an instruction format of a fixed length of 2 n bits which is smaller than the length of the maximum data word fed to instruction execution means. The control of the coded division is executed by noting the code bits.

8. 发明专利

DE69233412T2 未知
公开(公告)号：DE69233412T2
公开(公告)日：2005-02-17
申请号：DE69233412
申请日：1992-06-22
申请人： HITACHI LTD , HITACHI ULSI SYSTEMS CO
发明人： FUKADA KAORU , YAMAZAKI TAKANAGA , AKAO YASUSHI , BABA SHIRO , KIHARA TOSHIMASA , KURAKAZU KEIICHI , TAWARA YASUHIRO , KASHIWAGI YUGO , FUJITA SHUYA , ISHIDA KATSUHIKO , CHAKI HIDEAKI , SUGAWARA TADAHIKO , KAINAGA MASAHIRO , NOGUCHI KOKI , KAWASAKI SHUMPEI , SAKAKIBARA EIJI , TSUKAMOTO TAKASHI , MASUMURA SHIGEKI , SAWA NORIKO , ASANO YOICHI , WATABE
IPC分类号： G06F9/28 , G06F7/483 , G06F7/52 , G06F7/527 , G06F7/535 , G06F7/537 , G06F9/30 , G06F9/302 , G06F9/305 , G06F9/318 , G06F9/32 , G06F9/38 , G06F9/34
摘要： A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting an instruction format of a fixed length of 2 n bits which is smaller than the length of the maximum data word fed to instruction execution means. The control of the coded division is executed by noting the code bits.

9. 发明专利

DE69233412D1 未知
公开(公告)号：DE69233412D1
公开(公告)日：2004-10-21
申请号：DE69233412
申请日：1992-06-22
申请人： HITACHI LTD , HITACHI ULSI SYSTEMS CO
发明人： FUKADA KAORU , YAMAZAKI TAKANAGA , AKAO YASUSHI , BABA SHIRO , KIHARA TOSHIMASA , KURAKAZU KEIICHI , TAWARA YASUHIRO , KASHIWAGI YUGO , FUJITA SHUYA , ISHIDA KATSUHIKO , CHAKI HIDEAKI , SUGAWARA TADAHIKO , KAINAGA MASAHIRO , NOGUCHI KOKI , KAWASAKI SHUMPEI , SAKAKIBARA EIJI , TSUKAMOTO TAKASHI , MASUMURA SHIGEKI , SAWA NORIKO , ASANO YOICHI , WATABE
IPC分类号： G06F9/28 , G06F7/483 , G06F7/52 , G06F7/527 , G06F7/535 , G06F7/537 , G06F9/30 , G06F9/302 , G06F9/305 , G06F9/318 , G06F9/32 , G06F9/38 , G06F9/34
摘要： A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting an instruction format of a fixed length of 2 n bits which is smaller than the length of the maximum data word fed to instruction execution means. The control of the coded division is executed by noting the code bits.

10. 发明专利

DE69032342T2 未知
公开(公告)号：DE69032342T2
公开(公告)日：1999-02-25
申请号：DE69032342
申请日：1990-12-07
申请人： HITACHI LTD , HITACHI ULSI ENG CORP
发明人： AKAO YASUSHI , BABA SHIRO , MIWA YOSHIYUKI , SAWASE TERUMI , SATO YUJI , MASUMURA SHIGEKI
IPC分类号： G06F13/12 , G06F15/78 , G06F13/00
摘要： A single chip microprocessor 1 comprises a CPU 2 and a sub-processor 5 for implementing peripheral functions of the microprocessor 1 by software. The sub-processor 5 includes electrically writable internal storage devices called a microprogram memory unit 13 and a sequence control memory unit 62 for storing the software. Peripheral functions to be implemented by the sub-processor 5 can be defined or modified by writing software into the memory units 13 and 62. Accordingly, the time it takes to define or modify the peripheral functions is the same as the time it takes to program the memory units 13 and 62. The sub-processor 5 also includes an execution unit 16 for executing a plurality of tasks and an address control circuit 14 for providing addresses to the microprogram memory unit 13 in addition to the microprogram memory unit 13 for providing microinstructions to the execution unit 16. The sequence control memory unit 62 is part of the address control circuit 14 which also includes a plurality of address registers MAR0 to MAR11. The sequence control memory unit 62 is used for storing information on what order the multiple address registers MAR0 to MAR11 are to be selected in sequentially. One of the address registers MAR0 to MAR11 is selected at every read cycle performed on the sequence control memory unit 62. A microaddress stored in the selected one of the address registers MAR0 to MAR11 is then supplied to the microprogram memory unit 13. Task null information can also be stored in the sequence control memory unit 62. The selection of one of the address registers MAR0 to MAR11 at every read cycle allows the sub-processor 5 to operate on an event driven basis.

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