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1. 发明专利

DE69032342T2 未知
公开(公告)号：DE69032342T2
公开(公告)日：1999-02-25
申请号：DE69032342
申请日：1990-12-07
申请人： HITACHI LTD , HITACHI ULSI ENG CORP
发明人： AKAO YASUSHI , BABA SHIRO , MIWA YOSHIYUKI , SAWASE TERUMI , SATO YUJI , MASUMURA SHIGEKI
IPC分类号： G06F13/12 , G06F15/78 , G06F13/00
摘要： A single chip microprocessor 1 comprises a CPU 2 and a sub-processor 5 for implementing peripheral functions of the microprocessor 1 by software. The sub-processor 5 includes electrically writable internal storage devices called a microprogram memory unit 13 and a sequence control memory unit 62 for storing the software. Peripheral functions to be implemented by the sub-processor 5 can be defined or modified by writing software into the memory units 13 and 62. Accordingly, the time it takes to define or modify the peripheral functions is the same as the time it takes to program the memory units 13 and 62. The sub-processor 5 also includes an execution unit 16 for executing a plurality of tasks and an address control circuit 14 for providing addresses to the microprogram memory unit 13 in addition to the microprogram memory unit 13 for providing microinstructions to the execution unit 16. The sequence control memory unit 62 is part of the address control circuit 14 which also includes a plurality of address registers MAR0 to MAR11. The sequence control memory unit 62 is used for storing information on what order the multiple address registers MAR0 to MAR11 are to be selected in sequentially. One of the address registers MAR0 to MAR11 is selected at every read cycle performed on the sequence control memory unit 62. A microaddress stored in the selected one of the address registers MAR0 to MAR11 is then supplied to the microprogram memory unit 13. Task null information can also be stored in the sequence control memory unit 62. The selection of one of the address registers MAR0 to MAR11 at every read cycle allows the sub-processor 5 to operate on an event driven basis.

2. 发明专利

DE69032342D1 未知
公开(公告)号：DE69032342D1
公开(公告)日：1998-07-02
申请号：DE69032342
申请日：1990-12-07
申请人： HITACHI LTD , HITACHI ULSI ENG CORP
发明人： AKAO YASUSHI , BABA SHIRO , MIWA YOSHIYUKI , SAWASE TERUMI , SATO YUJI , MASUMURA SHIGEKI
IPC分类号： G06F13/12 , G06F15/78 , G06F13/00
摘要： A single chip microprocessor 1 comprises a CPU 2 and a sub-processor 5 for implementing peripheral functions of the microprocessor 1 by software. The sub-processor 5 includes electrically writable internal storage devices called a microprogram memory unit 13 and a sequence control memory unit 62 for storing the software. Peripheral functions to be implemented by the sub-processor 5 can be defined or modified by writing software into the memory units 13 and 62. Accordingly, the time it takes to define or modify the peripheral functions is the same as the time it takes to program the memory units 13 and 62. The sub-processor 5 also includes an execution unit 16 for executing a plurality of tasks and an address control circuit 14 for providing addresses to the microprogram memory unit 13 in addition to the microprogram memory unit 13 for providing microinstructions to the execution unit 16. The sequence control memory unit 62 is part of the address control circuit 14 which also includes a plurality of address registers MAR0 to MAR11. The sequence control memory unit 62 is used for storing information on what order the multiple address registers MAR0 to MAR11 are to be selected in sequentially. One of the address registers MAR0 to MAR11 is selected at every read cycle performed on the sequence control memory unit 62. A microaddress stored in the selected one of the address registers MAR0 to MAR11 is then supplied to the microprogram memory unit 13. Task null information can also be stored in the sequence control memory unit 62. The selection of one of the address registers MAR0 to MAR11 at every read cycle allows the sub-processor 5 to operate on an event driven basis.

3. 发明专利

DE68927907T2 未知
公开(公告)号：DE68927907T2
公开(公告)日：1997-10-09
申请号：DE68927907
申请日：1989-09-29
申请人： HITACHI LTD
发明人： SAWASE TERUMI , HAGIWARA YOSHIMUNE , NAKAMURA HIDEO , HATORI HIROYUKI , BABA SHIROU , AKAO YASUSHI
IPC分类号： G06F9/24 , G06F9/38 , G06F11/267 , G06F15/78
摘要： A single chip microcomputer comprises a control circuit (12a, 12b), a processing circuit (13a, 13b) and a plurality of address register - status register pairs. A logical unit formed within the control circuit (12a, 12b) comprises an electrically writable non-volatile semiconductor memory device. Information can be externally written into the non-volatile semiconductor memory included in the logical unit, and the plurality of address register - status register pairs can be arbitrarily selected. As a result, logic function of the logical unit can be arbitrarily established in accordance with externally supplied information. Demanded specifications of various users can be satisfied by the logic function thus arbitrarily formed.

4. 发明专利

DE3581951D1 LSI-MICROCOMPUTER. 未知
公开(公告)号：DE3581951D1
公开(公告)日：1991-04-11
申请号：DE3581951
申请日：1985-03-22
申请人： HITACHI LTD
发明人： NAKAMURA HIDEO , SAWASE TERUMI
IPC分类号： G06F12/00 , G06F12/06 , G06F13/16 , G06F15/17 , G06F15/78 , G06F15/76
摘要： The present invention discloses an integrated circuit having a data bus, an address bus, a processor and a memory each connected to the data bus and the address bus, a first transmitter for transmitting data inputted to a data terminal to the data bus, a second transmitter for transmitting data on the data bus to the data terminal, a third transmitter for transmitting an address inputted to an address terminal to the address bus, and signal generate means for generating signals to set the respective outputs from the first and third transmitters to the high impedance in response to a memory read request supplied from the processor, for generating signals to set the respective outputs from a data output of memory module to transmit data from the memory to the data bus, the first transmitter, and the third transmitter to the high impedance in response to a memory write request, for generating signals to set the respective outputs from a data output of processor module and an address output of processor module to output data and an address from the processor to the data bus and the address bus, respectively to the high impedance in response to a memory read request from an external device, and for generating signals to set the respective outputs from the data output of processor module and the address output of processor module in response to a memory write request from an external device, the integrated circuit further including a fourth transmitter for transmitting an address on the address bus to the address terminal; wherein the signal generate means generates signals to set the outputs from the first and third transmitters to the high impedance in response to an external memory read request supplied from the processor, sets the respective outputs from the data output of memory module, the first transmitter, and the third transmitter to the high impedance in response to an external memory write request supplied from the processor, and responds to the read or write request from the external device in preference to the read or write request from the processor.

5. 发明专利

DE3852251D1 未知
公开(公告)号：DE3852251D1
公开(公告)日：1995-01-12
申请号：DE3852251
申请日：1988-09-08
申请人： HITACHI LTD
发明人： SAWASE TERUMI , NOGUCHI KOUKI , NAKAMURA HIDEO , AKAO YASUSHI , BABA SHIRO , HAGIWARA YOSHIMUNE
IPC分类号： G11C29/00 , G06F7/00 , G06F9/22 , G06F9/24 , G06F15/78 , G11C16/02 , G11C17/00
摘要： A logic circuit (6) built in a single-chip microprocessor is configured of electrically-programmable memory elements, and information is written into the memory elements from outside, whereby a logic circuit having any desired logical functions can be constructed. The writing operation of the memory elements can be executed in a short time, and a user can obtain the single-chip microprocessor having hardware of peculiar prescribed specifications, in a short period.

6. 发明专利

DE2940690A1 未知
公开(公告)号：DE2940690A1
公开(公告)日：1980-04-10
申请号：DE2940690
申请日：1979-10-08
申请人： HITACHI LTD
发明人： TAKAI ATSUSHI , KITA YUZO , HAGIWARA YOSHIMUNE , SAWASE TERUMI , HAGIWARA TAKAAKI
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/26 , G11C7/00
摘要： In a memory array of memory cells each having at least a gate, a substrate, a source and a drain, a writing operation is effected when the substrate and the source and drain are at the same potential and when a potential difference Vp exists between the potential of the substrate and the source and drain and that at the gate. The stored contents are erased when a potential difference Vp exists between the gate and the substrate. The stored condition is prevented from changing when a potential difference Vp exists between the substrate and the gate and when a potential difference Vwd exists between the substrate and the source and drain. When such a memory array is partially erased, cells not to be erased are sequentially driven by applying a voltage Vwd between the source and drain and the substrate of the cell, applying a voltage Vp between the gate and the substrate of the cell, and applying the same potential to the substrate and the gate of the cell.

7. 发明专利

HK1003582A1 Single chip microcomputer 未知
公开(公告)号：HK1003582A1
公开(公告)日：1998-10-30
申请号：HK98102616
申请日：1998-03-27
申请人： HITACHI LTD
发明人： SAWASE TERUMI , HAGIWARA YOSHIMUNE , NAKAMURA HIDEO , HATORI HIROYUKI , BABA SHIROU , AKAO YASUSHI
IPC分类号： G06F9/24 , G06F9/38 , G06F11/267 , G06F15/78 , G06F
摘要： A single chip microcomputer comprises a control circuit (12a, 12b), a processing circuit (13a, 13b) and a plurality of address register - status register pairs. A logical unit formed within the control circuit (12a, 12b) comprises an electrically writable non-volatile semiconductor memory device. Information can be externally written into the non-volatile semiconductor memory included in the logical unit, and the plurality of address register - status register pairs can be arbitrarily selected. As a result, logic function of the logical unit can be arbitrarily established in accordance with externally supplied information. Demanded specifications of various users can be satisfied by the logic function thus arbitrarily formed.

8. 发明专利

DE2935104A1 未知
公开(公告)号：DE2935104A1
公开(公告)日：1980-03-13
申请号：DE2935104
申请日：1979-08-30
申请人： HITACHI LTD
发明人： HAGIWARA YOSHIMUNE , SAWASE TERUMI , TAKAI ATSUSHI , KITA YUZO , HONDA AKIRA
IPC分类号： H03J5/02 , H03J5/00
摘要： A television receiver of electronic tuning type employing a variable capacitance diode in a local oscillator of its tuning circuit, which comprises a memory storing a plurality of digital data indicative of tuning voltages corresponding to a plurality of channels respectively so that a tuning voltage corresponding to a selected channel can be applied to the variable capacitance diode in the tuning circuit, a D/A converter converting a digital data corresponding to a selected channel into an analog voltage to be supplied to the variable capacitance diode, and a tuning voltage control circuit which functions to sequentially modify, at a predetermined rate, the digital data of the selected channel read out from the memory until the tuning point is reached in the tuning circuit, and which applies sequentially such a signal to the D/A converter, whereby the tuning circuit can be tuned to the selected channel regardless of secular and other variations in the operating characteristic of the variable capacitance diode.

9. 发明专利

DE68927907D1 未知
公开(公告)号：DE68927907D1
公开(公告)日：1997-04-30
申请号：DE68927907
申请日：1989-09-29
申请人： HITACHI LTD
发明人： SAWASE TERUMI , HAGIWARA YOSHIMUNE , NAKAMURA HIDEO , HATORI HIROYUKI , BABA SHIROU , AKAO YASUSHI
IPC分类号： G06F9/24 , G06F9/38 , G06F11/267 , G06F15/78
摘要： A single chip microcomputer comprises a control circuit (12a, 12b), a processing circuit (13a, 13b) and a plurality of address register - status register pairs. A logical unit formed within the control circuit (12a, 12b) comprises an electrically writable non-volatile semiconductor memory device. Information can be externally written into the non-volatile semiconductor memory included in the logical unit, and the plurality of address register - status register pairs can be arbitrarily selected. As a result, logic function of the logical unit can be arbitrarily established in accordance with externally supplied information. Demanded specifications of various users can be satisfied by the logic function thus arbitrarily formed.

10. 发明专利

DE3852251T2 未知
公开(公告)号：DE3852251T2
公开(公告)日：1995-06-22
申请号：DE3852251
申请日：1988-09-08
申请人： HITACHI LTD
发明人： SAWASE TERUMI , NOGUCHI KOUKI , NAKAMURA HIDEO , AKAO YASUSHI , BABA SHIRO , HAGIWARA YOSHIMUNE
IPC分类号： G11C29/00 , G06F7/00 , G06F9/22 , G06F9/24 , G06F15/78 , G11C16/02 , G11C17/00
摘要： A logic circuit (6) built in a single-chip microprocessor is configured of electrically-programmable memory elements, and information is written into the memory elements from outside, whereby a logic circuit having any desired logical functions can be constructed. The writing operation of the memory elements can be executed in a short time, and a user can obtain the single-chip microprocessor having hardware of peculiar prescribed specifications, in a short period.

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