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1. 发明专利

DE69232232T2 未知
公开(公告)号：DE69232232T2
公开(公告)日：2002-08-29
申请号：DE69232232
申请日：1992-06-22
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KAWASAKI SHUMPEI , SAKAKIBARA EIJI , FUKADA KAORU , YAMAZAKI TAKANAGA , AKAO YASUSHI , BABA SHIRO , KIHARA TOSHIMASA , KURAKAZU KEIICHI , TSUKAMOTO TAKASHI , MASUMURA SHIGEKI , TAWARA YASUHIRO , KASHIWAGI YUGO , FUJITA SHUYA , ISHIDA KATSUHIKO , SAWA NORIKO , ASANO YOICHI , CHAKI HIDEAKI , SUGAWARA TADAHIKO , KAINAGA MASAHIRO , NOGUCHI KOUKI , WATABE MITSURU
IPC分类号： G06F9/28 , G06F7/483 , G06F7/52 , G06F7/527 , G06F7/535 , G06F7/537 , G06F9/30 , G06F9/302 , G06F9/305 , G06F9/318 , G06F9/32 , G06F9/38
摘要： A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting an instruction format of a fixed length of 2 n bits which is smaller than the length of the maximum data word fed to instruction execution means. The control of the coded division is executed by noting the code bits.

2. 发明专利

DE69324651D1 未知
公开(公告)号：DE69324651D1
公开(公告)日：1999-06-02
申请号：DE69324651
申请日：1993-10-25
申请人： HITACHI LTD , HITACHI VLSI ENG , HITACHI MICROCOMPUTER SYST
发明人： KAWASAKI SHUMPEI , FUKADA KAORU , WATABE MITSURU , NOGUCHI KOUKI , MATSUBARA KIYOSHI , MOCHIZUKI ISAMU , SUZUKAWA KAZUFUMI , MASUMURA SHIGEKI , AKAO YASUSHI , SAKAKIBARA EIJI
IPC分类号： G06F12/00 , G06F12/06 , G06F13/42 , G06F15/78
摘要： A microcomputer that is easy to use and connected direct to such memories as dynamic and static RAM's and to other peripheral circuits. The microcomputer has strobe signal output terminals CASH*, CASL* and RAS* for direct connection to a dynamic RAM, and chip select signal output terminals CS0* through CS6* for outputting a chip select signal in parallel with the output from the strobe signal output terminals. The microcomputer further includes address output terminals for outputting a non-multiplexed or multiplexed address signal as needed, and data I/O terminals for selectively outputting the address signal to comply with a multiple-bus interface scheme.

3. 发明专利

DE69232232D1 未知
公开(公告)号：DE69232232D1
公开(公告)日：2002-01-10
申请号：DE69232232
申请日：1992-06-22
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KAWASAKI SHUMPEI , SAKAKIBARA EIJI , FUKADA KAORU , YAMAZAKI TAKANAGA , AKAO YASUSHI , BABA SHIRO , KIHARA TOSHIMASA , KURAKAZU KEIICHI , TSUKAMOTO TAKASHI , MASUMURA SHIGEKI , TAWARA YASUHIRO , KASHIWAGI YUGO , FUJITA SHUYA , ISHIDA KATSUHIKO , SAWA NORIKO , ASANO YOICHI , CHAKI HIDEAKI , SUGAWARA TADAHIKO , KAINAGA MASAHIRO , NOGUCHI KOUKI , WATABE MITSURU
IPC分类号： G06F9/28 , G06F7/483 , G06F7/52 , G06F7/527 , G06F7/535 , G06F7/537 , G06F9/30 , G06F9/302 , G06F9/305 , G06F9/318 , G06F9/32 , G06F9/38
摘要： A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting an instruction format of a fixed length of 2 n bits which is smaller than the length of the maximum data word fed to instruction execution means. The control of the coded division is executed by noting the code bits.

4. 发明专利

JPH06150023A MICROCOMPUTER AND SYSTEM THEREOF 失效
公开(公告)号：JPH06150023A
公开(公告)日：1994-05-31
申请号：JP32259892
申请日：1992-11-06
申请人： HITACHI LTD , HITACHI MICOM SYST KK , HITACHI VLSI ENG
发明人： KAWASAKI SHUNPEI , FUKADA KAORU , WATABE MITSURU , NOGUCHI YOSHIKI , MATSUBARA KIYOSHI , MOCHIZUKI ISAMU , SUZUKAWA KAZUFUMI , MASUMURA SHIGEKI , AKAO YASUSHI , SAKAKIBARA EIJI
IPC分类号： G06F12/00 , G06F12/06 , G06F13/42 , G06F15/78
摘要： PURPOSE:To flexibly deal with required system construction by adopting an interface for a dynamic RAM and an interface for a memory such as a static RAM and a peripheral circuit to the microcomputer. CONSTITUTION:This microcomputer is provided with strobe signal output terminals CASH, CASL and RAS for the dynamic RAM and chip select signal output terminals CSO-CS6 for outputting chip select signals parallelly to respective outputs. Then, an address output terminal can output non-multiplexed address signals or address signals multiplexed as needed, and the input/output terminal of data is provided for selectively outputting the address signals so as to cope with the multibus system interface. Thus, the interface for the dynamic RAM and the interface for the memory such as the static RAM and the other peripheral circuit are adopted to the microcomputer.

5. 发明专利

JPH05197546A MICROCOMPUTER AND DIVIDING CIRCUIT 失效
公开(公告)号：JPH05197546A
公开(公告)日：1993-08-06
申请号：JP15452592
申请日：1992-05-21
申请人： HITACHI LTD , HITACHI MICOM SYST KK , HITACHI VLSI ENG
发明人： KAWASAKI SHUNPEI , TAWARA YASUHIRO , FUKADA KAORU , YAMAZAKI TAKANAGA , SAKAKIBARA EIJI , KURAKAZU KEIICHI , AKAO YASUSHI , BABA SHIRO , KIHARA TOSHIMASA , KASHIWAGI YUUGO , FUJITA HIDEYA , ISHIDA KATSUHIKO , SAWA NORIKO , ASANO YOICHI , CHAGI HIDEAKI , SUGAWARA MASAHIKO , UMINAGA MASAHIRO , NOGUCHI YOSHIKI , WATABE MITSURU , TSUKAMOTO TAKU , MASUMURA SHIGEKI
IPC分类号： G06F9/28 , G06F7/483 , G06F7/52 , G06F7/527 , G06F7/535 , G06F7/537 , G06F9/30 , G06F9/302 , G06F9/305 , G06F9/318 , G06F9/32 , G06F9/38
摘要： PURPOSE:To decrease program capacity or improve the utilization efficiency of a program memory by employing a fixed length instruction format which is smaller in the number of bits than the maximum length of data words supplied to an instruction executing means. CONSTITUTION:The microcomputer has RISC(reduced instruction set type computer) type architecture and has the fixed length instruction format. When data and instructions are transferred, a bus, e.g. an internal data bus IDB is of 32-bit constitution, but the instructions are in 16-bit fixed length instruction format. Then 16-bit instruction buffers (instruction queue) IRH and IRL store the instructions, one by one, and the instructions are loaded respectively in a single instruction fetch cycle. The instructions are transferred in 32-bit units through the internal data bus IDB and then loaded in an instruction register IR1 through a multiplexer MPX. Then the 16-bit instruction register IR1 holds the instructions present in an instruction decoding stage.

6. 发明专利

DE19527347B4 未知
公开(公告)号：DE19527347B4
公开(公告)日：2007-10-11
申请号：DE19527347
申请日：1995-07-26
申请人： HITACHI LTD , HITACHI AUTOMOTIVE ENG
发明人： KATAYAMA HIROSHI , KAYANO MITSUO , WATABE MITSURU , ISHII JUNICHI , ICHIHASHI TETSUYA , SASAKI SHOJI , TANAKA SATOSHI
IPC分类号： F02D45/00 , G05B19/042 , F02D41/24 , F02D41/26 , F02D43/00 , F02P5/15 , F02P7/077 , G05B15/02 , G06F1/04 , G06F15/78
摘要： A control processor has an output pattern generating circuit operating in cooperation with a free running timer, and a virtual OCR program for virtually realizing a large number of timer outputs by use of the output pattern generating circuit. Because more timer outputs than the actually incorporated timers are handled, the function of timer outputs is implemented with a higher degree of freedom and in a wider range of applications. For its enhanced function and availability, the control processor costs less.

7. 发明专利

DE69432886T2 未知
公开(公告)号：DE69432886T2
公开(公告)日：2004-06-03
申请号：DE69432886
申请日：1994-09-26
申请人： HITACHI LTD
发明人： SATOH JUN , YAMAGISHI KAZUSHIGE , NAKASHIMA KEISUKE , KATSURA KOYO , MIYAMOTO TAKASHI , WATABE MITSURU , OHMURA KENICHIROH
IPC分类号： G06F3/153 , G06F1/04 , G06F1/06 , G06F1/08 , G06F1/12 , G06F12/00 , G06F12/02 , G06F12/06 , G06F13/00 , G06F13/14 , G06F13/16 , G06F15/00 , G06F15/76 , G06T1/00 , G06T1/20 , G06T1/60 , G09G5/36 , G09G5/393 , G11C5/00 , G11C11/401 , G11C11/407 , G06F15/16 , G06F13/28
摘要： A data processor comprises a bus control circuit (14) adapted to be interfaced with a synchronous DRAM (22) which can be accessed in synchronism with a clock signal (CLK), a plurality of data processing modules (12, 13) coupled to said bus control circuit (14) for producing data and addresses for accessing a memory (22), and a clock driver (16) for feeding intrinsic operation clocks to said data processing modules (12, 13) and for feeding the clock signal for accessing said memory (22) in synchronism with the operations of said data processing modules (12, 13) to be operated by the operation clock signals, to the outside.

8. 发明专利

DE3575797D1 未知
公开(公告)号：DE3575797D1
公开(公告)日：1990-03-08
申请号：DE3575797
申请日：1985-10-29
申请人： HITACHI LTD
发明人： MORINAGA SHIGEKI , WATABE MITSURU
IPC分类号： G06F15/78 , G04G15/00 , G04G99/00 , G04G1/00
摘要： A counter/timer device includes a plurality of registers (105) each capable of performing any of the function of a counter/timer register, the function of a capture register and the function of a compare register, in accordance with a command from a central processing unit, and a plurality of task registers (103) corresponding to tasks which are to be carried out by using the above registers. Each of the task registers stores a task instruction for specifying a counter/timer register and a capture/compare register which are used in a task, and for specifying the operation mode of each of the specified registers. The task registers are scanned to successively read out the task instructions, and each of the read-out task instructions controls the operation of each of registers used in a corresponding task. Thus, tasks corresponding to the task instructions are all carried out at once.

9. 发明专利

DE60144459D1 Kraftfahrzeugsteuerungssystem und Fahrzeug damit 未知
公开(公告)号：DE60144459D1
公开(公告)日：2011-06-01
申请号：DE60144459
申请日：2001-07-17
申请人： HITACHI LTD
发明人： SAKURAI KOHEI , KANEKAWA NOBUYASU , MURABAYASHI FUMIO , WATABE MITSURU , HAYASHIBARA TOSHIO
IPC分类号： B60R16/02 , B60T8/88 , B60W50/00 , F02D41/30 , G06F7/00 , G06F17/00 , H04Q9/00

10. 发明专利

HK1011101A1 MICROCOMPUTER 未知
公开(公告)号：HK1011101A1
公开(公告)日：1999-07-02
申请号：HK98111668
申请日：1998-10-30
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： AKAO YASUSHI , KAWASAKI SHUMPEI , SAKAKIBARA EIJI , FUKADA KAORU , YAMAZAKI TAKANAGA , BABA SHIRO , KIHARA TOSHIMASA , KURAKAZU KEIICHI , TSUKAMOTO TAKASHI , MASUMURA SHIGEKI , TAWARA YASUHIRO , KASHIWAGI YUGO , FUJITA SHUYA , ISHIDA KATSUHIKO , SAWA NORIKO , ASANO YOICHI , CHAKI HIDEAKI , SUGAWARA TADAHIKO , KAINAGA MASAHIRO , NOGUCHI KOUKI , WATABE MITSURU
IPC分类号： G06F9/28 , G06F7/483 , G06F7/52 , G06F7/527 , G06F7/535 , G06F7/537 , G06F9/30 , G06F9/302 , G06F9/305 , G06F9/318 , G06F9/32 , G06F9/38 , G06F
摘要： A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting an instruction format of a fixed length of 2 n bits which is smaller than the length of the maximum data word fed to instruction execution means. The control of the coded division is executed by noting the code bits.

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