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1. 发明专利

JPS6123342A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路设备
公开(公告)号：JPS6123342A
公开(公告)日：1986-01-31
申请号：JP14238484
申请日：1984-07-11
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： UNNO TASUKU , TOMOSAWA AKIHIRO , MEGURO HIDEO , SUZUKI NORIO , YOSHIURA AIMEI , TANIGAKI YUKIO , SHIBATA TAKASHI
IPC分类号： H01L21/768
CPC分类号： H01L21/768
摘要： PURPOSE:To prevent an exfoliation by controlling a configuration of a conductive film to be a specified area thereby minimizing a stress occurred by the difference of a coefficient of thermal expansion between the conductive film and a PSG film. CONSTITUTION:The first conductive film 3, which is composed of a high melting point metal film or a silicide film which is a compound of a high melting point metal and a silicon, is set up on the upper part of a semiconductor substrate 1 by isolating electrically. The first insulating film 4 composed of phospho silicate glass film on which a glass flow is applied to cover this first conductive film 3 is set up. Said first conductive film 3 in this semiconductor integrated circuit device is formed to be a configuration of a specified area in which the separation does not occur from the first insulating film 4. When a pattern of the conductive film 3, for instance, is a rectangle approx. to a square, the product of a side A by a side B, that is, the area is formed into a configuration in order not to be over 400mum and the stress occurred by the difference of coefficient of thermal expansion between the conductive film 3 and the insulating film 4 on it is not more than a specified value.
摘要翻译：目的：通过将导电膜的配置控制在指定区域来防止剥离，从而使导电膜和PSG膜之间的热膨胀系数的差异发生最小化。构成：由高熔点金属膜或高熔点金属和硅的化合物的硅化物膜构成的第一导电膜3通过隔离来设置在半导体衬底1的上部电气。由施加了玻璃流以覆盖该第一导电膜3的磷酸硅玻璃膜构成的第一绝缘膜4被设定。该半导体集成电路器件中的所述第一导电膜3形成为从第一绝缘膜4不发生分离的特定区域的结构。当例如导电膜3的图案为矩形大约通过侧面B的侧面A的产物，即面积形成为不超过400μm2的构造，并且应力由导电性的热膨胀系数的差异而发生膜3和其上的绝缘膜4不超过规定值。

2. 发明专利

JPS6123343A Manufacture of semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造
公开(公告)号：JPS6123343A
公开(公告)日：1986-01-31
申请号：JP14238584
申请日：1984-07-11
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： MEGURO HIDEO , TOMOSAWA AKIHIRO , SUZUKI NORIO , UNNO TASUKU , YOSHIURA AIMEI , TANIGAKI YUKIO , SHIBATA TAKASHI
IPC分类号： H01L21/60 , H01L21/768
CPC分类号： H01L21/76897 , H01L21/768
摘要： PURPOSE:To prevent another exfoliation from occurring in order not to make a fall of an adhesive strength between a PSG film and a conductive film owing to forming of a connection hole at the time of a glass flow by forming the connection hole after forming the PSG film to cover a conductive film of a high melting point metal film or a silicide film and performing a glass flow. CONSTITUTION:After a MISFET consisting of a semiconductor substrate 1, an insulating film 3, a conductive film 4 and a pair of and a double structure of semiconductor regions 5 and 6 is almost completed, an insulating film 7 is formed to cover at least the conductive film 4. An insulating film 8 flattening an upper part of the insulating film is formed through the glass flow process after this. Connection holes 9A and 9B are formed by eliminating the insulating films 7 and 8 of the designated upper part of the conductive film 4 and insulating films 3, 7 and 8 of the designated upper part of a semiconductor region 6 after then. Though an adhesive strength between the insulating film 7 and an molybdenum silicide film 4B divided with dotted lines decreases, another exfoliation does not occur because of forming connection holes 9A and 9B after performing a glass flow.
摘要翻译：目的：为了防止由于在形成PSG后通过形成连接孔而形成玻璃流动时的连接孔而导致PSG膜与导电膜之间的粘合强度下降，防止发生另外的剥离膜覆盖高熔点金属膜或硅化物膜的导电膜并进行玻璃流动。构成：在由半导体衬底1构成的MISFET之后，绝缘膜3，导电膜4和半导体区域5和6的一对双结构几乎完成，形成绝缘膜7以至少覆盖在此之后，通过玻璃流动方法形成平坦化绝缘膜的上部的绝缘膜8。然后，通过去除指定的导电膜4的上部的绝缘膜7和8以及之后的半导体区域6的指定的上部的绝缘膜3,7和8，形成连接孔9A和9B。虽然绝缘膜7和分解为虚线的硅化钼膜4B之间的粘合强度降低，但是由于在进行玻璃流动之后形成连接孔9A和9B，不会发生另一剥离。

3. 发明专利

JPS6123341A Manufacture of semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造
公开(公告)号：JPS6123341A
公开(公告)日：1986-01-31
申请号：JP14237284
申请日：1984-07-11
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： YOSHIURA AIMEI , TOMOSAWA AKIHIRO , MEGURO HIDEO , UNNO TASUKU , SUZUKI NORIO , TANIGAKI YUKIO , SHIBATA TAKASHI
IPC分类号： H01L21/60 , H01L21/768
CPC分类号： H01L21/76897 , H01L21/768
摘要： PURPOSE:To form a PSG film and to prevent another separation from occurring due to a glass flow or a phosphorous treatment by eliminating an internal stress occurred on a silicide film or a high melting point metal film through introducing impurities with a heat treatment in a manner not to exist. CONSTITUTION:Impurities are introduced into a principal plane of a semiconductor region 5 of both ends of a conductive film 4 through an insulating film 3 by using the conductive film 4 as a mask for introducing impurities. As this introduction of impurities is performed by a relatively big energy with an arsenic ion at full atomic weight, a crystal damage is occurred on a molybdenum silicide film and a stress inducing another separation is generated. As an n type semiconductor region 6 is formed by performing an spreading diffusion introduced after this, an internal stress occurred in the molybdenum silicide film 4B with the introduction of impurities is eliminated. This spreading diffusion, that is, a heat treatment process is performed, for instance, within the time of about 10min with the temperature of the heat treatment of about 950 deg.C.
摘要翻译：目的：为了形成PSG膜，并且通过以通过以热处理的方式引入杂质而消除硅化物膜或高熔点金属膜上产生的内应力来防止由于玻璃流动或磷处理而发生的另一分离不存在构成：通过使用导电膜4作为引入杂质的掩模，通过绝缘膜3将杂质引入到导电膜4的两端的半导体区域5的主平面中。由于杂质的引入通过具有完全原子量的砷离子的相对大的能量进行，所以在硅化钼膜上发生晶体损伤，并且产生引起另一分离的应力。由于通过在其之后引入扩散扩散形成n +型半导体区域6，因此消除了导入杂质的硅化钼膜4B中产生的内部应力。这种扩散扩散，即热处理过程例如在约10分钟的时间内进行，热处理温度为约950℃。

4. 发明专利

JP2000133626A SUBSTRATE WASHING DEVICE 失效
公开(公告)号：JP2000133626A
公开(公告)日：2000-05-12
申请号：JP30370498
申请日：1998-10-26
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD , DAINIPPON SCREEN MFG
发明人： KINOSHITA HIDEO , SAKATA YASUKI , ONISHI AKIHIRO , TOMOSAWA AKIHIRO , HIRAOKA NOBUYASU , NISHI KOJI
IPC分类号： B08B3/02 , B08B3/12 , H01L21/304
摘要： PROBLEM TO BE SOLVED: To prevent the re-adhesion of any particles on the surface of a substrate, and to prevent the damage of the surface of the substrate due to ultrasonic waves at the time of supplying washing liquid to which ultrasonic waves are applied, and washing the back face of the substrate. SOLUTION: In this substrate washing device, a substrate W is rotated through a mechanical type spin chuck 10 in a state that the surface of the substrate W is faced down, and washing liquid to which ultrasonic waves are applied is supplied from a first washing liquid supplying nozzle 17 to the back face of the substrate W so that the back face of the substrate W can be washed. In this case, the washing liquid is radially supplied from a second washing liquid supplying nozzle 20 from the lower part of the substrate W to the surface of the substrate W. The washing liquid is thinly spread on the surface of the substrate W so that the re-adhesion of any particles on the surface of the substrate can be prevented, and the washing liquid is spread without being locally made thick on the surface of the substrate so that even when the ultrasonic waves are transmitted from the back face side of the substrate W to the surface of the substrate, the surface of the substrate can be prevented from being damaged due to the ultrasonic waves.

5. 发明专利

JPH10154677A METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH10154677A
公开(公告)日：1998-06-09
申请号：JP31442496
申请日：1996-11-26
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST
发明人： TOMOSAWA AKIHIRO , KINOSHITA HIDEO , SAKATA YASUKI , OONISHI AKIHIRO
IPC分类号： H01L21/304
摘要： PROBLEM TO BE SOLVED: To clean both surfaces of a semiconductor wafer simultaneously in scrub cleaning by utilizing ultrasonic. SOLUTION: Wash water 27 to which ultrasonic vibration has been propagated is emitted on the upper surface of a semiconductor substrate 1, and simultaneously pure water 28 is sprayed on to the lower surface of the semiconductor substrate 1. In such a cleaning the wash water 27 to which ultrasonic vibration has been propagated is emitted at an incident angle so as to attain a maximize transmittancy of ultrasonic through the substrate. Thus the pure water 28 is vibrated by the ultrasonic transmitting the semiconductor substrate 1 to clean the lower surface of the semiconductor substrate 1 simultaneously.

6. 发明专利

JPS62249454A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS62249454A
公开(公告)日：1987-10-30
申请号：JP9219286
申请日：1986-04-23
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： SHIMODA MAKI , SENBON TAKASHI , UEKI KAZUYOSHI , TOMOSAWA AKIHIRO , BANSHO JUNICHIRO , OONISHI TSUGUHIRO
IPC分类号： H01L21/3205 , H01L21/31
摘要： PURPOSE:To facilitate forming patterns such as wirings on the surface of predetermined layers without producing defects by a method wherein steps in the surface are so provided as to make the lengths of patterns which pass near the highest parts of the steps shorter or a structure in which there are practically no steps in the surface is provided. CONSTITUTION:A field insulating film 2 and an insulating film 3 are provided on the surface of a semiconductor substrate 1 and, for instance, a rectangular polycrystalline Si film 4 is provided on them. A layer insulating film 5 is provided so as to cover the polycrystalline Si film 4 and an Al film 6 and a photoresist film 7 are provided on the layer insulating film 5. As the parts of the surface of the layer insulating film 5 corresponding to the circumference 4a of the polycrystalline Si film 4 are the highest parts in this case, the thicknesses of the parts of the photoresist film 7 corresponding to the highest parts become thinner. However, the lengths of the parts of Al wirings 8 which are formed by etching the Al film 6 and pass near the highest parts are made to be shorter by predetermined values. With this constitution, the adhesion strengths of the parts of the photoresist film 7 where the film 7 is thinner to the Al film 6 are compensated by the adhesion strengths of the surrounding parts where the thickness is large. Therefore, defects of the Al wirings 8 such as distortion and short circuit can be avoided.

7. 发明专利

JPS58184A MANUFACTURING METHOD FOR INSULATED GATE TYPE SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS58184A
公开(公告)日：1983-01-05
申请号：JP6534182
申请日：1982-04-21
申请人： HITACHI LTD
发明人： TOMOSAWA AKIHIRO , KABURAGI MAKOTO
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/78
摘要： PURPOSE:To prevent pad caused contamination and thereby to stabilize element characteristics by a method wherein a polycrystalline Si layer is provided in the bonding pad forming section on an SiO2 film and the entire surface is coated with a PSG film whereupon a pad is built. CONSTITUTION:A P type well region 8 is diffusedly formed in an N type Si substrate 11. The whole surface is covered with an SiO2 film 12 and openings are provided in places where a source, drain, and gate and to be provided. Next, the substrate 11 and the exposed surface of the region 8 are coated with a gate SiO2 film and an polycrystalline Si film is grown over the entire surface including the SiO2 film. Etching is performed for the formation of gate electrodes 9a and 9b on the substrate 11 and the region 8 with a prescribed size SiO2 film working as underlay. At the same time, a bonding pad forming polycrystalline Si film 17 is formed on one of the films 12 surviving the etching process. Formation follows on the entire surface of an SiO2 film 10a, wherein a window is provided. A P type source and drain regions are diffusedly formed on the both sides of the electrode 9a and an N type source and drain regions are diffusedly formed on the both sides of the electrode 9b. At the same time, after endowing the film 17 with conductivity, the entire surface is coated with a PSG film 15 across which an Al pad 13 is provided on the film 17.

8. 发明专利

JPS57154858A METHOD FOR FORMATION OF ELECTRODE 失效
公开(公告)号：JPS57154858A
公开(公告)日：1982-09-24
申请号：JP3941581
申请日：1981-03-20
申请人： HITACHI LTD
发明人： TOMOSAWA AKIHIRO , SAKAMOTO ISAO , MIYAMOTO KEIJI
IPC分类号： H01L21/60 , H01L21/768 , H01L23/522 , H01L23/532
摘要： PURPOSE:To prevent an unsatisfactory short-circuit by a method wherein a polyimide resin is provided between the lower Al wiring and the upper Cu-Ti composite layer. CONSTITUTION:The Al wiring 2 and the insulating film 3, consisting of the polyimide resin, and formed on a substrate 1. Then, a through hole 4 is provided on the film 3. Subsequently, a composite alloy film is formed by superposing a Ti film 5 and a Cu film 6. Then, an insulating film 7 is formed and a bake process is performed. The Ti-Cu film 6a is exposed, and then an Ni film 9 is formed on the exposed film 6a. Then, an Sn film 10, which will become a solder material, and a Pb film 11 are formed, while films 10 and 11 are alloyed, and a bump electrode is formed.

9. 发明专利

JPS5619491A TIMER FOR ELECTRONIC EQUIPMENT WITH INCORPORATED MEMORY 失效
公开(公告)号：JPS5619491A
公开(公告)日：1981-02-24
申请号：JP9501679
申请日：1979-07-27
申请人： HITACHI LTD
发明人： TOMOSAWA AKIHIRO
IPC分类号： G04G15/00 , G04G99/00
摘要： PURPOSE:To obtain a timer that can prevent information on an electronic equipment with an incorporated volatile memory from being erased, by connecting an input-side electric power source through a timer switch and derectly. CONSTITUTION:Through switch SW that turns on a fixed time time later through clocking method 2, output terminal OUT1 of timer 1 is connected to an input-side electric power source so as to actuate an electronic equpment with an incorporated volatile memory at a desired time. Output terminal OUT2 of timer 1, on the other hand, is connected direct to the input-side electric power source at any time and the volatile memory is supplied invariably with electric power without reference to the timer time, so that memory contents of the memory will never disapper. Therefore, the timer which can prevent information on the electronic equpment with the incorporated volatile memory from being erased can be obtained.

10. 发明专利

JPS5570057A PREPARATION OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS5570057A
公开(公告)日：1980-05-27
申请号：JP14342478
申请日：1978-11-22
申请人： HITACHI LTD
发明人： TOMOSAWA AKIHIRO , SHIRATO TAKESHI , SAKAI YOSHIO
IPC分类号： H01L27/04 , H01L21/822 , H01L27/06 , H01L29/78
摘要： PURPOSE:To improve the accuracy of patterning, by selectively doping impurities to polysilicon after patterning the polysilicon when using the polysilicon as an electrode, wiring or resistance as MOSIC. CONSTITUTION:A thick field SiO2 film 12 and a thin gate SiO2 film 12A are formed on a surface of a P-type Si substrate 10, and the whole surface is coated with a poly Si layer 14. The poly Si layer hardly contains impurities. Other portions except a poly Si layer 14A for a gate electrode and a poly Si layer 14B for resistance are removed by patterning the poly Si layer 14 by means of a photo-resist mask. The poly Si layer 14B for high resistance is coated with an Si3N4 film 16 and an SiO2 film 18, and the gate electrode 14A is doped and a source 20 and a drain 22 are doped, thus completing a MOSIC. Consequently, the high accuracy of finishing can be obtained because poly Si is patterned under a condition that impurities are hardly contained.

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