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    • 1. 发明专利
    • Semiconductor intefrated circuit device
    • 半导体电路设计
    • JPS61117785A
    • 1986-06-05
    • JP23839584
    • 1984-11-14
    • Hitachi LtdHitachi Micro Comput Eng Ltd
    • SHIBATA TAKASHIAOKI KAZUOYASUNAGA SHINICHISUZUKI HIROSHI
    • G11C17/00G11C11/34G11C11/401G11C11/409G11C11/413H03K19/0175
    • PURPOSE: To lower the peak value of noise generated in a power source line by operating plural output buffers time serially according to set time difference by a delay circuit.
      CONSTITUTION: Four output buffers out of eight data output buffers that amplify read out signals from memory arrays MARY 4W7 consist of a sense amplifier SA4, inverter circuits for delaying IV1, IV2 and an output buffer. The delay time by IV1, IV2 is set larger than the operating time of an output buffer DOB3 etc. when an output enable signal OE is made to 'H', and -OE is made to 'L', an NAND gate G3 and an NOR gate G4 open, and NMOSTQ3 OR PMOSTQ4 turns on, and the output signal is sent out from a terminal D4.
      COPYRIGHT: (C)1986,JPO&Japio
    • 目的:通过延迟电路根据设定的时间间隔逐行地操作多个输出缓冲器来降低电源线中产生的噪声的峰值。 构成:八个数据输出缓冲器中的四个输出缓冲器,用于放大来自存储器阵列的读出信号MARY 4-7包括读出放大器SA4,用于延迟IV1,IV2和输出缓冲器的反相器电路。 当使输出使能信号OE为“H”,并将-OE设为“L”时,将与时钟相关的延迟时间设定为大于输出缓冲器DOB3等的工作时间,NAND门G3和 NOR门G4断开,NMOSTQ3或PMOSTQ4导通,输出信号从端子D4发出。
    • 2. 发明专利
    • Manufacture of semiconductor integrated circuit device
    • 半导体集成电路器件的制造
    • JPS6123341A
    • 1986-01-31
    • JP14237284
    • 1984-07-11
    • Hitachi LtdHitachi Micro Comput Eng Ltd
    • YOSHIURA AIMEITOMOSAWA AKIHIROMEGURO HIDEOUNNO TASUKUSUZUKI NORIOTANIGAKI YUKIOSHIBATA TAKASHI
    • H01L21/60H01L21/768
    • H01L21/76897H01L21/768
    • PURPOSE:To form a PSG film and to prevent another separation from occurring due to a glass flow or a phosphorous treatment by eliminating an internal stress occurred on a silicide film or a high melting point metal film through introducing impurities with a heat treatment in a manner not to exist. CONSTITUTION:Impurities are introduced into a principal plane of a semiconductor region 5 of both ends of a conductive film 4 through an insulating film 3 by using the conductive film 4 as a mask for introducing impurities. As this introduction of impurities is performed by a relatively big energy with an arsenic ion at full atomic weight, a crystal damage is occurred on a molybdenum silicide film and a stress inducing another separation is generated. As an n type semiconductor region 6 is formed by performing an spreading diffusion introduced after this, an internal stress occurred in the molybdenum silicide film 4B with the introduction of impurities is eliminated. This spreading diffusion, that is, a heat treatment process is performed, for instance, within the time of about 10min with the temperature of the heat treatment of about 950 deg.C.
    • 目的:为了形成PSG膜,并且通过以通过以热处理的方式引入杂质而消除硅化物膜或高熔点金属膜上产生的内应力来防止由于玻璃流动或磷处理而发生的另一分离 不存在 构成:通过使用导电膜4作为引入杂质的掩模,通过绝缘膜3将杂质引入到导电膜4的两端的半导体区域5的主平面中。 由于杂质的引入通过具有完全原子量的砷离子的相对大的能量进行,所以在硅化钼膜上发生晶体损伤,并且产生引起另一分离的应力。 由于通过在其之后引入扩散扩散形成n +型半导体区域6,因此消除了导入杂质的硅化钼膜4B中产生的内部应力。 这种扩散扩散,即热处理过程例如在约10分钟的时间内进行,热处理温度为约950℃。
    • 3. 发明专利
    • Semiconductor integrated circuit device
    • 半导体集成电路设备
    • JPS6123342A
    • 1986-01-31
    • JP14238484
    • 1984-07-11
    • Hitachi LtdHitachi Micro Comput Eng Ltd
    • UNNO TASUKUTOMOSAWA AKIHIROMEGURO HIDEOSUZUKI NORIOYOSHIURA AIMEITANIGAKI YUKIOSHIBATA TAKASHI
    • H01L21/768
    • H01L21/768
    • PURPOSE:To prevent an exfoliation by controlling a configuration of a conductive film to be a specified area thereby minimizing a stress occurred by the difference of a coefficient of thermal expansion between the conductive film and a PSG film. CONSTITUTION:The first conductive film 3, which is composed of a high melting point metal film or a silicide film which is a compound of a high melting point metal and a silicon, is set up on the upper part of a semiconductor substrate 1 by isolating electrically. The first insulating film 4 composed of phospho silicate glass film on which a glass flow is applied to cover this first conductive film 3 is set up. Said first conductive film 3 in this semiconductor integrated circuit device is formed to be a configuration of a specified area in which the separation does not occur from the first insulating film 4. When a pattern of the conductive film 3, for instance, is a rectangle approx. to a square, the product of a side A by a side B, that is, the area is formed into a configuration in order not to be over 400mum and the stress occurred by the difference of coefficient of thermal expansion between the conductive film 3 and the insulating film 4 on it is not more than a specified value.
    • 目的:通过将导电膜的配置控制在指定区域来防止剥离,从而使导电膜和PSG膜之间的热膨胀系数的差异发生最小化。 构成:由高熔点金属膜或高熔点金属和硅的化合物的硅化物膜构成的第一导电膜3通过隔离来设置在半导体衬底1的上部 电气。 由施加了玻璃流以覆盖该第一导电膜3的磷酸硅玻璃膜构成的第一绝缘膜4被设定。 该半导体集成电路器件中的所述第一导电膜3形成为从第一绝缘膜4不发生分离的特定区域的结构。当例如导电膜3的图案为矩形 大约 通过侧面B的侧面A的产物,即面积形成为不超过400μm2的构造,并且应力由导电性的热膨胀系数的差异而发生 膜3和其上的绝缘膜4不超过规定值。
    • 4. 发明专利
    • Manufacture of semiconductor integrated circuit device
    • 半导体集成电路器件的制造
    • JPS6123343A
    • 1986-01-31
    • JP14238584
    • 1984-07-11
    • Hitachi LtdHitachi Micro Comput Eng Ltd
    • MEGURO HIDEOTOMOSAWA AKIHIROSUZUKI NORIOUNNO TASUKUYOSHIURA AIMEITANIGAKI YUKIOSHIBATA TAKASHI
    • H01L21/60H01L21/768
    • H01L21/76897H01L21/768
    • PURPOSE:To prevent another exfoliation from occurring in order not to make a fall of an adhesive strength between a PSG film and a conductive film owing to forming of a connection hole at the time of a glass flow by forming the connection hole after forming the PSG film to cover a conductive film of a high melting point metal film or a silicide film and performing a glass flow. CONSTITUTION:After a MISFET consisting of a semiconductor substrate 1, an insulating film 3, a conductive film 4 and a pair of and a double structure of semiconductor regions 5 and 6 is almost completed, an insulating film 7 is formed to cover at least the conductive film 4. An insulating film 8 flattening an upper part of the insulating film is formed through the glass flow process after this. Connection holes 9A and 9B are formed by eliminating the insulating films 7 and 8 of the designated upper part of the conductive film 4 and insulating films 3, 7 and 8 of the designated upper part of a semiconductor region 6 after then. Though an adhesive strength between the insulating film 7 and an molybdenum silicide film 4B divided with dotted lines decreases, another exfoliation does not occur because of forming connection holes 9A and 9B after performing a glass flow.
    • 目的:为了防止由于在形成PSG后通过形成连接孔而形成玻璃流动时的连接孔而导致PSG膜与导电膜之间的粘合强度下降,防止发生另外的剥离 膜覆盖高熔点金属膜或硅化物膜的导电膜并进行玻璃流动。 构成:在由半导体衬底1构成的MISFET之后,绝缘膜3,导电膜4和半导体区域5和6的一对双结构几乎完成,形成绝缘膜7以至少覆盖 在此之后,通过玻璃流动方法形成平坦化绝缘膜的上部的绝缘膜8。 然后,通过去除指定的导电膜4的上部的绝缘膜7和8以及之后的半导体区域6的指定的上部的绝缘膜3,7和8,形成连接孔9A和9B。 虽然绝缘膜7和分解为虚线的硅化钼膜4B之间的粘合强度降低,但是由于在进行玻璃流动之后形成连接孔9A和9B,不会发生另一剥离。
    • 6. 发明专利
    • Multi-os configuration method
    • 多操作系统配置方法
    • JP2007035066A
    • 2007-02-08
    • JP2006270265
    • 2006-10-02
    • Hitachi Ltd株式会社日立製作所
    • SEKIGUCHI TOMONORIARAI TOSHIAKIKANEKO SHIGENORIONO HIROSHIINOUE TAROSHIBATA TAKASHI
    • G06F9/46G06F9/48
    • PROBLEM TO BE SOLVED: To provide a system for enabling one computer to easily run a plurality of OSs at the same time only with software relative to a complicated and great-overhead OS control system of a conventional virtual computer system. SOLUTION: A plurality of OSs are run at the same time through the steps of: dividing hardware resources managed by a first OS and another OS; initiating the other OS; switching the active OS; and determining an OS to perform interruption processing in accordance with an interruption factor and initiating an appropriate interruption handler. According to the present invention, a new function of operation completely independent of the first OS can be perfectly integrated into a computer, thereby achieving reduction of an interruption response time, improvement in reliability and the like. COPYRIGHT: (C)2007,JPO&INPIT
    • 要解决的问题:提供一种使得一台计算机能够相对于常规虚拟计算机系统的复杂且高架空操作系统控制系统而仅使用软件同时容易地运行多个OS的系统。 解决方案:通过以下步骤同时运行多个OS:划分由第一OS和另一OS管理的硬件资源; 启动其他操作系统; 切换主动操作系统; 以及确定OS以根据中断因素执行中断处理并启动适当的中断处理程序。 根据本发明,可以将完全独立于第一OS的新功能的操作完美地集成到计算机中,从而实现中断响应时间的减少,可靠性的提高等。 版权所有(C)2007,JPO&INPIT
    • 10. 发明专利
    • DYNAMOELECTRIC MACHINE
    • JPH11262212A
    • 1999-09-24
    • JP6251098
    • 1998-03-13
    • HITACHI LTD
    • AMAGI SHIGEOSHIBATA TAKASHI
    • H02K3/48
    • PROBLEM TO BE SOLVED: To provide a dynamoelectric machine which can be assembled, without giving damages to a stator insulating layer and has a high reliability. SOLUTION: Insulating layers are applied to the circumferences of the stator winding conductors 1 of a dynamoelectric machine. The stator winding conductors 1 are wound in a plurality of slots 50, formed in a stator core 30 consisting of layered electromagnetic steel plates. In order to prevent the stator winding conductor 1 from vibration and falling-off from the slot 50, which are caused by an electromagnetic force applied to the stator winding conductor 1, a flat spring 4 is inserted between the stator winding conductor 1 and a wedge 5 inserted into the stator core surface side of the slot 50. The flat spring 4 which is inserted between the stator winding conductor 1 and the wedge 5 is corrugated, so as to have two or more corrugation amplitudes in the radial direction of the stator and, in the axial direction of the stator core 30, the period of the high amplitude corrugation is longer than the period of the low amplitude corrugation.