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1. 发明专利

JP2013081010A Analog input circuit or analog/digital conversion device 审中-公开
标题翻译：模拟输入电路或模拟/数字转换器件
公开(公告)号：JP2013081010A
公开(公告)日：2013-05-02
申请号：JP2011218841
申请日：2011-10-03
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KAWADA YOSHIHIRO , ISHIKAWA TORU , YOKOYAMA KAZUTO , YOSHINUMA MASAHIRO
IPC分类号： H03M1/12
摘要： PROBLEM TO BE SOLVED: To provide an analog input circuit or an analog/digital conversion device that enables discharge of capacitors in a filter circuit and a flying capacitor circuit in a short time independently of an ON/OFF state of a control power supply without requiring external mechanical equipment and materials for discharge.SOLUTION: In an analog/digital conversion device, a plurality of sets of a filter circuit and a flying capacitor circuit connected in a cascade manner are provided, and latter parts of the flying capacitor circuits in the plurality of sets are commonly connected with an input terminal of an amplifier, and an analog/digital converter is provided at a latter part of the amplifier. The analog/digital conversion device is configured on a substrate connected with an external control power supply. In the analog/digital conversion device, the filter circuit and the flying capacitor circuit have a parallel capacitor, and a series circuit of a resistor and a normally-closed contact point that are connected in parallel to the parallel capacitor. The normally-closed contact point is connected between terminals of a control power supply, and is driven by an auxiliary relay excited via a control contact point.
摘要翻译：要解决的问题：提供一种模拟输入电路或模拟/数字转换装置，其能够在短时间内对滤波电路中的电容器和飞越电容器电路进行放电，而与控制电源的ON / OFF状态无关供应不需要外部机械设备和材料进行排放。解决方案：在模拟/数字转换装置中，提供多个以级联方式连接的多组滤波器电路和飞越电容电路，并且多组中的跨越电容电路的后部分共同连接具有放大器的输入端，并且模拟/数字转换器设置在放大器的后部。模拟/数字转换装置配置在与外部控制电源连接的基板上。在模拟/数字转换装置中，滤波电路和飞越电容电路具有并联电容器，以及与并联电容器并联连接的电阻器和常闭触点的串联电路。常闭触点连接在控制电源的端子之间，并由经由控制触点激励的辅助继电器驱动。版权所有（C）2013，JPO＆INPIT

2. 发明专利

JP2014041505A Maintenance system and maintenance method of control device 审中-公开
标题翻译：维护系统和维护方法的控制设备
公开(公告)号：JP2014041505A
公开(公告)日：2014-03-06
申请号：JP2012183782
申请日：2012-08-23
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： OSHIMA YOHEI , YAMAMOTO MASAYUKI , KAGAYA SHUNICHI , YOSHINUMA MASAHIRO
IPC分类号： G06F11/30 , G06F11/32
摘要： PROBLEM TO BE SOLVED: To provide a maintenance system which can acquire details of failure having occurred in a control device, provide a failure countermeasure, and procure replacement parts without spending much time.SOLUTION: An on-site maintenance staff reads a light emission pattern which includes failure information and is generated by light emission means provided on a control device at the site by using a light emission pattern reading terminal carried by the staff, and transmits the light emission pattern to a failure analysis center from the light emission pattern reading terminal via a communication network. The failure analysis center analyzes the light emission pattern to determine at least a failure countermeasure and necessary replacement parts, and transmits the analysis result to a service center. The service center at least transmits the failure countermeasure to the site, procures the necessary replacement parts and sends them to the site, or at least transmits the failure countermeasure to the site, procures the necessary replacement parts, sends them to the site, and also dispatches a service center side maintenance staff to the site.
摘要翻译：要解决的问题：提供可以获取控制装置中发生的故障的细节的维护系统，提供故障对策，并且在不花费大量时间的情况下购买替换部件。解决方案：现场维护人员读取发光图案其包括故障信息，并且由通过使用由人员携带的发光图案读取终端设置在现场的控制装置上的发光装置产生，并且将发光图案从发光图案读取终端发送到故障分析中心通过通信网络。故障分析中心分析发光模式至少确定故障对策和必要的更换部件，并将分析结果发送到服务中心。服务中心至少将故障对策传送到现场，采购必要的更换部件并将其发送到现场，或至少将故障对策传送到现场，采购必要的更换部件，发送到现场，以及派驻维修中心的维修人员到现场。

3. 发明专利

JP2003067219A Electronic computer system and recovery processing method 审中-公开
标题翻译：电子计算机系统和恢复处理方法
公开(公告)号：JP2003067219A
公开(公告)日：2003-03-07
申请号：JP2001259117
申请日：2001-08-29
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YOSHINUMA MASAHIRO , OSONOI HIDEKI
IPC分类号： G06F11/30
摘要： PROBLEM TO BE SOLVED: To provide an electronic computer system and its recovery method allowing a maintenance engineer to perform recovery processing without going to an installation site.
SOLUTION: An electronic computer system comprises at least two computers connected over a network; one is a computer 11 that sends a recovery processing request packet upon receiving a signal, which indicates that a computer has stopped, from failure detection means 13 checking whether the computer has stopped and the other is a computer 10 that has a recovery processing control circuit 104 executing recovery processing upon receiving the recovery processing request packet. If it is determined that the failure has been recovered after the computer 10 receives the recovery processing request packet and a microprocessor 101 executes recovery processing, the recovery processing control circuit 104 is set to the reset-inhibition state to end recovery processing.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供一种电子计算机系统及其恢复方法，允许维护工程师执行恢复处理而不去安装现场。解决方案：电子计算机系统包括通过网络连接的至少两台计算机; 一个是从故障检测装置13检查计算机是否停止而另一个是具有恢复处理控制电路的计算机10接收到指示计算机停止的信号的计算机11， 104在接收到恢复处理请求分组时执行恢复处理。如果在计算机10接收到恢复处理请求分组并且微处理器101执行恢复处理之后确定故障已经恢复，则恢复处理控制电路104被设置为复位禁止状态以结束恢复处理。

4. 发明专利

JP2011248801A Interface device 审中-公开
标题翻译：接口设备
公开(公告)号：JP2011248801A
公开(公告)日：2011-12-08
申请号：JP2010123887
申请日：2010-05-31
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TANAKA HIDECHIYO , YOKOYAMA KAZUTO , ISHIKAWA TORU , YOSHINUMA MASAHIRO , KOBAYASHI MASAMITSU , SEKI YUSUKE
IPC分类号： G06F11/20
摘要： PROBLEM TO BE SOLVED: To prevent inappropriate data from being inputted to process input/output devices in spite of non-coincidence of ID codes set in doubled interface devices.SOLUTION: An interface device 11 is provided with a station address setting switch 16 and a comparator circuit 12 that compares station addresses set in interface devices 11 and 21. There are further provided a transmission/reception control circuit 15 that transmits to process input/output devices 30A to 30N data received by the interface device 11 from a central arithmetic processing unit, an output circuit 14 that causes coincident station addresses to be stored in a memory circuit 13 and at the same time performs control to cause data to be inputted to the process input/output devices 30A to 30N or, if the station addresses are not coincident, to cause data not to be inputted to the process input/output devices 30A to 30N, and a non-coincidence display 17 that notifies non-coincidence if the station addresses are not coincident.
摘要翻译：要解决的问题：为了防止不必要的数据输入到处理输入/输出设备，尽管在双重接口设备中设置的ID代码不一致。解决方案：接口装置11设置有站地址设置开关16和比较电路12，比较器电路12对接口装置11和21中设置的站地址进行比较。还提供发送/接收控制电路15，其发送到处理输入/输出设备30A至30N由接口设备11从中央算术处理单元接收的数据，输出电路14使一致的站地址存储在存储器电路13中，同时执行控制以使数据成为输入到处理输入/输出设备30A至30N，或者如果站地址不一致，以使得不输入到处理输入/输出设备30A至30N的数据，以及通知非工作站的非重合显示器17，如果车站地址不一致，就是巧合。版权所有（C）2012，JPO＆INPIT

5. 发明专利

JP2013156872A Computer system 审中-公开
标题翻译：电脑系统
公开(公告)号：JP2013156872A
公开(公告)日：2013-08-15
申请号：JP2012017479
申请日：2012-01-31
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： OSHIMA YOHEI , OSONOI HIDEKI , YAMAMOTO MASAYUKI , KAWADA KENJI , YOSHINUMA MASAHIRO
IPC分类号： G06F1/26 , G06F1/30
摘要： PROBLEM TO BE SOLVED: To provide a computer system capable of suppressing a load on a power system due to simultaneous start of operation of plural computers without requiring complicated individual settings.SOLUTION: A computer system includes plural computers connected to a network. The plural computers are supplied with power from a common power supply source. At least one of the plural computers includes a power supply unit that receives power supplied from the power supply source and powers on the own computer, and power-on control means that controls the power supply unit to power on the computer with a delay of a predetermined delay time after the power supply unit receives power from the power supply source. The power-on control means collects the address of the own computer and the addresses of other computers connected to the network and sets the delay time on the basis of the collected addresses.
摘要翻译：要解决的问题：提供一种能够抑制由于多台计算机的同时开始运行而导致的电力系统负荷的计算机系统，而不需要复杂的单独设置。解决方案：计算机系统包括连接到网络的多个计算机。多台计算机由公用电源供电。多个计算机中的至少一个包括：电源单元，其接收从电源供给的电力并对自己的计算机供电;以及开机控制装置，其控制电源单元以延迟的方式对计算机通电电源单元从电源接收电力之后的预定延迟时间。上电控制装置收集自己的计算机的地址和连接到网络的其他计算机的地址，并根据所收集的地址设置延迟时间。

6. 发明专利

JP2004295702A Server 有权
公开(公告)号：JP2004295702A
公开(公告)日：2004-10-21
申请号：JP2003089567
申请日：2003-03-28
申请人： Hitachi Information & Control Systems Inc , Hitachi Ltd , 株式会社日立ハイコス , 株式会社日立製作所
发明人： KANAZAWA SUKEBUMI , FUKUMARU HIROAKI , YOSHINUMA MASAHIRO , SAKATA MASAYUKI , NEMOTO FUMIHIKO
IPC分类号： G06F1/20 , H05K7/20
摘要： PROBLEM TO BE SOLVED: To provide a server which continuously stably operates even if enhanced in performance and never suddenly causing a sudden server failure even if one cooling fan is stopped. SOLUTION: This server comprises: a mother board 5 set on the upper part of a hard disk unit 8 containing a hard disk drive 7 arranged under a server unit 1; a plurality of heat pipes 21 mounted on a CPU set on the mother board 5; a plurality of stages of cooling fins 4 mounted on the heat pipes 21; cooling fans 2 arranged on lateral sides relative to the alignment axis of the heat pipes 21; a plurality of ventilation holes 9 for guiding cooled air of the cooling fans 2 to the hard disk drive 7; and an exhaust port 10 provided on the surface opposed to the surface having the cooling fans of the server unit 1. COPYRIGHT: (C)2005,JPO&NCIPI

7. 发明专利

JPH09269855A DATA PROCESSING SYSTEM CAPABLE OF ON-LINE EXCHANGE OF MODULE 失效
公开(公告)号：JPH09269855A
公开(公告)日：1997-10-14
申请号：JP8004796
申请日：1996-04-02
申请人： HITACHI LTD , HITACHI PROCESS COMPUTER ENG
发明人： MURAMATSU HIROBUMI , SHOJI HIDEYOSHI , MIYAZAKI YOSHIHIRO , TAKATANI SOICHI , MIYAZAKI NAOTO , NAKAMURA AKIHISA , YOSHINUMA MASAHIRO
IPC分类号： G06F1/18 , G06F3/00 , G06F13/00
摘要： PROBLEM TO BE SOLVED: To securely execute work at ease without adversely affecting a module and a system bus by securely and electrically detaching a part being an exchange object before the module is physically inserted/extracted. SOLUTION: Bus switches 120A and 120B are connected to bus switch control parts 121A and 121B which on/off-change over the switches and a system bus 100. Connection/detachment timing detection parts 122A and 122B detect timing when the other module connected to the system bus 100 does not malfunction even if it receives noise occurring at the time of the electric connection/ detachment of the bus switches 120A and 120B when the bus connection/ detachment request command 123, the voltage abnormality 125 and the clock abnormality of the module 130 occur. Then, effect is transmitted to the switch control parts 121A and 121B. Furthermore, a function for outputting the extraction permission signal 124 of the module 130 after the bus switches 120A and 120B are turned off is provided.

8. 发明专利

JPH11161523A FAULT INFORMATION GATHERING DEVICE 失效
公开(公告)号：JPH11161523A
公开(公告)日：1999-06-18
申请号：JP32985897
申请日：1997-12-01
申请人： HITACHI LTD
发明人： KAWADA KENJI , MIYAZAKI YOSHIHIRO , TAKATANI SOICHI , NAKAMURA AKIHISA , YOSHINUMA MASAHIRO , KANEKO SHIGENORI
IPC分类号： G06F11/34
摘要： PROBLEM TO BE SOLVED: To efficiently gather and analyze fault information by starting an interruption in response to a report on the lapse of a specified time by a counter and copying data in an image memory to a backup area of a main memory by the interruption. SOLUTION: The connection of a reset/interruption changeover switch 108 is initialized to the side of an interruption control circuit 107. If some fault is detected in hardware or software during operation, a fault interruption is initiated to an interruption control circuit 107, which once receiving the fault interruption, issues a low-level interruption(INTA) to a processor 102 through a system bus 104 and makes a timer 116 to start counting. Then a fault information gathering program corresponding to the INTA process is started on the OS and the information in the image memory 113 is saved in two image memory backup areas of the main memory 103. Then the said timer 116 having started counting counts up, the interruption control 107 issues an unmasked interruption NMI.

9. 发明专利

JPH0877104A METHOD AND DEVICE FOR BUS ARBITRATION 失效
公开(公告)号：JPH0877104A
公开(公告)日：1996-03-22
申请号：JP21009294
申请日：1994-09-02
申请人： HITACHI LTD
发明人： NISHIBE SENICHI , FUKUMARU HIROAKI , MIYAZAKI YOSHIHIRO , TANJI MASAYUKI , YAMAGUCHI SHINICHIRO , NAKAMURA AKIHISA , TANAKA TAKAAKI , YOSHINUMA MASAHIRO
IPC分类号： G06F13/42 , G06F13/362
摘要： PURPOSE: To discriminate whether a bus is used or not by connecting a bus master, whose operation timing is later than the clock cycle of a common bus, to the common bus to resolve a lack of the setup time in the bus master due to delay of settlement of a bus occupation signal. CONSTITUTION: A common bus 51, bus masters 52 and 53 which output bus occupation request signals 59 and 511 at the time of the occurrence of a bus occupation request and use the bus, a bus arbiter circuit 54 which generates bus occupation permission signals 510 and 512 from bus occupation request signals 59 and 511, and a delay circuit 57 which delays signals by one or more clock cycles required for operation determination in bus masters are provided. When bus masters 52 and 53 occupy the common bus 51, bus occupation signals 59 and 511 are delayed by at least one clock cycle after transition of bus occupation signals 59 and 511 to the non-occupation state, and it is discriminated whether the bus should be occupied or not in the delayed clock cycle.

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