专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPH09269855A DATA PROCESSING SYSTEM CAPABLE OF ON-LINE EXCHANGE OF MODULE 失效
公开(公告)号：JPH09269855A
公开(公告)日：1997-10-14
申请号：JP8004796
申请日：1996-04-02
申请人： HITACHI LTD , HITACHI PROCESS COMPUTER ENG
发明人： MURAMATSU HIROBUMI , SHOJI HIDEYOSHI , MIYAZAKI YOSHIHIRO , TAKATANI SOICHI , MIYAZAKI NAOTO , NAKAMURA AKIHISA , YOSHINUMA MASAHIRO
IPC分类号： G06F1/18 , G06F3/00 , G06F13/00
摘要： PROBLEM TO BE SOLVED: To securely execute work at ease without adversely affecting a module and a system bus by securely and electrically detaching a part being an exchange object before the module is physically inserted/extracted. SOLUTION: Bus switches 120A and 120B are connected to bus switch control parts 121A and 121B which on/off-change over the switches and a system bus 100. Connection/detachment timing detection parts 122A and 122B detect timing when the other module connected to the system bus 100 does not malfunction even if it receives noise occurring at the time of the electric connection/ detachment of the bus switches 120A and 120B when the bus connection/ detachment request command 123, the voltage abnormality 125 and the clock abnormality of the module 130 occur. Then, effect is transmitted to the switch control parts 121A and 121B. Furthermore, a function for outputting the extraction permission signal 124 of the module 130 after the bus switches 120A and 120B are turned off is provided.

2. 发明专利

DE69718129T2 未知
公开(公告)号：DE69718129T2
公开(公告)日：2003-10-23
申请号：DE69718129
申请日：1997-10-27
申请人： HITACHI LTD
发明人： KANEKAWA NOBUYASU , YAMAGUCHI SHINICHIRO , MIYAZAKI NAOTO , KASUYA NAOHIRO , KAJIGAYA KAZUHIKO , MIYAZAKI YOSHIHIRO
IPC分类号： G05B9/03 , G06F11/00 , G06F11/16 , G06F11/18

3. 发明专利

DE69718129D1 未知
公开(公告)号：DE69718129D1
公开(公告)日：2003-02-06
申请号：DE69718129
申请日：1997-10-27
申请人： HITACHI LTD
发明人： KANEKAWA NOBUYASU , YAMAGUCHI SHINICHIRO , MIYAZAKI NAOTO , KASUYA NAOHIRO , KAJIGAYA KAZUHIKO , MIYAZAKI YOSHIHIRO
IPC分类号： G05B9/03 , G06F11/00 , G06F11/16 , G06F11/18

4. 发明专利

DE69911992T2 未知
公开(公告)号：DE69911992T2
公开(公告)日：2004-07-22
申请号：DE69911992
申请日：1999-07-16
申请人： HITACHI LTD
发明人： TAKEHARA TAKESHI , YAMAGUCHI SHINICHIRO , MIYAZAKI NAOTO , FUJIWARA MICHIO
IPC分类号： G05B9/02 , C09D5/36 , G05B23/02 , G06F11/30

5. 发明专利

DE69737573T2 未知
公开(公告)号：DE69737573T2
公开(公告)日：2008-03-06
申请号：DE69737573
申请日：1997-10-27
申请人： HITACHI LTD
发明人： KANEKAWA NOBUYASU , YAMAGUCHI SHINICHIRO , MIYAZAKI NAOTO , KASUYA NAOHIRO , KAJIGAYA KAZUHIKO , MIYAZAKI YOSHIHIRO
IPC分类号： G06F11/18 , G05B9/03 , G06F11/00 , G06F11/16

6. 发明专利

DE69737573D1 未知
公开(公告)号：DE69737573D1
公开(公告)日：2007-05-16
申请号：DE69737573
申请日：1997-10-27
申请人： HITACHI LTD
发明人： KANEKAWA NOBUYASU , YAMAGUCHI SHINICHIRO , MIYAZAKI NAOTO , KASUYA NAOHIRO , KAJIGAYA KAZUHIKO , MIYAZAKI YOSHIHIRO
IPC分类号： G06F11/18 , G05B9/03 , G06F11/00 , G06F11/16

7. 发明专利

DE69911992D1 未知
公开(公告)号：DE69911992D1
公开(公告)日：2003-11-13
申请号：DE69911992
申请日：1999-07-16
申请人： HITACHI LTD
发明人： TAKEHARA TAKESHI , YAMAGUCHI SHINICHIRO , MIYAZAKI NAOTO , FUJIWARA MICHIO
IPC分类号： G05B9/02 , C09D5/36 , G05B23/02 , G06F11/30

8. 发明公开

EP1132788A4 FAIL-SAFE CONTROLLER 有权
标题翻译： FEHLERSICHERE STEUERUNG
公开(公告)号：EP1132788A4
公开(公告)日：2001-10-04
申请号：EP99929892
申请日：1999-07-16
申请人： HITACHI LTD
发明人： TAKEHARA TAKESHI , YAMAGUCHI SHINICHIRO , MIYAZAKI NAOTO , FUJIWARA MICHIO
IPC分类号： G05B9/02 , G05B23/02 , G06F11/00 , G06F11/30
CPC分类号： G05B9/02
摘要： A fail-safe controller used for easily write and change an arithmetic operation program and improving the productivity of a system. A fail-safe controller (1) includes a control arithmetic unit (10) and an output unit (11). The control arithmetic unit (10) receives a state input (3) of a controlled system, performs arithmetic operations, and outputs the results of arithmetic operation as an arithmetic operation output (12). The output unit (11) has a timer (110), an alternating signal output section (111), and an output monitoring section (112). The output unit (11) converts the arithmetic operation output (12) from the control arithmetic unit (10) to an alternating signal asynchronously with the arithmetic operation of the control arithmetic unit (10) by use of a timer interruption (113) and monitors the output signal (114) from the alternating signal output section (111) so as to control the output/stop of a control output (2). The control arithmetic operation unit (10) outputs a control cycle start trigger (13) and feeds it to the alternating signal output section (111) and the output monitoring section (112).
摘要翻译：故障安全控制器用于轻松写入和更改算术运算程序，并提高系统的生产力。故障安全控制器（1）包括控制算术单元（10）和输出单元（11）。控制运算单元（10）接收受控系统的状态输入（3），执行算术运算，并且输出算术运算的结果作为算术运算输出（12）。输出部（11）具有计时器（110），交变信号输出部（111）以及输出监视部（112）。输出单元（11）通过使用定时器中断（113）与控制算术单元（10）的算术运算异步地将来自控制算术单元（10）的算术运算输出（12）转换为交变信号，并且监视来自交变信号输出部分（111）的输出信号（114），以便控制控制输出（2）的输出/停止。控制算术运算单元（10）输出控制周期开始触发（13）并将其馈送到交变信号输出部分（111）和输出监视部分（112）。

9. 发明专利

JPH10214207A INFORMATION PROCESSING SYSTEM 失效
公开(公告)号：JPH10214207A
公开(公告)日：1998-08-11
申请号：JP1622597
申请日：1997-01-30
申请人： HITACHI LTD
发明人： MIYAZAKI NAOTO , YAMAGUCHI SHINICHIRO , KANEKAWA NOBUYASU , KASUYA NAOHIRO
IPC分类号： G06F11/30 , G06F13/00
摘要： PROBLEM TO BE SOLVED: To surely detect an error caused by asynchronously generated noises or the like by checking the normality of address on a system bus during a period, in which the address is valid, asynchronously with a bus clock. SOLUTION: An address monitor part 17-1 is composed of high level set registers 34-1 and 35-1 and an incorrect address transition register 37-1. When asynchronous noises are generated during an address period, both the high level set registers 34-1 and 35-1 are set and the incorrect address transition register 37-1 is set so that an error detecting signal 26-1 can be asserted. Then, the error is reported to each central processing unit by an error reporting circuit, fault processing is performed and the incorrect address transition register 37-1 can be reset by a reset register 1 to be executed at the time of fault processing. Thus, at the address monitor part 17-1, the error can be detected asynchronously with the operating clock.

10. 发明专利

JPH10133900A REDUNDANT SYSTEM 失效
公开(公告)号：JPH10133900A
公开(公告)日：1998-05-22
申请号：JP28639096
申请日：1996-10-29
申请人： HITACHI LTD
发明人： KANEKAWA NOBUYASU , YAMAGUCHI SHINICHIRO , MIYAZAKI NAOTO , KASUYA NAOHIRO
IPC分类号： G06F11/16 , G06F11/18 , G06F11/22
摘要： PROBLEM TO BE SOLVED: To facilitate the test of a final output circuit and to make it possible to find a failure in its early stages by providing an output interface circuit for modules with a register for outputting written data from all modules and a register for outputting data only from its corresponding module and neglecting other modules. SOLUTION: Redundant modules 11 to 1n are respectively provided with output interfaces 21 to 2n and generate respective outputs 31 to 3n. The outputs 31 to 3n are inputted to the final output circuit 4. When any one of the modules 11 to 1n can not generate a normal output due to a fault, the circuit 4 can select a normal output and continue normal operation. Different outputs 31 to 3n can be obtained in every module while allowing the modules 11 to 1n to synchronously execute the same instruction and a test pattern for operation check can be given to the final output circuit 4.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式