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1. 发明专利

JP2010161416A Electronic device 审中-公开
标题翻译：电子设备
公开(公告)号：JP2010161416A
公开(公告)日：2010-07-22
申请号：JP2010088669
申请日：2010-04-07
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KIKUCHI HIROSHI , NAKAZATO NORIO , ANDO HIDEKO , SUGA TAKU , ISOMURA SATORU , KUBO TAKASHI , SASAKI HIROYASU , FUKUHARA MASANORI , TANAKA TADAYOSHI , NOSE FUJIAKI
IPC分类号： H01L23/12 , H01P3/08
CPC分类号： H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To improve quality of high-frequency characteristics of a semiconductor device and an electronic device. SOLUTION: A high-frequency signal from a tape-like line portion 40 having a surface-layer lead 40g and surface-layer GND leads 40h on both sides thereof is input directly to a semiconductor chip through a signal surface-layer portion of a package substrate and further a solder bump electrode, or on the contrary a high-frequency signal from the semiconductor chip is output to the outside through the tape-like line portion 40, and the high-frequency signals can be transmitted through only all microstrip lines of a surface layer of the package substrate, so that the high-frequency signals can be transmitted not through a via etc., but through only the microstrip lines. Consequently, the high-frequency signals can be transmitted without any loss in frequency characteristics, and loss in high-frequency transmission is reduced to transmit high-frequency signals of high quality. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提高半导体器件和电子器件的高频特性的质量。解决方案：具有表面层引线40g和表面层GND两端的导通40h的带状线部分40的高频信号通过信号表面层部分直接输入到半导体芯片的封装基板和另外的焊料凸块电极，或者相反，来自半导体芯片的高频信号通过带状线部分40输出到外部，并且高频信号可以仅通过全部微带线，使得高频信号不能通过通孔等而仅通过微带线传输。因此，可以在没有频率特性的任何损失的情况下传输高频信号，并且降低高频传输中的损耗以传输高质量的高频信号。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2007235149A Semiconductor device and electronic device 审中-公开
标题翻译：半导体器件和电子器件
公开(公告)号：JP2007235149A
公开(公告)日：2007-09-13
申请号：JP2007096464
申请日：2007-04-02
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KIKUCHI HIROSHI , NAKAZATO NORIO , ANDO HIDEKO , SUGA TAKU , ISOMURA SATORU , KUBO TAKASHI , SASAKI HIROYASU , FUKUHARA MASANORI , TANAKA TADAYOSHI , NOSE FUJIAKI
IPC分类号： H01L23/12 , H01P3/08 , H01P5/08
CPC分类号： H01L2224/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/09701 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To transmit a high frequency signal without degrading frequency characteristics, and to transmit the high frequency signal of high quality with less loss in high frequency transmission. SOLUTION: The high frequency signal from a tape-shaped line part 40 comprising a surface signal lead 40g and surface GND leads 40h arranged on both sides thereof is inputted directly to a semiconductor chip via surface wiring for signal of a package substrate and further transmitted through a solder bump electrode, or in an opposite direction, the high frequency signal from the semiconductor chip is outputted to the external part via the tape-shaped line part 40. By transmitting the high frequency signal only with all micro strip lines of the surface layer of a package board in this way, the high frequency signal is transmitted only with the micro strip line of the surface layer not through a via, etc. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：在不降低频率特性的情况下发送高频信号，并且在高频率传输中以较少的损耗发送高质量的高频信号。解决方案：包括表面信号引线40g和布置在其两侧的表面GND引线40h的带状线部分40的高频信号通过用于封装基板信号的表面布线直接输入到半导体芯片，进一步透过焊料凸点电极或相反的方向，来自半导体芯片的高频信号通过带状线部分40被输出到外部部分。通过仅将高频信号传输到所有的微带线以这种方式，封装板的表面层，只有表面层的微带线不通过通孔等传输高频信号。（C）2007，JPO＆INPIT

3. 发明专利

JP2004153179A Semiconductor device and electronic device 有权
公开(公告)号：JP2004153179A
公开(公告)日：2004-05-27
申请号：JP2002318936
申请日：2002-10-31
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KIKUCHI HIROSHI , NAKAZATO NORIO , ANDO HIDEKO , SUGA TAKU , ISOMURA SATORU , KUBO TAKASHI , SASAKI HIROYASU , FUKUHARA MASANORI , TANAKA TADAYOSHI , NOSE FUJIAKI
IPC分类号： H01L23/12 , H01P3/08 , H01P5/08
CPC分类号： H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To improve high frequency characteristics by reducing transmission loss of high frequency, by transmitting a high frequency signal via a transmission line part connected to a surface layer wiring of a wiring board. SOLUTION: The high frequency signal from a tape-shaped line part 40 comprising a surface signal lead 40g and surface GND leads 40h arranged on both sides thereof is inputted directly to a semiconductor chip via surface wiring for signal of a package substrate and further transmitted through a solder bump electrode, or on the contrary the high frequency signal from the semiconductor chip is outputted to the external part via the tape-shaped line part 40. By transmitting the high frequency signal only with all micro strip lines of the surface layer of a package board in this way, the high frequency signal is transmitted only with the micro strip line of the surface layer not through a via, etc. Consequently the high frequency signal is transmitted without loss of frequency characteristics, and the high frequency signal of high quality is transmitted with less loss in high frequency transmission. COPYRIGHT: (C)2004,JPO

4. 发明专利

JP2005291999A Strain gauge mounted with chip with radio function 审中-公开
标题翻译：应变片用无线电功能安装在芯片上
公开(公告)号：JP2005291999A
公开(公告)日：2005-10-20
申请号：JP2004109167
申请日：2004-04-01
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TANAKA TADAYOSHI , OTA HIROYUKI , SUMIKAWA TAKASHI , KUMAGAI YUKIHIRO
IPC分类号： G01B7/16 , G08C17/00
摘要： PROBLEM TO BE SOLVED: To realize a strain gauge mounted with a chip with radio functions, capable of executing accurately a deformation condition of a large structure and building, and a deformation condition under rotation of a high-speed rotary structure, without requiring complicated wiring handling. SOLUTION: This strain gauge is provided with a strain sensitive gauge part 1, a radio transmission antenna 4, and the chip 3 with the radio functions for radio-transmitting a strain value of the object detected by the strain-sensitive gauge part 1 via the antenna part 4. Since deformation information of the measuring object is transmitted by radio waves, the deformation condition of the large structure, and the deformation condition under the rotation of the high-speed rotary structure are executed accurately, without requiring the complicated wiring handling. The strain gauges having the chip 3 with the radio functions are provided in a plurality of portions of the structure, such as a bridge; the deformation information of the structure is obtained from the plurality of portions; a deformation amount and a deformation portion under vibration is compared with a deformation amount and a deformation portion under no vibration; and safety confirmation of the structure, prediction of strength lowering thereof and the like are carried out by analysis therein. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了实现安装有具有无线功能的芯片的应变仪，能够精确地执行大型结构和建筑物的变形状态以及高速旋转结构的旋转下的变形状态，而没有需要复杂的接线处理。解决方案：该应变仪设有应变敏感测量部件1，无线电传输天线4和具有射频功能的芯片3，用于无线电传输由应变敏感测量部件检测到的物体的应变值由于测量对象的变形信息通过无线电波发送，因此能够精确地执行大型结构的变形状态和高速旋转体的旋转下的变形状态，而不需要复杂的接线处理。具有无线电功能的芯片3的应变仪设置在诸如桥的结构的多个部分中; 从多个部分获得结构的变形信息; 将变形量和振动下的变形部与无振动的变形量和变形部进行比较; 通过分析进行结构的安全确认，强度降低的预测等。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2004342690A Semiconductor chip, method of manufacturing the same, semiconductor device, and method of manufacturing the same 有权
公开(公告)号：JP2004342690A
公开(公告)日：2004-12-02
申请号：JP2003134810
申请日：2003-05-13
申请人： Hitachi Ltd , Mitsubishi Electric Corp , Rohm Co Ltd , ローム株式会社 , 三菱電機株式会社 , 株式会社日立製作所
发明人： TANIDA KAZUMA , NEMOTO YOSHIHIKO , TANAKA TADAYOSHI
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/60 , H01L21/768 , H01L23/12 , H01L23/31 , H01L23/48 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L25/50 , H01L21/76898 , H01L23/3128 , H01L23/481 , H01L24/11 , H01L24/48 , H01L25/0657 , H01L2224/02372 , H01L2224/06181 , H01L2224/13025 , H01L2224/13099 , H01L2224/14181 , H01L2224/16145 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06586 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01049 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2224/45099
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor chip having through electrodes and high rigidity, and to provide a method of manufacturing the chip. SOLUTION: The semiconductor chip 1 contains a semiconductor substrate 2 of about 100 μm in thickness. A functional element 3 having a plurality of electrodes is formed on the surface of the substrate 2. Through holes 4 are formed through the substrate 2 in the thickness direction on the lateral sides of the functional element 3. In the through holes 4, the areas shallower than about 70 μm from the front surface side of the substrate 2 are filled up with front surface-side through electrodes 10A which are electrically connected to the functional element 3. In the through holes 4, in addition, the areas shallower than about 30 μm from the rear surface side of the semiconductor substrate 2 are filled up with rear surface-side through electrodes 10B. The front and the rear surface-side electrodes 10A and 10B form through electrodes 10 constituting the conducting routes between the front and the rear surface sides of the semiconductor substrate 2. COPYRIGHT: (C)2005,JPO&NCIPI

6. 发明专利

JP2003318363A Salient electrode bonded type semiconductor device and method of manufacturing the same 有权
标题翻译：耐电极接合型半导体器件及其制造方法
公开(公告)号：JP2003318363A
公开(公告)日：2003-11-07
申请号：JP2002125032
申请日：2002-04-25
申请人： Hitachi Ltd , Sharp Corp , シャープ株式会社 , 株式会社日立製作所
发明人： SATOU TOMOTOSHI , TANAKA TADAYOSHI
IPC分类号： H01L25/18 , H01L21/60 , H01L25/065 , H01L25/07
CPC分类号： H01L2224/16145 , H01L2224/45144 , H01L2924/01067 , H01L2924/01078 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To narrower a pitch of salient electrodes and suppress a connection failure of the salient electrodes due to strain, in a structure wherein there is a resin layer between semiconductor chips whose salient electrodes are bonded to each other. SOLUTION: The lower LSI chip 1 and the upper LSI chip 3 are bonded to each other with the salient electrodes 2 and 4 facing each other, and there is the resin layer between the LSI chips 1 and 2. The salient electrodes 2 and 4 are solid-state bonded. Assuming H1 is the height of the salient electrode 2, H2 is the height of the salient electrode 4, and H(=H1+H2) is the total height of a bonded salient electrode 7, H1, H2 and H0 satisfy the formula: H1 COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：为了缩小突起电极的间距并抑制由于应变引起的突出电极的连接故障，在其显着电极彼此接合的半导体芯片之间存在树脂层的结构中。解决方案：下部LSI芯片1和上部LSI芯片3彼此接合，凸极电极2和4彼此面对，并且在LSI芯片1和2之间存在树脂层。凸极电极2 和4是固态键合。假设H1是突出电极2的高度，H2是突出电极4的高度，H（= H1 + H2）是接合的突出电极7，H1，H2和H0的总高度，满足公式：H1

7. 发明专利

JP2003289122A Ball-grid-array type semiconductor device 审中-公开
标题翻译：球形阵列型半导体器件
公开(公告)号：JP2003289122A
公开(公告)日：2003-10-10
申请号：JP2003123531
申请日：2003-04-28
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YAGUCHI AKIHIRO , HARUTA AKIRA , ICHITANI MASAHIRO , TANAKA TADAYOSHI
IPC分类号： H01L23/12
CPC分类号： H01L2224/48091 , H01L2224/73265 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To realize a highly reliable BGA-type semiconductor device by suppressing the disconnection of conductive wiring and breakage of an external terminal. SOLUTION: Respective insulating films 3 covering respective lands 2b are separated from each other, and a dummy wiring 10 in addition to conductive wiring 2 connected to the lands 2 is projected from a side face 3b of the insulating film 3 covering the lands 2b. Thus, it is possible to increase the rate of wiring materials whose rigidity is large inside the insulating film 3, and to strengthen the constraint of the thermal deformation of the insulating film 3 itself by the dummy wiring 10. Also, it is possible to suppress the peeling of the side face 3b of the insulating film by the conductive wiring 2 and the dummy wiring 10, and to reduce the increase of the thermal deformation quantity of the insulating film 3 due to the generation of the peeling of the side face 3b. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：通过抑制导电布线的断开和外部端子的断裂来实现高可靠性的BGA型半导体器件。解决方案：覆盖相应焊盘2b的各绝缘膜3彼此分离，并且除了连接到焊盘2的导电布线2之外的虚设布线10从覆盖该焊盘的绝缘膜3的侧面3b突出 2b。因此，能够提高绝缘膜3内部的刚性大的布线材料的使用率，并且通过虚设布线10来加强绝缘膜3本身的热变形的约束。另外，也可以抑制通过导电布线2和虚拟布线10剥离绝缘膜的侧面3b，并且由于产生侧面3b的剥离而减少绝缘膜3的热变形量的增加。版权所有（C）2004，JPO

8. 发明专利

JP2003302318A Method for indicating resin material 有权
标题翻译：表征材料的方法
公开(公告)号：JP2003302318A
公开(公告)日：2003-10-24
申请号：JP2003136678
申请日：2003-05-15
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： NISHIMURA ASAO , TANAKA TADAYOSHI , HIROSE BATSU
IPC分类号： G01N19/04 , G01N1/28 , G01N3/06 , G01N3/24
摘要： PROBLEM TO BE SOLVED: To provide a method for measuring bond strength of a resin material, which separates true bond strength from residual stress thereby accurately and easily measuring universal bond strength independent of the size or shape of a test piece.
SOLUTION: In the method, a peel point is disposed partially between a resin 2 and a material to be bonded 3, and two loads P
1 , P
2 are applied in different directions respectively so that shearing stresses τ
1 , τ
2 act on an adhesive interface 4 in directions opposite to each other, thereby obtaining the true bond strength from apparent peel progression strength in respective cases.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种用于测量树脂材料的粘结强度的方法，其将真正的粘合强度与残余应力分开，从而精确且容易地测量与测试件的尺寸或形状无关的通用粘合强度。解决方案：在该方法中，剥离点部分地设置在树脂2和待接合材料3之间，并且两个载荷P 1 P 2 分别施加在剪切应力τ 1 上，τ 2 在粘合界面4上彼此相反的方向上作用，从而获得表观剥离的真实粘结强度各种情况下的进展强度。版权所有（C）2004，JPO

9. 发明专利

JP2000315707A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2000315707A
公开(公告)日：2000-11-14
申请号：JP12259399
申请日：1999-04-28
申请人： HITACHI LTD
发明人： TERASAKI TAKESHI , MIURA HIDEO , KOJIMA KIYOMI , YAGUCHI AKIHIRO , TANAKA TADAYOSHI
IPC分类号： H01L21/60
摘要： PROBLEM TO BE SOLVED: To accomplish a highly reliable semiconductor device on which the fatigue life of a solder bump can be extended. SOLUTION: The diameter of the area equal to the area of the part, which comes in contact with the pad 9 or the pad 10 of a lead-free solder bump 7, is set as A size and the diameter of the sphere of the cubic volume equal to the cubic volume of the lead-free solder bump 7 is set as B size. In this case, when the A size of the solder bump 7 is formed in the size which is 0.8 to 1.1 times of the B size, the contact surface of the solder bump 7 and the pads 9 and 10 is increased, and the intensity of junction interface is increased. Also, in proportion to the A-size becoming larger, it becomes cylindrical shape, the regidity of the solder bump 7 itself becomes higher, and the amount of thermal deformation added to the solder bump 7 becomes small.

10. 发明专利

JP2000106257A SOCKET FOR INSPECTING SEMICONDUCTOR ELEMENT, SEMICONDUCTOR DEVICE, MANUFACTURE OF THE SEMICONDUCTOR DEVICE, AND METHOD FOR INSPECTING THE SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2000106257A
公开(公告)日：2000-04-11
申请号：JP27551298
申请日：1998-09-29
申请人： HITACHI LTD
发明人： TANAKA TADAYOSHI , OTA HIROYUKI , ANJO ICHIRO , ARIMA HIDEO , HASEBE AKIO , YAMAMOTO KENICHI
IPC分类号： H01R33/76 , G01R1/04 , H01L23/32 , H01R33/94 , H05K3/32
摘要： PROBLEM TO BE SOLVED: To provide a socket for inspecting a semiconductor element which is refined and given high density, capable of accurately inspecting the semiconductor device, while absorbing the variations in height between the adjacent external projection electrodes of an IC. SOLUTION: Electrode pads 7 are formed on a tape circuit 2, in such a way as to correspond to the positions of the solder bumps 6 of an IC 5. The tape circuit 2 is electrically connected to mother sockets 4 with a plurality of pins formed on the peripheral part of the tape circuit 2. At the IC mounting part of the tape circuit 2 where the electrode pads 7 are formed, an elastomer sheet 1 is placed between the mother sockets 4 and the tape circuit 2, and cut grooves 3 are formed in a grid shape on the surface of the sheet 1 making contact with the tape circuit 2, with the center parts of the electrode pads 7 almost coinciding with the intersections of the grooves 3. Therefore, the parts of the sheet 1 defined by the grooves 3 can independently absorb pressures from the solder bumps 6 and are seldom affected by variations, if any, in height among the solder bumps 6 to surely bring the solder bumps 6 into contact with the electrode pads 7.

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