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1. 发明专利

JP2003309459A Design method for logic circuit and semiconductor integrated circuit with logic circuit 审中-公开
标题翻译：具有逻辑电路的逻辑电路和半导体集成电路的设计方法
公开(公告)号：JP2003309459A
公开(公告)日：2003-10-31
申请号：JP2002114324
申请日：2002-04-17
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SATO MASAYUKI , SHIMIZU ISAO
IPC分类号： H01L21/822 , H01L21/82 , H01L27/04 , H03K19/00 , H03K19/0175
摘要： PROBLEM TO BE SOLVED: To provide a technique for configuring a logic circuit including a sequence circuit with a wired logic circuit mainly employing wired logics so as to employ a low voltage power supply for a semiconductor logic integrated circuit. SOLUTION: A signal latch circuit such as a flip-flop circuit is configured by the wired logics and the entire logic circuit including both a combination circuit and a sequence circuit is configured by wired logic circuits mainly employing wired logics. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种用于配置包括具有主要采用有线逻辑的布线逻辑电路的序列电路以用于半导体逻辑集成电路的低电压电源的逻辑电路的技术。解决方案：诸如触发电路的信号锁存电路由有线逻辑构成，包括组合电路和序列电路的整个逻辑电路由主要采用有线逻辑的有线逻辑电路构成。版权所有（C）2004，JPO

2. 发明专利

JP2003066123A Test method, test apparatus and method for constructing test apparatus 审中-公开
标题翻译：测试方法，测试装置和构造测试装置的方法
公开(公告)号：JP2003066123A
公开(公告)日：2003-03-05
申请号：JP2001251779
申请日：2001-08-22
申请人： Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： SATO MASAYUKI , WAKAMATSU HIROKI
IPC分类号： G01R31/3183 , G01R31/28 , G01R31/317 , G06F11/22 , G06F17/50
摘要： PROBLEM TO BE SOLVED: To provide a technology capable of constructing a tester for semiconductor device suitable to respective programs described in a tester language while reducing the required test cost. SOLUTION: One apparatus is constituted so as to be changeable into a plurality of testers of different architecture, e.g. a logic tester capable of inspecting a logical circuit including a combination logic effectively or a memory tester capable of inspecting a memory circuit effectively. The apparatus is changed by selecting any one of the plurality of changeable testers and an object to be tested is tested using the changed apparatus.
摘要翻译：要解决的问题：提供能够构建适合于在测试语言中描述的各个程序的半导体器件的测试器的技术，同时降低所需的测试成本。解决方案：一个装置被构造成可以变化成多个不同架构的测试器，例如，能够有效地检查包括组合逻辑的逻辑电路的逻辑测试器或能够有效地检查存储器电路的存储器测试器。通过选择多个可更换的测试仪中的任一个来改变设备，并且使用改变的设备来测试被测试对象。

3. 发明专利

JP2002374165A Semiconductor integrated circuit device and manufacturing method therefor 审中-公开
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：JP2002374165A
公开(公告)日：2002-12-26
申请号：JP2001178037
申请日：2001-06-13
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SATO MASAYUKI , ADACHI HIROYUKI , OKAMOTO YOSHIHIKO
IPC分类号： H01L27/04 , H01L21/82 , H01L21/822 , H03K19/173 , H03K19/177
摘要： PROBLEM TO BE SOLVED: To solve the problem in a conventional FPGA(field programmable gate array) of a logic capable of being mounted, being unable to be increased satisfactorily in scale, because a variable wiring circuit is comparatively large in scale.
SOLUTION: As connection switching means (P1-P18), provided on an intersecting point of each wiring of a wiring group (VLA, LA), arranged in a grid like form between variable logic circuits(VLC), program elements capable of setting conduction/non-conduction between the wirings are used.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题为了解决能够安装的逻辑的常规FPGA（现场可编程门阵列）中的问题，由于可变布线电路规模比较大，不能令人满意地增加规模。解决方案：作为连接切换装置（P1-P18），设置在布线组（VLA，LA）的每个布线的交叉点上，以可变逻辑电路（VLC）之间的格子形状布置，能够设置导通 /使用布线之间的非导通。

4. 发明专利

JP2008049306A Apparatus for mixing gas 审中-公开
标题翻译：混合气体装置
公开(公告)号：JP2008049306A
公开(公告)日：2008-03-06
申请号：JP2006229996
申请日：2006-08-28
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： MATSUMOTO TAKEHIRO , SATO MASAYUKI , KOWATARI TAKEHIKO
IPC分类号： B01F5/00 , B01F3/02 , F01N3/08
摘要： PROBLEM TO BE SOLVED: To solve such a problem that the size of a system becomes larger or the output of the system is decreased since a main conduit of a long section is required or several devices are arranged in the main conduit to cause a pressure loss in a fluid when two fluids are mixed almost uniformly with each other.
SOLUTION: An auxiliary conduit is arranged through which an additional gas is made to pass and an outlet of the auxiliary conduit is arranged to be opened to the vicinity of the center of the main conduit through which a main gas is made to pass. A plate for dispersing the additional gas in the radial direction or a frustum-like structure, the cross-sectional area of which is made larger as the cross section near the auxiliary conduit is parted from the auxiliary conduit, is arranged in the vicinity of the center of the main conduit just after the outlet of the auxiliary conduit. A whirling member having a plurality of stator blades or rotor blades for forming a whirling flow in a current of the main gas is arranged for promoting the mixing of the additional gas with the main gas.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了解决由于需要长段的主管道或者在主管道中布置多个设备而导致系统尺寸变大或者系统的输出减小的问题，导致当两种流体彼此几乎均匀地混合时，流体中的压力损失。
解决方案：配置辅助导管，附加气体通过该辅助导管通过，并且辅助导管的出口被布置成向主导管的中心附近开放，主气体通过该导管通过。用于将附加气体分散在径向方向上的板或平截头体状结构，当辅助导管附近的横截面与辅助导管分离时，截面积更大的横截面积被设置在主导管的中心位于辅助导管出口之后。布置有用于在主气体的电流中形成旋转流的多个定子叶片或转子叶片的旋转构件，用于促进附加气体与主气体的混合。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2003270305A Test method for semiconductor integrated circuit and transaction method 审中-公开
标题翻译：半导体集成电路和交易方法的测试方法
公开(公告)号：JP2003270305A
公开(公告)日：2003-09-25
申请号：JP2002073962
申请日：2002-03-18
申请人： Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： SATO MASAYUKI , OGAWA KATSUMI
IPC分类号： G01R31/317 , G06Q50/00 , G06Q50/04 , G06F17/60
CPC分类号： Y02P90/30
摘要： PROBLEM TO BE SOLVED: To provide a test method allowing an efficient and low-cost testing of a semiconductor device by selecting the most suitable tester among a plurality of testers with different architectures, and allowing easy correction of a test program, thus reducing a total development period. SOLUTION: The test program is prepared using a statement-type or operation-description-type language not regulated by the architecture of the tester as a common tester language. For each description of the test program, whether executable or not is judged with a plurality of testers prepared in advance. Based on the judgment results, the tester with the lowest testing cost is selected among ones capable of executing every description. The test is performed with the selected tester by converting the test program into a program executable by that tester. COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：为了提供一种测试方法，通过在具有不同体系结构的多个测试器中选择最合适的测试器，并且允许容易地校正测试程序，从而对半导体器件进行有效且低成本的测试，因此减少总体发展时期。
解决方案：测试程序是使用语言类型或操作描述类型语言编写的，该语言不受测试器体系结构的限制，作为常见的测试语言。对于测试程序的每个描述，是否可以使用预先准备的多个测试器来判断是否可执行。根据判断结果，选择能够执行每个描述的测试人员的测试成本最低。通过将测试程序转换成可由该测试人员执行的程序，通过选定的测试仪进行测试。版权所有（C）2003，JPO

6. 发明专利

JP2002057152A MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002057152A
公开(公告)日：2002-02-22
申请号：JP2000242238
申请日：2000-08-10
申请人： HITACHI LTD
发明人： ISHIDA TAKASHI , SATO MASAYUKI , HIROKAWA JUN , HORIUCHI MITSUAKI
IPC分类号： H01L23/52 , H01L21/314 , H01L21/3205 , H01L21/60
摘要： PROBLEM TO BE SOLVED: To provide a technique which can improve humidity resistance of a semiconductor device. SOLUTION: After a metallic layer 8a, which constitutes a part of a foundation metal BLM for a CCB bump, is processed by using a resist pattern 13 as a mask, a hydrophobic fluoride layer 12 is formed by plasma processing using fluorine gas in a surface of a PIQ film 9b while leaving the resist pattern 13. Thereby, it is possible to prevent water and humidity out of circumference from permeating into the PIQ film 9b.

7. 发明专利

JP2001210685A TEST SYSTEM AND METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2001210685A
公开(公告)日：2001-08-03
申请号：JP2000264193
申请日：2000-08-31
申请人： HITACHI LTD
发明人： SHIMIZU ISAO , SATO MASAYUKI , FUKIAGE HIROSHI
IPC分类号： G01R1/06 , G01R31/28 , G01R31/30 , G01R31/3183 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To shorten extremely long test time of a test in wafer stage using a prober, where individual semiconductor chips are tested sequentially in conventional IC inspection, in which inspection is made both in a wafer stage and in a packaged stage. SOLUTION: A test without using a tester can be made, by constructing test circuits on a probe card or on a wafer in which semiconductor chips to be tested are formed and by electrically connecting the test circuits respectively to the semiconductor chips to be tested for performing the test. In addition, by conducting test in wafer stage in an aging apparatus, it is possible to simplify or omit the test, after being packaged.

8. 发明专利

JP2000164667A MANUFACTURE OF INSPECTION SYSTEM, ANALYZING UNIT, AND ELECTRONIC DEVICE 失效
公开(公告)号：JP2000164667A
公开(公告)日：2000-06-16
申请号：JP2000010131
申请日：2000-01-14
申请人： HITACHI LTD
发明人： ISHIHARA KAZUKO , ISHIKAWA SEIJI , SHIMOSHA SADAO , NAKAZATO JUN , MATSUOKA KAZUHIKO , MIYAMOTO YOSHIYUKI , NARUSHIMA MASACHIKA , MIYAZAKI ISAO , SHIGYO YOSHIHARU , SATO MASAYUKI , OSHIMA TAKAYUKI , HASHIMOTO TAIZO
IPC分类号： G01R31/28 , G06F11/22 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To cope with a higher integration of a semiconductor, to perform analysis with nigh measurement accuracy, to provide an easy-to-use user interface for easier analysis, and also efficiently perform compression of analyzed data. SOLUTION: An FB analysis system 105, an inspection data analyzing system 101, and a tester are provided with an LSI design information 107 for data analysis provided as well. Its failure information, analysis data, or inspection condition, are displayed on a display device, using a multiple-windows. At data compression of the analyzed data, storage mode is made different from each other, according as to a mode where a defective bit takes place.

9. 发明专利

JPH11354576A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH11354576A
公开(公告)日：1999-12-24
申请号：JP16160998
申请日：1998-06-10
申请人： HITACHI LTD
发明人： SAITO TOSHIO , SATO MASAYUKI , ISHIDA TAKASHI
IPC分类号： H01L21/60 , H01L21/603
摘要： PROBLEM TO BE SOLVED: To set a connection part to be thin, to reduce cost and to improve connection reliability, in a semiconductor device executing flip chip connection. SOLUTION: Chip side gold electrode layers 2a arranged by connecting them to the pads 1a of a semiconductor chip 1, a chip supporting substrate 3 where substrate side gold electrode layers 2b are formed, Au-Si adhesion layers 2c, which are arranged between the chip side gold electrode layers 2a on the semiconductor chip 1 and the substrate side gold electrode layers 2b on the chip supporting substrate 3, and execute Au-Si eutectic junction with the chip side gold electrode layers 2a and the substrate side gold electrode layers 2b at the time of executing flip chip connection, a sealing part sealing the semiconductor chip 1 and the connection part 2 and a plurality of pin members 5, are installed. The chip side gold electrode layers 2a, the substrate side gold electrode layer 2b and the Au-Si adhesion layers 2c between them are arranged. Thus, flip chip connection is executed by low temperature heat press contact.

10. 发明专利

JPH06275696A ANALYZING SYSTEM FOR SEMICONDUCTOR DEFECT AND COMPRESSING METHOD FOR ANALYSIS DATA 失效
公开(公告)号：JPH06275696A
公开(公告)日：1994-09-30
申请号：JP4400693
申请日：1993-03-04
申请人： HITACHI LTD
发明人： ISHIHARA KAZUKO , ISHIKAWA SEIJI , SHIMOSHA SADAO , NAKAZATO JUN , MATSUOKA KAZUHIKO , MIYAMOTO YOSHIYUKI , NARUSHIMA MASACHIKA , MIYAZAKI ISAO , SHIGYO YOSHIHARU , SATO MASAYUKI , OSHIMA TAKAYUKI , HASHIMOTO TAIZO
IPC分类号： G11C29/00 , G11C29/40 , H01L21/66
摘要： PURPOSE:To facilitate an analysis and to efficiently compress analysis data by analyzing with high measuring accuracy corresponding to high integration of a semiconductor and providing a user interface to be easily used in a semicon ductor defect analyzing system. CONSTITUTION:The semiconductor defect analyzing system comprises an FB analyzing system 105, an inspecting data analyzing system 101, a tester, and an LSI designing information 107 for data analysis. A display device displays defect information, analysis data or inspecting conditions in multi-windows. Further, at the time of compressing the analysis data, a storage mode is differentiated according to a mode for generating defective bits.

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