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1. 发明专利

JPH04225252A METHOD AND APPARATUS FOR INSPECTING SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH04225252A
公开(公告)日：1992-08-14
申请号：JP41453290
申请日：1990-12-26
申请人： HITACHI LTD
发明人： OGINO MASAYOSHI , SHIGYO YOSHIHARU , TSUKAGOSHI MASAKI , SATO MASAYUKI , OSHIMA TAKAYUKI
IPC分类号： H01L21/66 , H01L21/82 , H01L21/822 , H01L27/04
摘要： PURPOSE:To visually recognize an actual concrete position in a semiconductor device of a defective cell by an operator and to accurately and rapidly dispose the cell of a desired position by simulatively displaying the position of the cell in simulation images of a cell group. CONSTITUTION:Simulation images of a cell group are displayed on a cell group image display unit 8. Position informations of a foreign matter and a defect stored in an auxiliary storage device 3 are called through a host CPU. Information for displaying the simulation images of the matter and the defect is formed, and supplied to the display unit 8. Thus, in the unit 8, a defect simulation image is superposed on a cell simulation image, a defective cell simulation image to be displayed. In this case, the cell group simulation image, the defective cell simulation image and the foreign matter defect simulation image can stepwisely be enlarged.

2. 发明专利

JPH06181244A METHOD AND APPARATUS FOR INSPECTION OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH06181244A
公开(公告)日：1994-06-28
申请号：JP35306992
申请日：1992-12-11
申请人： HITACHI LTD
发明人： SHIGYO YOSHIHARU , MIYAMOTO YOSHIYUKI , OSHIMA TAKAYUKI
IPC分类号： H01L21/66 , H01L21/82
摘要： PURPOSE:To reduce time for inspection by converting a position information based on a logic adress arrangement of the first and last failure cells regarding a failure cell group into a position information formed by a substantial adress arrangement based on a simple layout information. CONSTITUTION:A means 21 for compressing defective cell position information compresses a position information on a failure cell group in which at least 2 continue on the same line and the same row into only position information on the first and last defective cells. Meanwhile, a simple layout information generating device 5 generates simple layout information according to the information on the origin of arrangement, the information on the position of cells from the origin, and the information on the direction of arrangement of cells out of the layout information on a semiconductor device. In a defective cell position information converting means 7, the position information based on logic adress arrangement of the first and last defective cells is converted into position information based substantial adress arrangement based on the simple layout information. Next, a defective cell automatic arrangement means 12 arranges the first and last defective cells within a visual field of a detective cell observing device 13 automatically.

3. 发明专利

JP2000164667A MANUFACTURE OF INSPECTION SYSTEM, ANALYZING UNIT, AND ELECTRONIC DEVICE 失效
公开(公告)号：JP2000164667A
公开(公告)日：2000-06-16
申请号：JP2000010131
申请日：2000-01-14
申请人： HITACHI LTD
发明人： ISHIHARA KAZUKO , ISHIKAWA SEIJI , SHIMOSHA SADAO , NAKAZATO JUN , MATSUOKA KAZUHIKO , MIYAMOTO YOSHIYUKI , NARUSHIMA MASACHIKA , MIYAZAKI ISAO , SHIGYO YOSHIHARU , SATO MASAYUKI , OSHIMA TAKAYUKI , HASHIMOTO TAIZO
IPC分类号： G01R31/28 , G06F11/22 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To cope with a higher integration of a semiconductor, to perform analysis with nigh measurement accuracy, to provide an easy-to-use user interface for easier analysis, and also efficiently perform compression of analyzed data. SOLUTION: An FB analysis system 105, an inspection data analyzing system 101, and a tester are provided with an LSI design information 107 for data analysis provided as well. Its failure information, analysis data, or inspection condition, are displayed on a display device, using a multiple-windows. At data compression of the analyzed data, storage mode is made different from each other, according as to a mode where a defective bit takes place.

4. 发明专利

JPH06275696A ANALYZING SYSTEM FOR SEMICONDUCTOR DEFECT AND COMPRESSING METHOD FOR ANALYSIS DATA 失效
公开(公告)号：JPH06275696A
公开(公告)日：1994-09-30
申请号：JP4400693
申请日：1993-03-04
申请人： HITACHI LTD
发明人： ISHIHARA KAZUKO , ISHIKAWA SEIJI , SHIMOSHA SADAO , NAKAZATO JUN , MATSUOKA KAZUHIKO , MIYAMOTO YOSHIYUKI , NARUSHIMA MASACHIKA , MIYAZAKI ISAO , SHIGYO YOSHIHARU , SATO MASAYUKI , OSHIMA TAKAYUKI , HASHIMOTO TAIZO
IPC分类号： G11C29/00 , G11C29/40 , H01L21/66
摘要： PURPOSE:To facilitate an analysis and to efficiently compress analysis data by analyzing with high measuring accuracy corresponding to high integration of a semiconductor and providing a user interface to be easily used in a semicon ductor defect analyzing system. CONSTITUTION:The semiconductor defect analyzing system comprises an FB analyzing system 105, an inspecting data analyzing system 101, a tester, and an LSI designing information 107 for data analysis. A display device displays defect information, analysis data or inspecting conditions in multi-windows. Further, at the time of compressing the analysis data, a storage mode is differentiated according to a mode for generating defective bits.

5. 发明专利

JPH04289477A ANALYZING SYSTEM FOR DEFECT OF SEMICONDUCTOR MEMORY AND DEFECTIVE CELL DISPLAY OUTPUT METHOD 失效
公开(公告)号：JPH04289477A
公开(公告)日：1992-10-14
申请号：JP7851891
申请日：1991-03-18
申请人： HITACHI LTD
发明人： SATO MASAYUKI , OSHIMA TAKAYUKI
IPC分类号： G01R31/28 , G11C29/00 , G11C29/44
摘要： PURPOSE:To make the defect analysis of semiconductor memory easy by converting origin information, position information and pitch information in accordance with the layout of a semiconductor memory to real address matrix information nearly allied to the geometrical cell layout on a semiconductor chip and displaying the defective cell. CONSTITUTION:The electrical characteristics of a semiconductor memory completed in trial fabrication or make up process is inspected with a memory tester 21 to detect the position of a defective memory cell and the position information of each is stored in a logic address space in a defective memory cell position information part 22. A real address matrix converter 23 specfies the origin mark being the standard of memory cell which is a part of the layout information read out of an auxilially memory of a host CPU, the memory origin to specify the position of each memory and position information of a defective memory cell based on its arrangement direction and stores them. The converter 23 displays and defective memory cel at the position corresponding to the real address space on a screen of a display terminal.

6. 发明专利

JP2000164666A MANUFACTURE OF INSPECTION SYSTEM, ANALYZING UNIT, AND ELECTRONIC DEVICE 失效
公开(公告)号：JP2000164666A
公开(公告)日：2000-06-16
申请号：JP2000010130
申请日：2000-01-14
申请人： HITACHI LTD
发明人： ISHIHARA KAZUKO , ISHIKAWA SEIJI , SHIMOSHA SADAO , NAKAZATO JUN , MATSUOKA KAZUHIKO , MIYAMOTO YOSHIYUKI , NARUSHIMA MASACHIKA , MIYAZAKI ISAO , SHIGYO YOSHIHARU , SATO MASAYUKI , OSHIMA TAKAYUKI , HASHIMOTO TAIZO
IPC分类号： G01R31/28 , G06F11/22 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To cope with a higher integration of a semiconductor, to perform analysis with high measurement accuracy, to provide an easy-to-use user interface for easier analysis, and also efficiently perform compression of analyzed data. SOLUTION: An FB analysis system 105, an inspection data analyzing system 101, and a tester are provided with an LSI design information 107 for data analysis provided as well. Its failure information, analysis data, or inspection conditions are displayed on a display device using multiple windows. At data compression of the analyzed data, storage mode is made different from each other by a mode where defective bits take place.

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