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1. 发明专利

JP2006295748A Content reproducing apparatus 审中-公开
标题翻译：内容再现设备
公开(公告)号：JP2006295748A
公开(公告)日：2006-10-26
申请号：JP2005116397
申请日：2005-04-14
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YUASA TAKASHI , FUJII YUKIO , TANAKA KAZUHIKO , HOSOKI KOJI , NAKADA KEIMEI , EHAMA MASAKAZU
IPC分类号： H04N5/44 , H04N5/60 , H04N7/173
CPC分类号： G06F1/3203 , G06F1/3265 , Y02D10/153
摘要： PROBLEM TO BE SOLVED: To provide a content reproducing apparatus which realizes power saving by performing power source control corresponding to input contents.
SOLUTION: While utilizing a result of investigating whether or not video contents are included by analyzing additional information of inputted contents by a PSI analysis section 6 or investigating whether or not a video signal is included in the input contents by a signal detection section 7, in a content reproducing apparatus 19, a video information detection section 8 detects whether or not video information is included in the input contents and outputs a result of the detection to a power source control section 9. If the video information is included in the input contents, the power source control section 9 supplies power to a display 18 to power on the display but if video information is not included, the power source control section 9 stops supplying power to the display 17 to power off the display.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供一种通过对应于输入内容执行电源控制来实现省电的内容再现装置。解决方案：利用通过PSI分析部分6分析输入内容的附加信息来检查视频内容是否包含的结果，或者通过信号检测部分检查视频信号是否包括在输入内容中的结果如图7所示，在内容再现装置19中，视频信息检测部分8检测输入内容中是否包括视频信息，并将检测结果输出到电源控制部分9.如果视频信息包括在输入内容，电源控制部9向显示器18供电以对显示器通电，但是如果不包括视频信息，则电源控制部9停止向显示器17供电以断开显示。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2005209060A System including address generation apparatus and address generation apparatus 审中-公开
标题翻译：包括地址生成装置和地址生成装置的系统
公开(公告)号：JP2005209060A
公开(公告)日：2005-08-04
申请号：JP2004016737
申请日：2004-01-26
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： NAKADA KEIMEI , FUJII YUKIO , TANAKA KAZUHIKO , HOSOKI KOJI , EHAMA MASAKAZU
IPC分类号： G06F12/02 , G06F9/345 , G06F12/06 , G06F13/28 , G09G3/20 , G09G5/37 , G09G5/39
CPC分类号： G06F9/345 , G09G3/20 , G09G2340/0407
摘要： PROBLEM TO BE SOLVED: To provide a system including an address generation apparatus capable of generating addresses necessary for resolution conversion or the like of display data by an adder and a counter without using a multiplexer which is disadvantageous in terms of a mount area or operation speed when mounted in an integration circuit, and to provide the address generation apparatus.
SOLUTION: A part for selecting some values out of a plurality of values prepared for calculating the next address to add them and a part for generating a signal to control selection of values to be added are prepared. A plurality of counters are prepared for the part for controlling the selection of values to be added and, by these values of the counter, values to be added are selected. The address generation apparatus is incorporated into a DMA control unit, a memory access control unit, a display control unit and the like, and the resolution conversion or the like is performed.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种包括地址产生装置的系统，其能够通过加法器和计数器产生显示数据的分辨率转换等所需的地址，而不使用在安装面积方面不利的多路复用器或操作速度，并提供地址产生装置。
解决方案：准备用于从准备用于计算下一个地址以添加它们的多个值中选择一些值的部分和用于生成用于控制要添加的值的选择的信号的部分。准备多个计数器用于控制要添加的值的选择，并且通过计数器的这些值来选择要添加的值。地址生成装置被结合到DMA控制单元，存储器访问控制单元，显示控制单元等中，并且执行分辨率转换等。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2005165588A Microprocessor 审中-公开
标题翻译：微处理器
公开(公告)号：JP2005165588A
公开(公告)日：2005-06-23
申请号：JP2003402557
申请日：2003-12-02
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： EHAMA MASAKAZU , HOSOKI KOJI , TANAKA KAZUHIKO , NAKADA KEIMEI , TOJIMA SHIGEKI
IPC分类号： G06F15/78 , H04N7/24 , H04N19/00 , H04N19/42 , H04N19/423 , H04N19/436
摘要： PROBLEM TO BE SOLVED: To provide a microprocessor equipped with a data transfer engine for enabling a processor core to automatically perform data transfer to be performed the next without performing the polling of the end of the processing of a peripheral circuit.
SOLUTION: A data transfer engine is provided with a processing status register, and the processing status register is provided with bits which are made rewritable by a peripheral circuit, and assigned to each peripheral circuit when data processing ends. This data transfer engine monitors the value of the processing status register instead of a processor core, and starts itself when all the processing ends, and starts the assigned data transfer.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种配备有数据传输引擎的微处理器，用于使处理器核心能够自动执行下一次执行的数据传输，而不执行对外围电路的处理结束的轮询。解决方案：数据传输引擎设置有处理状态寄存器，并且处理状态寄存器被提供有由外围电路可重写的位，并且当数据处理结束时被分配给每个外围电路。该数据传输引擎监视处理状态寄存器的值而不是处理器内核，并且在所有处理结束时自动启动，并启动分配的数据传输。版权所有（C）2005，JPO＆NCIPI

4. 发明专利

JP2005157783A Processor system equipped with accelerator capable of reserving execution 审中-公开
标题翻译：具有加速器的处理器系统可保存执行
公开(公告)号：JP2005157783A
公开(公告)日：2005-06-16
申请号：JP2003395995
申请日：2003-11-26
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HOSOKI KOJI , FUJII YUKIO , TANAKA KAZUHIKO , NAKADA KEIMEI , EHAMA MASAKAZU
IPC分类号： G06F12/08 , G06F9/38 , G06F9/50 , G06F15/78 , G06F17/50 , G06T1/20 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/50 , H04N19/503 , H04N19/61 , H04N19/625 , H04N19/91 , H04N7/32
CPC分类号： G06T1/20 , G06F9/5083 , G06F15/7864 , H04N19/42
摘要： PROBLEM TO BE SOLVED: To provide a processor system capable of image processing at high speed. SOLUTION: The processor system is equipped with a CPU 1 that is connected to an accelerator 3 and issues a reservation of an activation request to the accelerator, and the accelerator 3 having a counter of the number of requests that counts the number of requests issued by the CPU, and a counter of the number of terminations that counts the number of terminated processings. The accelerator 3 is made to activate itself when the value of the counter of the number of requests is larger than the value of the counter of the number of terminated processings. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供能够高速图像处理的处理器系统。解决方案：处理器系统配备有CPU 1，其连接到加速器3并向加速器发出激活请求的预约，加速器3具有计数器的数量的计数器的数量由CPU发出的请求，以及计数终止处理次数的终止数的计数器。当请求数量的计数器的值大于终止处理次数的计数器的值时，使加速器3自身激活。版权所有（C）2005，JPO＆NCIPI

5. 发明专利

JP2004317536A Display control system 审中-公开
标题翻译：显示控制系统
公开(公告)号：JP2004317536A
公开(公告)日：2004-11-11
申请号：JP2003107194
申请日：2003-04-11
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： NAKADA KEIMEI , HOSOKI KOJI , TANAKA KAZUHIKO
IPC分类号： G06F12/00 , G06F12/02 , G09G5/00 , G09G5/377
摘要： PROBLEM TO BE SOLVED: To efficiently access a memory by suppressing the storage capacity of a buffer for temporarily storing display data read out of the memory.
SOLUTION: When gaining access to a plurality of frame memory areas, display data is read out of each frame memory area according to prescribed order in the unit of small amount of display data. At this time, the order is specified so that the data amount proportional to the average data amount required for each one pixel of the display data stored in the frame memory may be read from each frame memory area. Also, when gaining access to the memory in such order, address conversion is performed before accessing the memory so that specifying of row address can be omitted.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：通过抑制用于临时存储从存储器读出的显示数据的缓冲器的存储容量来有效地访问存储器。解决方案：当获取对多个帧存储区域的访问时，根据规定的顺序以少量的显示数据为单位从每个帧存储区域读出显示数据。此时，指定顺序，使得可以从每个帧存储区域读取与存储在帧存储器中的显示数据的每个像素所需的平均数据量成比例的数据量。此外，当以这样的顺序访问存储器时，在访问存储器之前执行地址转换，以便可以省略对行地址的指定。版权所有（C）2005，JPO＆NCIPI

6. 发明专利

JP2003295848A Display controller 有权
标题翻译：显示控制器
公开(公告)号：JP2003295848A
公开(公告)日：2003-10-15
申请号：JP2002100733
申请日：2002-04-03
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： NAKADA KEIMEI , FUJIKAWA YOSHIBUMI , KUROKAWA YOSHITAKE , SAKAO HIDEKI , TANAKA KAZUHIKO
IPC分类号： G09G5/00
摘要： PROBLEM TO BE SOLVED: To reduce the quantity of data required for state control and the transfer quantity of the data while retaining the degree of freedom of the control state of a display controller.
SOLUTION: State control information being the data required for the state control is divided into a plurality of groups and the state control information is made omittable by the group units in state transition timing. The state control information is transferred to a data distributor 362 from an FIFO buffer 311. The next state is written in a state holder A364 and a state holder B365 according to the groups in the state transition timing detected by means of an update decision device 316. The contents in the state holders corresponding to the omitted group are retained in the previous state form or is returned to a fixed state.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：为了在保持显示控制器的控制状态的自由度的同时减少状态控制所需的数据量和数据的传送量。解决方案：作为状态控制所需的数据的状态控制信息被分成多个组，并且状态控制信息在状态转换定时中被组单元所忽略。状态控制信息从FIFO缓冲器311传送到数据分配器36.下一状态根据通过更新判定装置316检测的状态转移定时中的组被写入状态保持器A364和状态保持器B365 对应于省略组的状态持有人的内容保留在先前的状态或返回到固定状态。版权所有（C）2004，JPO

7. 发明专利

JP2008003708A Image processing engine and image processing system including the same 有权
标题翻译：图像处理发动机和图像处理系统，包括它们
公开(公告)号：JP2008003708A
公开(公告)日：2008-01-10
申请号：JP2006170382
申请日：2006-06-20
申请人： Hitachi Ltd , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社日立製作所
发明人： HOSOKI KOJI , EHAMA MASAKAZU , NAKADA KEIMEI , IWATA KENICHI , MOCHIZUKI SEIJI , YUASA TAKASHI , KOBAYASHI YUKIFUMI , SHIBAYAMA TETSUYA , UEDA KOJI , NOBORI MASAKI
IPC分类号： G06F9/34 , G06F9/38 , G06F15/80
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30036 , G06F9/30087
摘要： PROBLEM TO BE SOLVED: To resolve the problem that the power consumption is increased by occurrence of an instruction memory read at every cycle because of supply of one or more instructions in one cycle with respect to instructions issued from a CPU and is increased by the occurrence of simultaneous access of instruction memories at every cycle because of the increase in number of instruction memories for a multiprocessor configuration.
SOLUTION: A means is provided which designates two-dimensional source registers and destination registers to an operand of an instruction, and an operation using a plurality of source registers is executed in a plurality of cycles to obtain a plurality of destinations. In an instruction to obtain destinations by using a plurality of source registers and consuming a plurality of cycles, a data rounding computing unit is connected to the last step of a pipeline. Furthermore, a plurality of CPUs are connected in series and use shared instruction memories in common. In this case, a field for controlling synchronization between adjacent CPUs is provided in an instruction operand of each CPU, whereby synchronization control is performed.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：解决由于在每个周期读取指令存储器而产生的功耗增加的问题，因为相对于从CPU发出的指令在一个周期内提供一个或多个指令并增加由于多处理器配置的指令存储器数量的增加，在每个周期的同时存取指令存储器的发生。解决方案：提供一种将二维源寄存器和目标寄存器指定到指令的操作数的装置，并且以多个周期执行使用多个源寄存器的操作以获得多个目的地。在通过使用多个源寄存器并消耗多个周期来获取目的地的指令中，数据舍入计算单元连接到流水线的最后一个步骤。此外，多个CPU串联连接并共同使用共享指令存储器。在这种情况下，在每个CPU的指令操作数中提供用于控制相邻CPU之间的同步的字段，由此执行同步控制。版权所有（C）2008，JPO＆INPIT

8. 发明专利

JP2005339372A Direct memory access transfer control device, system using it, and debug support method and system therefor 审中-公开
标题翻译：直接存储器访问传输控制设备，使用它的系统以及调试支持方法和系统
公开(公告)号：JP2005339372A
公开(公告)日：2005-12-08
申请号：JP2004159808
申请日：2004-05-28
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： NAKADA KEIMEI , TANAKA KAZUHIKO , HOSOKI KOJI , TASHIRO TAKU
IPC分类号： G06F13/00
摘要： PROBLEM TO BE SOLVED: To analyze the past DMA transfer regardless of the presence of error. SOLUTION: A descriptor that is information showing a parameter necessary for DMA transfer is recorded as a log of transfer every time the parameter is read from the descriptor in transfer. Process identification information can be included in the log, and log collecting function can be validated for each channel. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：分析过去的DMA传输，无论是否存在错误。解决方案：每当从传送描述符中读取参数时，将显示DMA传输所必需的参数的描述符记录为传输日志。过程识别信息可以包含在日志中，日志收集功能可以对每个通道进行验证。版权所有（C）2006，JPO＆NCIPI

9. 发明专利

JP2010108207A Video display device 有权
标题翻译：视频显示设备
公开(公告)号：JP2010108207A
公开(公告)日：2010-05-13
申请号：JP2008279066
申请日：2008-10-30
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： NAKADA KEIMEI , CHIHARA NOBUHIRO , MUSHA YOSHINORI
IPC分类号： G06T1/00 , G06T3/40 , H04N1/387
摘要： PROBLEM TO BE SOLVED: To achieve two-dimensional display, and to reduce deterioration of quality in two-dimensionally displaying normal two-dimensional video content in a video display device for displaying stereoscopic video content using parallax. SOLUTION: A stereoscopic video display device based on right eye and right eye images includes; a resolution enhancement processing part for enhancing resolution from right eye and left eye images; an image input selection part for selecting either a resolution enhanced image by the resolution enhancement processing part or the right eye and left eye images; and a display device for performing the two-dimensional display and stereoscopic display of the video. In performing the resolution enhancement processing, the resolution enhancement processing part uses either the right eye image or the left eye image as a reference image, and performs processing for retrieving a section corresponding to the display position of the reference image from the other image, and retrieves a range which is wide in the left direction with respect to the right direction in using the left eye image as a reference, and retrieves a range which is wide in the right direction with respect to the left direction in using the right eye image as a reference for performing the retrieval processing. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了实现二维显示，并且在用于使用视差显示立体视频内容的视频显示装置中二维地显示正常的二维视频内容的质量的劣化。解决方案：基于右眼和右眼图像的立体视频显示装置包括：用于增强从右眼和左眼图像的分辨率的分辨率增强处理部分; 用于通过分辨率增强处理部分或右眼和左眼图像选择分辨率增强图像的图像输入选择部分; 以及用于执行视频的二维显示和立体显示的显示装置。在执行分辨率增强处理时，分辨率增强处理部分使用右眼图像或左眼图像作为参考图像，并且执行用于从另一图像中检索与参考图像的显示位置相对应的部分的处理，以及在使用左眼图像作为基准时，检索相对于右方向的左方向宽的范围，并且在使用右眼图像时检索相对于左方向的右方向宽的范围用于执行检索处理的参考。版权所有（C）2010，JPO＆INPIT

10. 发明专利

JP2009296080A Super-resolution image generation system 审中-公开
标题翻译：超分辨率图像生成系统
公开(公告)号：JP2009296080A
公开(公告)日：2009-12-17
申请号：JP2008145257
申请日：2008-06-03
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TANAKA KAZUHIKO , NAKADA KEIMEI
IPC分类号： H04N5/232 , H04N1/387 , H04N5/92
摘要： PROBLEM TO BE SOLVED: To solve the problem that required operation performance is sharply improved due to the increase of reference frames when enlarging images by super-resolution processing.
SOLUTION: A first intermediate super-resolution frame is generated from image data of a first image frame and a second image frame, a second intermediate super-resolution frame is generated from image data of the second image frame and a third image frame, and third motion vector information is generated from first motion vector information obtained when generating the first intermediate super-resolution frame and second motion vector information obtained when generating the second intermediate super-resolution frame. A final super-resolution frame is generated from the first intermediate super-resolution frame, the second intermediate super-resolution frame and the third motion vector information, and the super-resolution processing is hierarchically performed.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了解决当通过超分辨率处理放大图像时由于参考帧的增加而急剧改善所需操作性能的问题。解决方案：从第一图像帧和第二图像帧的图像数据生成第一中间超分辨率帧，从第二图像帧的图像数据和第三图像帧生成第二中间超分辨率帧并且当生成第一中间超分辨率帧时获得的第一运动矢量信息和当生成第二中间超分辨率帧时获得的第二运动矢量信息来生成第三运动矢量信息。从第一中间超分辨率帧，第二中间超分辨率帧和第三运动矢量信息生成最终的超分辨率帧，并且分级执行超分辨率处理。版权所有（C）2010，JPO＆INPIT

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