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1. 发明专利

JPS62131517A SEMICONDUCTOR MANUFACTURING DEVICE 失效
公开(公告)号：JPS62131517A
公开(公告)日：1987-06-13
申请号：JP27144785
申请日：1985-12-04
申请人： HITACHI LTD
发明人： URYU TAKESHI , ONO RYOICHI
IPC分类号： G03F7/40 , G03C5/00 , G03F7/00 , G03F7/30 , H01L21/027 , H01L21/30
摘要： PURPOSE:To perform the procedures such as development, far ultraviolet ray irradiation and baking process automatically by a method wherein a developing part developing photoresist film, a far ultraviolet ray irradiating part irradiating the photoresist film with far ultraviolet rays and a baking part baking the photoresist film are provided. CONSTITUTION:A movable cover 18 covering the periphery and lower part of a specimen table 15 is provided while a developer jetting nozzle 20 spraying wafer 6 on the spinner table 15 with developer such as organic alkali solution etc. as well as a cleanser jetting nozzle 21 spraying the wafer 6 with cleanser such as pure water etc. are provided in a development part 2. The wafer 6 loaded on a belt conveyer 22 is successively shifted to a far ultraviolet ray irradiating part 3, a baking part 4 and an unloader 5 to be irradiated with far ultraviolet ray at the part 3 for a few minutes. Besides, a heater 28 is provided on the ceiling in the furnace body 24 of baking part 4 to bake a positive type resist film on the surface of wafer 6 being shifted by the belt conveyer 22.

2. 发明专利

JPS63263720A ELECTRON BEAM LITHOGRAPHY EQUIPMENT 失效
公开(公告)号：JPS63263720A
公开(公告)日：1988-10-31
申请号：JP9734187
申请日：1987-04-22
申请人： HITACHI LTD
发明人： URYU TAKESHI , ONO RYOICHI
IPC分类号： H01L21/30 , H01L21/027
摘要： PURPOSE:To make it possible to conduct a positioning and a patterning in a highly precise manner by a method wherein two electron guns are prepared, and each electron gun is exclusively used for a patterning and a mask detection respectively. CONSTITUTION:The title electron beam lithography equipment with a patterning electron beam system 4 and a mask detecting electron beam system 5 which are independently operated. When a patterning operation is conducted on GaAs wafers, the electron beam of accelerated voltage of 30 KV is discharged, the electron beam of accelerated voltage of 15 KV is discharged when a mark- detecting operation is conducted, and the mark detecting and the patterning operations are conducted in parallel with each other. The patterning or the mark detecting operation can be conducted with the optimum accelerated voltage by exclusively using the electron guns 6 and 20 for the patterning 6 and the mark detection 20 respectively. As a result, the positioning and the patterning operations can be performed in a highly precise manner.

3. 发明专利

JPS62131584A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62131584A
公开(公告)日：1987-06-13
申请号：JP27146585
申请日：1985-12-04
申请人： HITACHI LTD
发明人： MITANI KATSUHIKO , TAKAHASHI SUSUMU , OKAZAKI SHINJI , YANAGISAWA HIROSHI , ONO RYOICHI , URYU TAKESHI
IPC分类号： H01L21/28 , H01L21/338 , H01L29/80 , H01L29/812
摘要： PURPOSE:To form a minute electrode pattern simply by using a single resist layer, by coating a dielectric film on a substrate having stepped structure, and selectively performing anisotropic etching of a region including a step part. CONSTITUTION:In a GaAs crystal substrate 1, recess etching is performed. An SiO2 dielectric film 2 is applied on the substrate by a chemical vapor deposition method. Resist 3 is applied on the substrate. A hole is provided in the resist including a step part of the dielectric film 2. With the resist pattern as a mask, the dielectric thin film 2 undergoes reactive ion etching, and a metal electrode 4 is formed by a lift-off method. Thus a recess structure is provided, the length of a gate can be shortened and the distance between a source and a drain can be also shortened.

4. 发明专利

JPS61218174A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS61218174A
公开(公告)日：1986-09-27
申请号：JP5833085
申请日：1985-03-25
申请人： HITACHI LTD
发明人： URYU TAKESHI
IPC分类号： H01L29/812 , H01L21/338 , H01L29/80
摘要： PURPOSE:To obtain a Schottky barrier gate type FET having excellent high frequency characteristic with good reproducibility by etching widely to the midway of an ohmic contact layer as compared with a gate width, and then etching to a channel layer in the gate width. CONSTITUTION:An N-type channel layer 9 and an N type ohmic contact layer 10 are formed on the main surface of a wafer 7 made of a GaAs substrate. After a source electrode 1 and a drain electrode 2 are formed on the main surface of the wafer 7, with an insulating film 13 as a mask an ohmic contact layer 10 is etched to the midway in the width wider than a gate electrode forming region. Then, with an insulating film 15 as a mask the gate electrode forming region is etched to the surface layer of the layer 9. A gate electrode 3 is formed on the formed flat groove 16. Thus, a fine gate can be formed with good reproducibility, thereby obtaining a Schottky barrier gate FET having excellent high frequency characteristics.

5. 发明专利

JP2001267331A METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2001267331A
公开(公告)日：2001-09-28
申请号：JP2000071414
申请日：2000-03-15
申请人： HITACHI LTD
发明人： URYU TAKESHI
IPC分类号： H01L29/417 , H01L21/304 , H01L21/3205 , H01L21/338 , H01L23/52 , H01L27/095 , H01L29/778 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To readily form vias in a semiconductor substrate at a low cost. SOLUTION: In the manufacturing method for a semiconductor device, having semiconductor elements on a semiconductor substrate main surface, an light transmissive film is adhered to the semiconductor substrate main surface, the backside of the semiconductor substrate is polished to remove the film. According to this means, the film covering the semiconductor substrate main surface uses a low-cost film, allowing vias to be easily formed at a low cost, and the sued film is light transmissive, allowing the semiconductor substrate main surface to be observed with the film adhered. Thus the aligning, etc., is easy in forming the vias.

6. 发明专利

JPH02250335A MANUFACTURE OF SEMICONDUCTOR ELEMENT 失效
公开(公告)号：JPH02250335A
公开(公告)日：1990-10-08
申请号：JP7061589
申请日：1989-03-24
申请人： HITACHI LTD
发明人： KOBAYASHI MASAYOSHI , MIYASHITA ISAO , URYU TAKESHI , SHIMIZU SHUICHI
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/338 , H01L29/778 , H01L29/812
摘要： PURPOSE:To form an electrode such as a gate electrode of a T-sheped cross section without damaging an active layer and with good reproducibility by a method wherein a desired amount of an insulating film is removed, an opening part of a T-shaped cross section is formed and an electrode, with a structure of a T-shaped cross section, whose central part comes into contact with the active layer is formed by a lift-off method by utilizing an electron-beam resist film. CONSTITUTION:An insulating film 5 with which an active layer 2 is covered is formed in a desired depth by an anisotropic dry etching operation by making use of an electron-beam resist film 15 as a mask. After that, a desired thickness over a whole region in a surface-layer part of the electron-beam resist film 15 is removed by an isotropic dry etching operation; a T-shaped hollow is formed by a hollow of the insulating film 5 and by inside faces of the electron-beam resist film 15 placed on the insulating film 5. In addition, a prescribed depth of the insulating film 5 is removed by an anisotropic dry etching operation by making use of the electron-beam resist film 15 as a mask; a T-shaped opening part is formed; then, a gate electrode 6 is formed by a lift-off method. Thereby, the active layer is not damaged; a gate electrode of a T-shaped cross section can be formed with good reproducibility.

7. 发明专利

JPS63232329A MANUFACTURE OF SEMICONDUCTOR DEVICE AND ALIGNMENT MARK 失效
公开(公告)号：JPS63232329A
公开(公告)日：1988-09-28
申请号：JP6392287
申请日：1987-03-20
申请人： HITACHI LTD
发明人： URYU TAKESHI , ONO RYOICHI , YANAGISAWA HIROSHI
IPC分类号： H01L21/08 , G01B15/00 , H01L21/027 , H01L21/30
摘要： PURPOSE:To improve the accuracy of alignment by composing an alignment mark of high a density material which emits a large quantity of reflected electrons and secondary electrons. CONSTITUTION:In the manufacturing process of GaAs-MES-FET, alignment is performed before an electron beam lithography process for forming a gate with a dimension of 0.3 mum in such a manner that, when source and drain electrodes 17 and 18 made of Au system electrode material is formed by a lift-off method with an SiO2 film as a mask, an alignment mark 1 is formed with the Au system electrode material at the same time and then the alignment mark 1 is detected to correct the discrepancy of an electron beam lithography equipment and the electron beam lithography is carried out to form a pattern for forming the gate electrode. As the Au electrode material has Au, which is high density material, on its surface, it emits a large quantity of reflected electrons and secondary electrons when an electron beam is applied to the alignment mark 1 for detecting the position. Therefore, the edge of the mark 1 can be detected with a high precision by detecting those electrons and the detection can be more clarified by amplification of obtained signals.

8. 发明专利

JPS61125149A Manufacture of electronic device 失效
标题翻译：电子器件的制造
公开(公告)号：JPS61125149A
公开(公告)日：1986-06-12
申请号：JP24603284
申请日：1984-11-22
申请人： Hitachi Ltd
发明人： MATSUZAWA MANABU , OKUBO TOSHIO , URYU TAKESHI , KOBAYASHI MASAMICHI
IPC分类号： H01L29/78 , H01L21/3205 , H01L23/52
摘要： PURPOSE:To improve the accuracy of finishing of etching by forming a high melting-point metallic film body under the state, in which the film body occludes oxygen, onto a substrate, processing the film body to a required wiring pattern through dry etching and thermally treating it at 700 deg.C or higher. CONSTITUTION:A high-resistivity p type silicon layer 2 is shaped onto a low- resistivity p type silicon substrate 1, and a field oxide film is formed. The silicon layer 2 is exposed partially, and the surface of the substrate 1 is termally oxidized to shape a gate oxide film 3. A metallic molybdenum film 4 is formed onto the oxide film 3. A section not masked in the Mo film 4 is removed, and a Mo gate 4a is shaped. n type layers 7 are formed while using the Mo gate 4a and a peripheral field film 6 as masks. An inter-layer insulating film 8 is shaped onto the whole surface. The whole is annealed and treated in a N2 atmosphere at 900 deg.C. Al electrodes 9 brought into ohmic-contact with sourcedrain sections and an Al wiring 10 connected to the Mo gate are formed through Al evaporation and etching.
摘要翻译：目的：为了通过在薄膜体内吸附氧的状态下形成高熔点金属膜体来提高蚀刻精度，通过干蚀刻和热处理将膜体加工成所需的布线图案在700摄氏度以上处理。构成：将高电阻率p +型硅层2成形为低电阻率p +型硅衬底1，形成场氧化膜。硅层2被部分曝光，并且衬底1的表面被定期氧化以形成栅极氧化膜3.在氧化物膜3上形成金属钼膜4.去除Mo膜4中未被掩蔽的部分并且Mo门4a成形。在使用Mo门4a和外围场膜6作为掩模的同时形成n +型层7。层间绝缘膜8成形为整个表面。整个退火并在900℃的N 2气氛中进行处理。通过Al蒸发和蚀刻形成与源极区段欧姆接触的Al电极9和连接到Mo栅极的Al布线10。

9. 发明专利

JPS61120476A Semiconductor device and manufacture thereof 失效
标题翻译：半导体器件及其制造
公开(公告)号：JPS61120476A
公开(公告)日：1986-06-07
申请号：JP24062184
申请日：1984-11-16
申请人： Hitachi Ltd
发明人： SHIMIZU SHUICHI , URYU TAKESHI , ONO RYOICHI , YANAGI YOSHIKAZU , YUKIMOTO TOMIHISA
IPC分类号： H01L21/338 , H01L29/10 , H01L29/812
CPC分类号： H01L29/8128 , H01L29/1029
摘要： PURPOSE:To obtain an FET having excellent high frequency characteristics, by forming an implanted by layer having high impurity concentration on a semi-insulating substrate, dividing the implanted layer into a source region and a drain region by a groove, providing a low impurity concentration channel region having the same conducting type as those regions, and connecting those regions to the source and drain regions by heat treatment. CONSTITUTION:An n type layer 9 is formed on the surface of a semi-insulating GaAs substrate 8 by ion implantation. Etched parts 7 are provided on both sides of the layer, and the layer 9 is made to be an island shape. Then, the entire surface is covered by a first SiO2 film 11. A window is provided. Etching is performed and a groove 12 is provided. The layer 9 is divided into an ion implanted layer 13 for a source and an ion implanted layer 14 for a drain. An n type channel layer 15 is formed on the substrate 8 exposed in the groove 12. Thereafter, heat treatment is performed, and strain in the layers 13-15 is removed. The layer 15 is connected to the layers 13 and 14. The entire surface is covered by a second SiO2 film 16. A window corresponding to a channel layer 19 formed from the layer 15 is provided, and a gate electrode 3 is attached to the window.
摘要翻译：目的：为了获得具有优异的高频特性的FET，通过在半绝缘基板上形成具有高杂质浓度的注入层，通过沟槽将注入层划分为源区和漏区，提供低杂质浓度沟道区域与这些区域具有相同的导电类型，并且通过热处理将这些区域连接到源极和漏极区域。构成：通过离子注入在半绝缘GaAs衬底8的表面上形成n +型层9。蚀刻部7设置在层的两侧，层9形成为岛状。然后，整个表面被第一SiO 2膜11覆盖。提供一个窗口。进行蚀刻并设置凹槽12。层9被分为用于源的离子注入层13和用于漏极的离子注入层14。在凹槽12中露出的基板8上形成n型沟道层15.此后，进行热处理，并且去除层13-15中的应变。层15连接到层13和14。整个表面被第二SiO 2膜16覆盖。提供与由层15形成的沟道层19相对应的窗口，并且栅电极3附接到窗口。

10. 发明专利

JPH0382112A CHARGED PARTICLE BEAM LITHOGRAPHY AND DEVICE THEREFOR 失效
公开(公告)号：JPH0382112A
公开(公告)日：1991-04-08
申请号：JP21735189
申请日：1989-08-25
申请人： HITACHI LTD
发明人： URYU TAKESHI , YAMAGUCHI MICHIO
IPC分类号： H01L21/027
摘要： PURPOSE:To prevent generation of irregularity in pattern size after patterning by a method wherein, before a desired pattern is drawn by projecting a charged particle beam on a resist, the resist is baked in a vacuum. CONSTITUTION:As an accommodating chamber 15 is evacuated into a high vacuum state by a rotary vacuum pump 17 and a cryo-pump 16, the resist 2 coated on each wafer 1 is baked in a high vacuum atmosphere. The solvent and the low-molecular weight component contained in the resist 2 are evaporated completely by the baking in a high vacuum atmosphere. Accordingly, the generation of irregularity in sensitivity of the wafer 1 group can be restrained or suppressed. When an electron beam 8 is projected on the resist 2 of the wafer 1, which is positioned on and supported by a sample stand 13, while the electron beam 8 is being controlled in a patterning chamber 11, a desired circuit pattern can be drawn on the resist 2.

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