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1. 发明专利

JPS61120476A Semiconductor device and manufacture thereof 失效
标题翻译：半导体器件及其制造
公开(公告)号：JPS61120476A
公开(公告)日：1986-06-07
申请号：JP24062184
申请日：1984-11-16
申请人： Hitachi Ltd
发明人： SHIMIZU SHUICHI , URYU TAKESHI , ONO RYOICHI , YANAGI YOSHIKAZU , YUKIMOTO TOMIHISA
IPC分类号： H01L21/338 , H01L29/10 , H01L29/812
CPC分类号： H01L29/8128 , H01L29/1029
摘要： PURPOSE:To obtain an FET having excellent high frequency characteristics, by forming an implanted by layer having high impurity concentration on a semi-insulating substrate, dividing the implanted layer into a source region and a drain region by a groove, providing a low impurity concentration channel region having the same conducting type as those regions, and connecting those regions to the source and drain regions by heat treatment. CONSTITUTION:An n type layer 9 is formed on the surface of a semi-insulating GaAs substrate 8 by ion implantation. Etched parts 7 are provided on both sides of the layer, and the layer 9 is made to be an island shape. Then, the entire surface is covered by a first SiO2 film 11. A window is provided. Etching is performed and a groove 12 is provided. The layer 9 is divided into an ion implanted layer 13 for a source and an ion implanted layer 14 for a drain. An n type channel layer 15 is formed on the substrate 8 exposed in the groove 12. Thereafter, heat treatment is performed, and strain in the layers 13-15 is removed. The layer 15 is connected to the layers 13 and 14. The entire surface is covered by a second SiO2 film 16. A window corresponding to a channel layer 19 formed from the layer 15 is provided, and a gate electrode 3 is attached to the window.
摘要翻译：目的：为了获得具有优异的高频特性的FET，通过在半绝缘基板上形成具有高杂质浓度的注入层，通过沟槽将注入层划分为源区和漏区，提供低杂质浓度沟道区域与这些区域具有相同的导电类型，并且通过热处理将这些区域连接到源极和漏极区域。构成：通过离子注入在半绝缘GaAs衬底8的表面上形成n +型层9。蚀刻部7设置在层的两侧，层9形成为岛状。然后，整个表面被第一SiO 2膜11覆盖。提供一个窗口。进行蚀刻并设置凹槽12。层9被分为用于源的离子注入层13和用于漏极的离子注入层14。在凹槽12中露出的基板8上形成n型沟道层15.此后，进行热处理，并且去除层13-15中的应变。层15连接到层13和14。整个表面被第二SiO 2膜16覆盖。提供与由层15形成的沟道层19相对应的窗口，并且栅电极3附接到窗口。

2. 发明专利

JPS6220324A ELECTRONIC DEVICE FORMING SUBSTRATE AND MANUFACTURE OF ELECTRONIC DEVICE 失效
公开(公告)号：JPS6220324A
公开(公告)日：1987-01-28
申请号：JP15816785
申请日：1985-07-19
申请人： HITACHI LTD
发明人： KITAHARA TOSHIAKI , YUKIMOTO TOMIHISA , INABA KEIZO
IPC分类号： H01L29/812 , H01L21/304 , H01L21/338 , H01L29/80
摘要： PURPOSE:To reduce the defect density on the surface of a wafer by mirror- polishing the both surfaces of the wafer without working strain layer. CONSTITUTION:Since a small strain layer 7 still remains on the both main surfaces of a wafer when the both surfaces of the wafer are lapped with abra sive of grain size of #1200 to remove a cutting strain layer 6, if it is mirror- polished with ultrafine abrasive of #3000-4000 of grain size, the strain layers of the both surfaces are completely removed to become a mirror-polished surface 8. Doner impurity ions of Si or the like are implanted to one main surface of the wafer 1 which is mirror-finished on the both surfaces to form a layer 9. Then, an N-type active layer 2 is formed by actively annealing (700-800 deg.CX20min) in the state that a PSG film 10 is formed by a CVD method. The PSG film 10 is selectively removed by etching, source and drain electrodes and a gate electrode are then formed to complete a GaAs FET.

3. 发明专利

JPS61290714A MANUFACTURE OF COMPOUND SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS61290714A
公开(公告)日：1986-12-20
申请号：JP13185585
申请日：1985-06-19
申请人： HITACHI LTD
发明人： KITAHARA TOSHIAKI , YUKIMOTO TOMIHISA , INABA KEIZO
IPC分类号： H01L29/812 , H01L21/265 , H01L21/338 , H01L29/80
摘要： PURPOSE:To prevent the thermal strain produced in a semiconductor substrate due to a difference in thermal expansion coefficient between the substrate and a covering film provided for preventing the scattering of an impurity and to improve the yield of the product, by performing a heat treatment after forming the covering film on the substrate and removing a part of the covering film. CONSTITUTION:Ions of a donor impurity Si 6 are selectively implanted in one principal surface of a GaAs substrate 1. A covering film 7 of phosphorus or silicon oxide glass is then formed for preventing the scattering of the As. The portions of the film 7 not included in the regions where elements are to be formed (the film portions for separating the substrate) are removed both in the vertical and transverse directions, so that groves 9 are provided in those directions. The substrate 1 is thereafter heated and annealed to diffuse the Si, whereby N-type active layers 2 and N type diffused layers 3 for source and drain regions are formed. Consequently, any thermal strain caused by a difference in thermal expansion coefficient between the substrate 1 and the covering film 7 is absorbed by the grooves 9. Therefore, no strain is produced during the heat treatment and the yield of the products can be improved.

4. 发明专利

JPS62249489A COMPOUND SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62249489A
公开(公告)日：1987-10-30
申请号：JP9214686
申请日：1986-04-23
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD
发明人： KITAHARA TOSHIAKI , YASUDA TAKESHI , YANAGI YOSHIKAZU , SAKAMOTO KAZUMICHI , YUKIMOTO TOMIHISA
IPC分类号： H01L29/812 , H01L21/338 , H01L29/80 , H01L29/866
摘要： PURPOSE:To reduce lateral diffusion by a method wherein a p-n junction surface is laid along the direction which makes right angle with the direction to which the lateral diffusion of an impurity which determines p-type or n-type is small. CONSTITUTION:Not to speak of a back-to-back protective diode, the p-n junction surface of a p-n junction structure diode is laid along the direction which makes right angle with the direction to which the lateral diffusion of an impurity for forming the p-n junction is small. The orientation of each p-n junction surface of the back-to-back protective diode is so selected as to be the direction along a crystal direction which is parallel to the crystal face (0-1-1) of the orientation flat (OF) 4 of an wafer l if the crystal face of the main surface of the wafer 1 is (100). Therefore, when zinc is diffused to form the p-n junction of the protective diode, as the lateral diffusion of zinc is small, the distance between the p-n junction surface and an electrode provided on the n-type region becomes short and the ON resistance of the diode is reduced.

5. 发明专利

JPS61290772A MANUFACTURE OF COMPOUND SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS61290772A
公开(公告)日：1986-12-20
申请号：JP13185485
申请日：1985-06-19
申请人： HITACHI LTD
发明人： KITAHARA TOSHIAKI , YUKIMOTO TOMIHISA , INABA KEIZO
IPC分类号： H01L29/812 , H01L21/28 , H01L21/338 , H01L29/80 , H01L29/866
摘要： PURPOSE:To scale down a junction area and the shape of a junction, and to improve high-frequency characteristics and reliability by forming a junction section through an impurity diffusion method for shaping a junction diode to the surface of a substrate and removing the diffused surface section of the substrate. CONSTITUTION:An N type ion implantation layer 6 is formed onto a semi- insulating GaAs substrate 1. An N-type ion implantation layer 2 is shaped. An SiO2 film 9 is deposited, and annealed and treated to form each diffusion layer for N type layers 3, 6 and the N-type active layer 2. A window is bored to one part 10 of the SiO2 film on the diode side. Zn as an acceptor impurity is diffused from the window opening section to shape a P diffusion layer 7. SiO2 in the surface of the N type layer on the diode side is removed. An inden tation section 11 is formed by using a GaAs etching liquid thereby electrodes 4, 5 are shaped.

6. 发明专利

JPH1187345A COMPOUND SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH1187345A
公开(公告)日：1999-03-30
申请号：JP23565897
申请日：1997-09-01
申请人： HITACHI LTD
发明人： KUROKAWA ATSUSHI , YAMANE MASAO , YUKIMOTO TOMIHISA
IPC分类号： H01L21/768 , H01L21/318 , H01L21/338 , H01L23/522 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To improve moisture resistance, suppress characteristic fluctuation and improve reliability, by providing a water resistant insulating film which extends along a semiconductor substrate and covers an element forming region in the horizontal direction, and providing openings that penetrate the insulating film outside the element forming region. SOLUTION: The entire plane of an element forming region 2 is covered with a water resistant insulating film 8, and openings that penetrate the insulating film 8 are all provided outside the element forming region 2. Therefore, water infiltration to the element forming region 2 is suppressed and the moisture resistance of a semiconductor device is improved. It is also possible to improve the moisture resistance by forming an interlayer insulating film 5 or an interlayer insulating film 7 of silicon nitride. A part of the insulating film 8 that contacts with a semiconductor substrate 1 is provided at a slightly inner position from the edge of the semiconductor substrate 1, for preventing such part from being damaged even when chipping is generated at the edge in pellet cutting, etc.

7. 发明专利

JPH04303922A MOLECULAR BEAM CRYSTAL GROWTH APPARATUS 失效
公开(公告)号：JPH04303922A
公开(公告)日：1992-10-27
申请号：JP9367291
申请日：1991-03-29
申请人： HITACHI LTD
发明人： YUKIMOTO TOMIHISA , NAKADA HIROYUKI , TAKAHASHI NUSHITO , TAGAMI TOMONORI , TAMURA NAOYUKI
IPC分类号： C30B23/08 , H01L21/203
摘要： PURPOSE:To prevent an MBE growth layer from being contaminated with Mn at a molecular beam crystal growth apparatus. CONSTITUTION:At a molecular beam crystal growth apparatus, at least a protective part 24 at a shroud 23 for a K cell 18 for gallium use is formed of a high- melting-point metal material 25 whose melting point is at 1500 deg.C or higher. Even when the component of the high-melting-point metal material 25 has adhered to the K cell 23 for gallium use, it is possible to avoid that moleculaes for the high-melting-point metal material reach a wafer 15. As a result, it is possible to completely prevent the high-melting-point metal material 25 from being taken into an MBE growth layer as impurities.

8. 发明专利

JPS61269311A MANUFACTURE OF COMPOUND SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS61269311A
公开(公告)日：1986-11-28
申请号：JP11032185
申请日：1985-05-24
申请人： HITACHI LTD
发明人： KITAHARA TOSHIAKI , YUKIMOTO TOMIHISA , INABA KEIZO
IPC分类号： H01L29/812 , H01L21/265 , H01L21/338
摘要： PURPOSE:To prevent the occurrence of heat distortion by performing the heat- treatment for activation under the state where a film of a material is formed on the both main surfaces so as to prevent impurity from being released after impurity ions are implanted into a substrate. CONSTITUTION:Specified amount of Si is introduced onto one main surface of a GaAs wafer 1 with ion implantation to form a Si implantation layer 6. After films 7a and 7b of PSG is formed with CVD, activation annealing is performed for about 20min at 500-1,000 deg.C to form an n-type active layer 2, an n type diffusion layer 3 for source drain on the one main surface of the wafer 1. Then, the films 7a and 7b are removed, and a surface insulation layer 8 consisting of CVD.PSG is newly formed. A contact section is opened with photoresist technique. Then, source and drain electrode 4 and a gate electrode 5 are formed to complete a FET.

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