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1. 发明专利

DE3172722D1 METHOD OF FORMING A MICROSCOPIC PATTERN 未知
公开(公告)号：DE3172722D1
公开(公告)日：1985-11-28
申请号：DE3172722
申请日：1981-07-31
申请人： HITACHI LTD
发明人： MATSUZAWA TOSHIHARU , DOUTA KIKUO , IWAYANAGI TAKAO , YANAGISAWA HIROSHI
IPC分类号： C23F1/00 , G03F7/012 , G03F7/038 , G03F7/26 , H01L21/306 , G03F7/08
摘要： A negative photoresist (5) having bezene rings is irradiated with short-wavelength ultraviolet radiation. Because the benzene rings greatly absorb this radiation on developing a photoresist pattern is formed where sectional shape is an inverted trapezoid.An aluminum layer (4) is deposited, and is discontinuous because of the overhanging edges of the trapezoidal photoresist patterns. On removal of the photoresist, the layer (4) thereon is also lifted off, to leave an aluminum pattern of high precision without the troublesome steps which the lift-off process has heretofore entailed.

2. 发明专利

JPH04171732A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH04171732A
公开(公告)日：1992-06-18
申请号：JP29712790
申请日：1990-11-05
申请人： HITACHI LTD
发明人： MITANI KATSUHIKO , MASUDA HIROSHI , MOCHIZUKI KAZUHIRO , KUSANO CHUSHIRO , YANAGISAWA HIROSHI
IPC分类号： H01L21/285 , H01L21/28 , H01L21/338 , H01L29/80 , H01L29/812
摘要： PURPOSE:To improve controllability and reliability by forming an electrode of gate length corresponding to the film thickness of a germanium layer. CONSTITUTION:For example, an n type arsenic gallium layer 11, an n-type germanium layer 12, and an n type arsenic gallium layer 13 are piled up one after another on a semiinsulating arsenic gallium substrate 10. Next, after oxygen ions are injected to form a high resistance layer 14 in an element isolation region, mesa etching is performed. Then, an n-type germanium layer 12 exposed from the side wall of a formed recess is selectively coated with W films 15 to form gate electrodes. After the n type arsenic gallium layers 11, 13 are overlaid with source and drain electrodes 16, a passivation film and wirings are provided. This can provide extremely short gate electrodes with excellent controllability and uniformity and prevent strain and cracks of the channel zone because of successive pile-ups of semiconductor layers.

3. 发明专利

JPH03232971A DEVICE FOR VAPOR FORMATION OF THIN FILM 失效
公开(公告)号：JPH03232971A
公开(公告)日：1991-10-16
申请号：JP2854890
申请日：1990-02-09
申请人： HITACHI LTD
发明人： YANAGISAWA HIROSHI , MATSUBARA HIROKAZU
IPC分类号： C23C16/02 , C23C16/34 , C23C16/54 , H01L21/31
摘要： PURPOSE:To allow the continuous formation of thin films by a CVD method without absorbing moisture in insulating films of a coating type by providing a means for heating the samples in a predischarge chamber and a means for supplying ozone to the samples. CONSTITUTION:The insulating films of the coating type are first formed by an ordinary spin coating method on the planar samples 14 formed with semiconductor elements. The planar samples 14 are then imposed on a transporting mechanism 15 existing in the predischarge chamber 15 and while the samples are kept heated to 200 deg.C by lamps 18. The ozone generated by an ozone generator 16 is introduced through a nozzle 17 for uniformizing gaseous flow to the surfaces of the planar samples 14. This state is maintained for 20 minutes to bake the insulating films of the coating type. The supply of the ozone is then stopped, and after the inside of the predischarge chamber 11 is evacuated to a vacuum, the planar samples 14 are transported through a gate valve 13 by the transporting mechanism 15 into a plasma reaction chamber 12 where the thin films of SiNx are formed by the plasma CVD method. The formation of the plasma CVD films is possible without exposing the samples to the atm. air after the baking of the insulating films of the coating type.

4. 发明专利

JPS6261372A COUPLING METHOD OF GAAS LSI GATE AND OHMIC ELECTRODES 失效
公开(公告)号：JPS6261372A
公开(公告)日：1987-03-18
申请号：JP19940285
申请日：1985-09-11
申请人： HITACHI LTD
发明人： KODERA NOBUO , YANAGISAWA HIROSHI , MIYAZAKI MASARU , KAJITA SHINJI , TANAKA HIRONORI
IPC分类号： H01L29/812 , H01L21/28 , H01L21/338 , H01L21/768 , H01L23/522 , H01L29/80
摘要： PURPOSE:To reduce the layout area by using a contacting hole common for both gate and ohmic electrodes to simplify the coupling of the ohmic electrode with the gate electrode. CONSTITUTION:A Schottky barrier is formed by superposing a gate electrode 1 and an N-channel 2, and an ohmic electrode contact is formed by superposing an ohmic metal 4 on a high density N type layer 3 connected with the N- channel 2 and alloying them. A contacting hole 5 crossing over both the electrode 1 and the metal 4 is formed in an insulating film such as an SiO2 formed on the metals 1 and 4, and wiring metal 6 is disposed to completely cover the hole 5.

5. 发明专利

JPS61137371A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS61137371A
公开(公告)日：1986-06-25
申请号：JP25970184
申请日：1984-12-07
申请人： Hitachi Ltd
发明人： MORI MUTSUHIRO , YAO TSUTOMU , YANAGISAWA HIROSHI , MIYAZAKI MASARU
IPC分类号： H01L29/80 , H01L29/10
CPC分类号： H01L29/1066
摘要： PURPOSE:To obtain an SIT which has less leakage current between a gate and a source by forming a source region of an overhang structure by etching the upper layer of a substrate laminated with semiconductor layers of different carrier densities, and forming a gate region and a drain region at both sides with the source region as a mask. CONSTITUTION:An N type layer 100 and an N type layer 1d are laminated on an N type semiconductor substrate, not shown, etched to form an overhang structure to the halves of the layers 1d and 100 and a recess 10 at the side of the remaining overhang structure. Then, the side wall of the overhang structure is coated by an insulating film 30, and with the remaining overhang structure as a mask a P type gate region and a P type drain region 1c are formed by ion implanting. Then, an insulating film and an insulating film 31 of fast etching velocity on the regions are coated, and a film 31 is removed while removing a foreign material adhered onto the region. Then, a source electrode 22 is formed on the layer 1d, and a gate electrode 23 is formed on a gate region.
摘要翻译：目的：通过蚀刻层叠有不同载流子密度的半导体层的基板的上层，通过形成突出结构的源极区域来获得栅极和源极之间的漏电流较小的SIT，并形成栅极区域和漏极区域以源区域为掩模。构成：在N +型半导体衬底（未示出）上层压N +型层100和N +型层1d，以对层1d和100的一半进行蚀刻以形成突出结构，并且在其余悬垂结构侧的凹部10。然后，通过绝缘膜30涂覆悬伸结构的侧壁，以剩余的悬垂结构作为掩模，通过离子注入形成P型栅极区域和P型漏极区域1c。然后，涂覆在区域上具有快速蚀刻速度的绝缘膜和绝缘膜31，并且除去附着在该区域上的异物的膜31。然后，在层1d上形成源极22，在栅极区上形成栅电极23。

6. 发明专利

JPS6053457B2 失效
公开(公告)号：JPS6053457B2
公开(公告)日：1985-11-26
申请号：JP13897977
申请日：1977-11-21
申请人： HITACHI LTD
发明人： SHIMOMOTO TAIJI , IMAMURA YOSHINORI , YANAGISAWA HIROSHI , NARAOKA KYOTAKE , KONDO HIROYUKI
IPC分类号： G03F1/00 , G03F1/40 , G03F1/54 , H01L21/027 , H01L21/302

7. 发明专利

JPS6086829A APPLICATOR FOR PHOTO-RESIST 失效
公开(公告)号：JPS6086829A
公开(公告)日：1985-05-16
申请号：JP19425983
申请日：1983-10-19
申请人： HITACHI LTD
发明人： YANAGISAWA HIROSHI , KANEKO TADAO , KOBASHI TAKAHIRO , HASHIMOTO TETSUKAZU , OOHAYASHI HIDEHITO
IPC分类号： B05C11/08 , G03F7/16 , H01L21/027
摘要： PURPOSE:To treat the surface with excellent reproducibility in a short time by heating a sample before applying a photo-resist and exposing the sample in organic compound vapor. CONSTITUTION:A sample wafer is carried to a surface treating mechanism section by a carrying section 19, and loaded on a sample base 14. A reaction-chamber lower section 12 and a heating jig 15 are lifted, and the sample is shifted on the heating jig 15 while the reaction-chamber lower section 12 and a reaction-chamber upper section 13 are fast stuck, thus forming a hermetically sealed reaction chamber. A solenoid valve 111 is opened, and the reaction chamber is evacuated by using a pump 117. The solenoid valve 111 is closed, solenoid valves 112, 113 are opened, the vapor of an organic compound positioned in a bubbler 20 is introduced into the reaction chamber, and the sample is surface-treated. Lastly, the solenoid valve 112 is closed, the solenoid valve 111 is opened, and residual vapor in the reaction chamber is evacuated, thus completing treatment. Accordingly, adhesive properties between the surface of an element and a photo- resist can be improved with excellent reproducibility, and the time of processes can be shortened.

8. 发明专利

JPS6053028A FORMATION OF FINE PATTERN 失效
公开(公告)号：JPS6053028A
公开(公告)日：1985-03-26
申请号：JP16035283
申请日：1983-09-02
申请人： HITACHI LTD
发明人： MATSUZAWA TOSHIHARU , YANAGISAWA HIROSHI , SHIRAISHI HIROSHI , KADOTA KAZUYA
IPC分类号： H01L21/3205 , H01L21/28 , H01L21/302 , H01L21/3065
摘要： PURPOSE:To enable to lift off a wiring of 1mum or less of line width by a method wherein an undercut-shape pattern is formed to a resist according to plasma etching. CONSTITUTION:A positive type photo resist 2 and a resist layer 3 containing triiodophenol are formed on an Si wafer 1 [the figure (a)]. A pattern of 0.8mum line width and 1.2mum line interval is transferred to the sample thereof formed with the two layer thin film according to the reducing projection exposure method following to the usual method, and only the layer 3 containing triiodophenol is developed [the figure (b)]. After that, when isotropic etching according to oxygen plasma is performed for 20min using a cylindrical plasma processor, the second layer pattern becomes to show resistance against oxygen plasma in proportion to progress of oxidation of triiodophenol, as a result thereof, a side etched shape can be formed to the lower layer resist layer [the figure (c)]. Al 4 is evaporated to the sample acted with the process mentioned above [the figure (d)], and by removing the resist parts 2, 3 according to a resist remover following to the usual method at the lift-off process, an Al wiring 4 of 0.8mum interval and 1.2mum line width can be formed [the figure (e)].

9. 发明专利

JPS5969929A Manufacture of mask for x-ray lithography 失效
标题翻译：用于X射线光刻的掩模的制造
公开(公告)号：JPS5969929A
公开(公告)日：1984-04-20
申请号：JP17985382
申请日：1982-10-15
申请人： Hitachi Ltd
发明人： OOHAYASHI HIDEHITO , KIMURA TAKESHI , MOCHIJI KOUZOU , SOGA TAKASHI , YANAGISAWA HIROSHI
IPC分类号： H01L21/027 , H01L21/30
CPC分类号： G03F1/22
摘要： PURPOSE:To prevent the coating of Ni, etc. onto a resist pattern, and to form an X-ray absorber of high quality on a mask substrate through electroless plating by making the surface of the resist pattern hydrophobic and attaching a catalyst. CONSTITUTION:The polished surface of the Si single crystalline substrate 1 is coated with Si3N4 2 and BN 3, the resist pattern 4 is formed, and the resist 4 is also applied on the whole back. The resists 4 are photo-inactivated through heat treatment, and the resists 4 are made hydrophobic completely through CF4 plasma treatment. The whole is dipped in a catalyst liquid for electroless Ni plating, the catalyst is attached, and a Ni film 5 is formed on the substrate through Ni electroless plating. The resists 4 are removed, and Si 1 is etched while leaving a peripheral section. Since the resist patterns and a resist film on the back do not moisten with the catalyst liquid, a phenomenon in which the side surfaces of the resist are coated with the Ni film by an electric capillarity can be prevented, and an absorption pattern consisting of the Ni film conforming to the resist pattern can be formed.
摘要翻译：目的：通过使抗蚀剂图案的表面疏水化并附着催化剂，通过化学镀来防止将Ni等涂覆在抗蚀剂图案上，形成高质量的X射线吸收体。构成：Si单晶衬底1的抛光表面涂覆有Si 3 N 4 2和BN 3，形成抗蚀剂图案4，并且抗蚀剂4也全部涂覆在背面。抗蚀剂4通过热处理而光致灭活，抗蚀剂4通过CF4等离子体处理完全疏水化。将其全部浸入用于无电镀镍的催化剂液体中，安装催化剂，并通过Ni化学镀在基板上形成Ni膜5。去除抗蚀剂4，并且在留下周边部分的同时蚀刻Si 1。由于抗蚀剂图案和背面的抗蚀剂膜不会被催化剂液体润湿，因此可以防止抗蚀剂的侧表面通过电毛细管涂覆有Ni膜的现象，并且可以防止由可以形成符合抗蚀剂图案的Ni膜。

10. 发明专利

JPS57149733A DRY ETCHING METHOD 失效
公开(公告)号：JPS57149733A
公开(公告)日：1982-09-16
申请号：JP3389881
申请日：1981-03-11
申请人： HITACHI LTD
发明人： KURE TOKUO , OKUDAIRA SADAYUKI , HASEGAWA NOBUO , YANAGISAWA HIROSHI , UEHARA KEIJIROU
IPC分类号： H01L21/302 , G03F7/36 , H01L21/3065
摘要： PURPOSE:To improve the characteristics of etching and controllability by irradiating ultraviolet rays to a photo-resist pattern and thermally treating it and conducting dry etching. CONSTITUTION:N2 Is discharged when ultraviolet rays are irradiated to the resist pattern or it is heated at 130 deg.C or higher, and etching can be conducted at predetermined speed, but an effect by an organic solvent, etc., which are not decomposed optically, is eliminated when further using jointly heat treatment, the etching further becomes effective, and the characteristics of etching and controllability are improved. It is preferabe that such treatment is executed just before etching, and the characteristics of etching is further improved when the resist pattern is exposed and heated in a pretreatment chamber and carried up to an etching chamber in vacuum.

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