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1. 发明专利

DE3036431A1 未知
公开(公告)号：DE3036431A1
公开(公告)日：1981-04-16
申请号：DE3036431
申请日：1980-09-26
申请人： HITACHI LTD
发明人： HIRAO MOTOHISA , NAKAMURA MICHIHARU , DOI ATSUTOSHI , TSUJI SHINJI , TAKEDA YUTAKA , MORI TAKAO
IPC分类号： H01L21/208 , H01L33/16 , H01L33/28 , H01L33/30 , H01L33/40 , H01S5/00 , H01S5/227 , H01S3/19

2. 发明专利

CA1150808A SEMICONDUCTOR LASER DEVICE 未知
公开(公告)号：CA1150808A
公开(公告)日：1983-07-26
申请号：CA361212
申请日：1980-09-29
申请人： HITACHI LTD
发明人： HIRAO MOTOHISA , NAKAMURA MICHIHARU , DOI ATSUTOSHI , TSUJI SHINJI , TAKEDA YUTAKA , MORI TAKAO
IPC分类号： H01L21/208 , H01L33/16 , H01L33/28 , H01L33/30 , H01L33/40 , H01S5/00 , H01S5/227 , H01S3/19
摘要： SEMICONDUCTOR LASER DEVICE A semiconductor laser device includes an active region consisting of a semiconductor material and a semiconductor region consisting of a material having a different composition from that of the active region and confining the active region. The invention provides at least one p-n junction formed inside the confining region in parallel with the active region. The impurity concentration of the region having the p-n junction is such that current can flow through regions other than the active region via the p-n junction at a field strength below that causing degradation of the device. As a result, the device does not undergo catastrophic degradation even when a current higher than the rated value is applied thereto.

3. 发明专利

CA1151275A SEMICONDUCTOR LASER DEVICE AND METHOD OF MANUFACTURING THE SAME 未知
公开(公告)号：CA1151275A
公开(公告)日：1983-08-02
申请号：CA377009
申请日：1981-05-06
申请人： HITACHI LTD
发明人： HIRAO MOTOHISA , DOI ATSUTOSHI , NAKAMURA MICHIHARU , TSUJI SHINJI , MORI TAKAO
IPC分类号： H01S5/00 , H01S5/227 , H01S3/19
摘要： : A buried-heterostructure semiconductor laser including a mesa-shaped optical confinement region having an active layer and a clad layer and disposed on a semiconductor substrate; a burying layer burying both side surfaces of the region; and at least one p-n junction so formed inside the burying layer in parallel to the active layer so as to be in a reverse biased state during the operation of the laser. Surface protection semiconductor layers are formed on the mesa-shaped optical confinement region and on the burying layer, respectively. They protect the semiconducor assembly in the arrangement such that the surface of the protection semiconductive layers do not come into direct contact with each other. Even if the forbidden band gaps of these surface protection semiconductor layers are relatively small, it is possible to realize a semiconductor laser having an extremely small leakage current and reduced variance of threshold current values, while protecting the surface of the multi-layer semiconductor layers.

4. 发明专利

JPS6144492A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS6144492A
公开(公告)日：1986-03-04
申请号：JP16012785
申请日：1985-07-22
申请人： Hitachi Ltd
发明人： SATOU NAOSHI , HIRAO MOTONAO , KOBAYASHI MASAYOSHI , MORI TAKAO
IPC分类号： H01L29/43 , H01L21/28 , H01S5/00 , H01S5/042
摘要： PURPOSE: To enhance the reliability of the titled device by preventing the reaction of both of the followings by providing an Mo or W barrier between a III-V group compound semiconductor crystal of GaAlAs, InGaAsP series or the like and a solder of Au or Au-Sn, In-Sn, or Pb-Sn series.
CONSTITUTION: A P type InP 5 and P type InGaAsP 6 are laminated on an InGaAsP active layer 3 filled with a P type InP 2 on an N-InP substrate 1, and an electrode window is provided in an SiO
2 film 7. Next, Cr of about 150∼500Å, Mo or W of about 1,000∼2,000Å, and Au of 1,000∼10,000Å are laminated by successive evaporation. Loading to a heat radiator produces the electrode structure of ohmic electrode and adhesion layer-barrier metallic laser-Au or solder layer. Even under high temperature and high output, the reaction of the solder and the laser constituent or the rise in operating current due to the diffusion of solder into the laser element never occurs.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：为了通过在GaAlAs，InGaAsP系列等的III-V族化合物半导体晶体和Au或Au的焊料之间提供Mo或W阻挡层来防止两者的反应来提高标题器件的可靠性 -Sn，In-Sn或Pb-Sn系列。构成：将AP型InP 5和P型InGaAsP 6层叠在N-InP基板1上填充有P型InP 2的InGaAsP活性层3上，在SiO 2膜7中设置电极窗。接着，将Cr 150-500埃，Mo或W为约1,000-2,000埃，Au为1,000-10,000埃，通过连续蒸发层压。负载到散热器产生欧姆电极和粘附层阻挡金属激光Au或焊料层的电极结构。即使在高温高输出的情况下，由于焊料向激光元件的扩散也不会发生焊料与激光成分的反应或工作电流的上升。

5. 发明专利

JPS6053018A IMPURITY DIFFUSION TO COMPOUND SEMICONDUCTOR 失效
公开(公告)号：JPS6053018A
公开(公告)日：1985-03-26
申请号：JP16034183
申请日：1983-09-02
申请人： HITACHI LTD
发明人： MORI TAKAO , TSUJI SHINJI , NAKAYAMA YOSHINORI , FUJISAKI YOSHIHISA , HIRAO MOTONAO
IPC分类号： H01L21/22 , H01L21/223 , H01L33/30 , H01L33/40 , H01S5/00
摘要： PURPOSE:To form a shallow impurity diffusion layer with high concentration, and moreover having favorable reproducibility when Zn is to be diffused to a compound semiconductor containing phosphorus by a method wherein an impurity diffusion source composed of zinc phosphide and phsphorus is used. CONSTITUTION:To diffuse Zn into InP, InGaAsP, when diffusion is performed adding phosphorus to a diffusion dopant source in addition to the simple substance of ZnP2, Zn3P2, the diffusing speed thereof can be controlled, and moreover, when an ohmic electrode is formed on the diffused layer, the favorably low resistance ohmic electrode can be obtained, and surface concentration of the diffused layer is also enlarged sufficiently. When an InGaAsP/InP semiconductor laser device is to be manufactured applying this invention, a Zn selective diffusion layer 510 of 8mum width and 1mum depth is formed using an oxide film 509 formed according to the CVD method as a mask to reduce contact resistance of the ohmic electrode 508 consisting of Cr/Au and to be formed on a P type InGaAsP layer. At this time, when Zn is diffused according to the diffusion source added with P to ZnP2, and the temperature is made at 610 deg.C and the diffusion time is made for 20-30min, a shallow diffusion layer can be formed at a high temperature and moreover under a favorable diffusion condition having favorable controllability.

6. 发明专利

JPS6021587A SEMICONDUCTOR LASER DEVICE 失效
公开(公告)号：JPS6021587A
公开(公告)日：1985-02-02
申请号：JP12768383
申请日：1983-07-15
申请人： HITACHI LTD
发明人： TSUJI SHINJI , MIZUISHI KENICHI , MORI TAKAO , HIRAO MOTONAO , NAKAYAMA YOSHINORI
IPC分类号： H01S5/00 , H01S5/227
摘要： PURPOSE:To reduce or eliminate the influence of crystal defect on an element structure by a method wherein an InGaAsP/InP buried hetero type laser is provided with a buried layer of a structure wherein an InGaAsP four-element layer is sandwiched by InP crystals. CONSTITUTION:The first crystal part 1' is composed of an InGaAsP active layer 11 on a substrate 3, a P type InGaAsP surface layer 13, and an InP 12; a buried crystal part 2' of a P type InP 21, an N type InP 22, an N type InGaAsP 24, a P type InP 25, and a P type InGaAsP layer 23 in this order from the substrate InP 3. Since the Peierls force of InGaAsP is larger than that of InP, the advancement of dislocation introduced in the wafer process is inhibited by the presence of the four-element layer 24, and accordingly the reactive current flowing through the buried layer can be reduced.

7. 发明专利

JPS58192370A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS58192370A
公开(公告)日：1983-11-09
申请号：JP7522382
申请日：1982-05-07
申请人： Hitachi Ltd
发明人： MORI MITSUHIRO , SAITOU KATSUTOSHI , MORI TAKAO , CHIBA KATSUAKI , KOBAYASHI MASAYOSHI , SATOU NOBU , KATOU HIROSHI , KOBAYASHI MASAMICHI
IPC分类号： H01L29/872 , H01L21/28 , H01L29/43 , H01L29/45 , H01L29/47 , H01S5/00 , H01L29/48
CPC分类号： H01L29/452
摘要： PURPOSE:To suppress the diffusion of constituting atoms and an ohmic contact forming metal of a substrate into an Au layer, which is used as an electrode, by a method wherein a metal layer consisting of Pd is provided on the metal layer, having Au as a base material, formed on a III-V group compound semiconductor substrate. CONSTITUTION:A P type ohmic electrode 32 is formed on the wafer 31 consisting of n-GaAs crystal. Then, Au-Ge-Ni 33 is vapor-deposited on the back side of the wafer 31. While the above vapor-deposition procedure is performed, an alloy reaction is generated between n-GaAs and Au-Ge-Ni alloy and an excellent ohmic contact is formed. Then, a Pd film 34 is vapor-deposited on the above. Desirably, a metal such as Au 35, for example, is vapor-deposited on the film 34. This film 34 can suppress the diffusion of Ge, Ga and the like on the surface of Au, thereby enabling to form a highly reliably ohmic electrode.
摘要翻译：目的：为了通过以下方法抑制构成原子的扩散和形成金属的基底的欧姆接触形成作为电极的Au层，其中在金属层上设置由Pd构成的金属层，其具有Au作为形成在III-V族化合物半导体衬底上的基材。构成：在由n-GaAs晶体构成的晶片31上形成P型欧姆电极32。然后，在晶片31的背面上气相沉积Au-Ge-Ni 33。在进行上述蒸镀工序的同时，在n-GaAs与Au-Ge-Ni合金之间产生合金化反应，形成欧姆接触。然后，在上述气相沉积Pd膜34。理想地，诸如Au 35的金属气相沉积在膜34上。该膜34可以抑制Ge，Ga等在Au表面上的扩散，从而能够形成高度可靠的欧姆电极。

8. 发明专利

JPH04159555A EXPOSURE DEVELOPING DEVICE 失效
公开(公告)号：JPH04159555A
公开(公告)日：1992-06-02
申请号：JP28424590
申请日：1990-10-24
申请人： HITACHI LTD
发明人： YOSHIDA SATOSHI , MORI TAKAO , MIZUISHI KENICHI
IPC分类号： G03F7/30 , G03F7/20 , H01L21/027 , H01L21/30
摘要： PURPOSE:To stabilize the exposure developing speed and to improve the resolution of a thick film pattern by providing a developer tank which can execute a development processing simultaneously with an exposure processing in the device. CONSTITUTION:A new developer is supplied and discharged into a developer tank 107 at a prescribed speed by a liquid supply pump 105. That is, as an exposure processing time elapses, a resist melting quantity into a developer increases. Since this melted resist has a light shielding operation, the light quantity irradiating an unexposed resist part is also changed with time. Simultaneously, since the resist meting quantity into a developer in the vicinity of an exposure part reaches a saturated state, the transmission light quantity also shows a saturation tendency, and an exposure developing speed decreases gradually. Therefore, by supplying uniformly a new developer to the whole surface of a sample at a constant speed by the liquid supply pump 105, the developer of the exposure part is always replaced with the new developer. In such a way, the light shielding operation of the resist melted in the developer can be prevented in advance, therefore, there is no change with time in the transmission light quantity, and the exposure developing speed is not saturated either.

9. 发明专利

JPH01147374A MICROPROBER 失效
公开(公告)号：JPH01147374A
公开(公告)日：1989-06-09
申请号：JP30563687
申请日：1987-12-04
申请人： HITACHI LTD
发明人： SATO KAZUO , MIZUISHI KENICHI , MORI TAKAO , YASUNAGA MORITOSHI , TODOKORO HIDEO
IPC分类号： G01R1/073 , G01R31/28 , H01L21/66
摘要： PURPOSE:To array probes with high density, to obtain a pointed probe to prevent an electric field from being disordered owing to wiring by forming a beam structure and a probe structure which projects vertically in the same body with a single crystal body. CONSTITUTION:A wafer 1 which has elements to be inspected on the surface is fixed on a movable table 2 and individual signal lines and feed lines on the wafer are probed by a probe substrate 3. The tracers 10 of the probe- substrate 3 and the beam structure 11 which receive a force for pressing the probes are formed of silicon single crystal in integrated structure. Slits 12 are formed in the beam structure 11 so as to enable the tips of all the probes to enter probing operation even if the surface of a body to be measured have unevenness. The signal and feed lines 13 are guided on the surface of the beam structure and terminated by pads 14, and signals are led out to an external connection substrate 5 from the pads 14 through a through hole substrate 4.

10. 发明专利

JPS63272056A CONNECTION ELECTRODES OF INTEGRATED SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63272056A
公开(公告)日：1988-11-09
申请号：JP10423087
申请日：1987-04-30
申请人： HITACHI LTD
发明人： MORI TAKAO , ONOZATO AKIMASA , YUKI FUMIO , MIZUISHI KENICHI
IPC分类号： H01L21/60
摘要： PURPOSE:To realize the high density arrangement of bump electrodes with a high aspect ratio and obtain connection electrodes which facilitate flip chip bonding in a clean atmosphere without using flux by a method wherein the connection electrodes are composed of Au or Cu bumps formed by selective plating with photosensitive resist as a mask. CONSTITUTION:Connection electrodes 102 in the mounting structure wherein a semiconductor device 101 of flip chip type and a wiring board 103 are connected to each other are composed of Au or Cu bumps formed by selective plating with photosensitive resist as a mask. For instance, bump electrodes 102 whose main component is Au are formed on the LSI device 101 beforehand. Au/Sn electrodes 102' are formed under the bump electrodes 102 beforehand and the Au bumps 102 are formed on the electrodes 102' by electroplating. Further, Au/Sn electrodes 102'' whose composition is the same as the composition of the Au/Sn electrodes 102' of the LSI device 101 are formed on wiring metal layers 105 of the wiring board 103. the electrodes of both the sides are mutually aligned and heated and melted to connect the LSI device 101 to the wiring board 103 with bump electrodes 102 between.

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