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1. 发明专利

JP2005209507A Dangerous substance detecting method 审中-公开
标题翻译：危险物质检测方法
公开(公告)号：JP2005209507A
公开(公告)日：2005-08-04
申请号：JP2004015539
申请日：2004-01-23
申请人： Hitachi Hybrid Network Co Ltd , Hitachi Ltd , 日立ハイブリッドネットワーク株式会社 , 株式会社日立製作所
发明人： HOSAKA KOJI , TAKEDA KATSUNOBU , KURIHARA MASAHIRO , NOJIRI TATSUO
IPC分类号： G01N27/62 , H01J49/06 , H01J49/40
摘要： PROBLEM TO BE SOLVED: To provide a dangerous substance detecting apparatus which can be easily used anywhere, by limiting the purpose of use so as to detect the presence of a particular determined dangerous substance.
SOLUTION: By analyzing an output change from the point when a gate is turned off in a short time after the ON-OFF gate controlling the passing/non-passing state of ions is turned on, the dangerous substance (explosive substance, chemical substance etc.) is determined.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种危险物质检测装置，其可以在任何地方容易地使用，通过限制使用目的来检测特定确定的危险物质的存在。
解决方案：通过分析在ON-OFF门控制离子通过/不通过状态之后的短时间内关闭栅极时的输出变化，危险物质（爆炸性物质，化学物质等）。版权所有（C）2005，JPO＆NCIPI

2. 发明专利

JP2004069501A Substance detection method and device 审中-公开
公开(公告)号：JP2004069501A
公开(公告)日：2004-03-04
申请号：JP2002229406
申请日：2002-08-07
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： NAGUMO KATSUMI , NODA MITSUHIRO , TAKIZAWA MASAYUKI , MORISHIMA SHIGENORI , NOJIRI TATSUO , AIKAWA YUKIAKI , SASAKI NAOYA
IPC分类号： G01N27/62 , G01N1/22 , G01N1/44 , G01N27/68 , G01N33/22 , H01J49/04 , H01J49/26
CPC分类号： G01N33/227 , G01N1/44
摘要： PROBLEM TO BE SOLVED: To provide a substance detection method and a device for it capable of detecting a substance with high precision (high sensitiveness) even on the substance with a low vapor pressure or of trace. SOLUTION: A sample 16, to which the substance adheres, is heated at a temperature, at which the substance is easily vaporized, for vaporizing the substance, and the atmospheric air is sucked to be fed into a space for arranging the sample. The vapor taken in by the sucked atmospheric air is negatively ionized. The substance adhering to the sample is detected when the ion is analyzed. COPYRIGHT: (C)2004,JPO

3. 发明专利

JP2005353340A Mass spectrometer 审中-公开
标题翻译：质谱仪
公开(公告)号：JP2005353340A
公开(公告)日：2005-12-22
申请号：JP2004170807
申请日：2004-06-09
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HONJO SHIGERU , HOSODA SHIGERU , NOJIRI TATSUO
IPC分类号： G01N27/62 , H01J49/04 , H01J49/26
摘要： PROBLEM TO BE SOLVED: To provide a mass spectrometer preventing lowering of detection rate occurring in conventional devices and analyzing respective substances to be detected in proper condition. SOLUTION: The mass spectrometer is constructed so as to analyze the substance to be detected by providing a single sample guiding part 1 for guiding and evaporating the sample, a plurality of ion sources 3, 6 for generating specific ions at every substances contained in the vapor of the sample supplied from the single sample guiding part, and mass analyzing parts 5, 8 performing the mass spectrometry, arranged so as to correspond to respective ion sources. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种防止传统装置中发生的检测率降低的质谱仪，并在适当的条件下分析待检测的各种物质。解决方案：质谱仪被构造成通过提供用于引导和蒸发样品的单个样品引导部分1来分析待检测的物质，用于在每个含有的物质产生特定离子的多个离子源4,6 在从单个样品引导部供给的样品的蒸气中以及进行质谱分析的质量分析部件5,8配置成对应于各离子源。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JPH02105611A D-TYPE LATCH CIRCUIT 失效
公开(公告)号：JPH02105611A
公开(公告)日：1990-04-18
申请号：JP25719888
申请日：1988-10-14
申请人： HITACHI LTD
发明人： YAMAUCHI TATSUMI , IWAMURA MASAHIRO , TADA HISASHI , TANAKA SHIGEYA , NOJIRI TATSUO , NAKANO TETSUO
IPC分类号： H03K3/037
摘要： PURPOSE:To supply a fast and stable data through time against the fluctuation of an output load by separating a positive feedback circuit for data storage from the output load, and using a BiCOS circuit as a separation means. CONSTITUTION:The output signal 102 of a clocked inverter 1 is brought into contact with the positive feedback circuit consisting of an inverter 2 and a clocked inverter 3. The locked inverter 3 is opened by a clock signal 202. A BiCMOS inverter 4 sets the signal as input and sets the output data 103 of a D-type latch circuit as output. Data through time is decided by the delay time of the clocked inverter 1 and the BiCMOS inverter 4. Also, data set-up time is decided by the delay time of the clocked inverter 1 and the inverter 2. Therefore, it is possible to supply the data through time and the data set-up time against the fluctuation of the output load at high speed and stably.

5. 发明专利

JPH09147571A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH09147571A
公开(公告)日：1997-06-06
申请号：JP32501995
申请日：1995-11-20
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MAKUTA KIICHI , NOJIRI TATSUO , KOBA TAKASHI , FUKAZAWA TAKESHI
IPC分类号： G11C11/41 , G11C11/413
摘要： PROBLEM TO BE SOLVED: To prevent the time from the memory cell selection operation to the sense amplifier activation from becoming excessively short when the gate length (the width dimension of polysilicon wiring layer) of the MOS transistor changes by the variation of the manufacturing process. SOLUTION: A sense amplifier activation control signal ϕsa is activated in synchronization with the completion of the pulsive change of an address change detection pulse signal ϕatd. Fuse blowing judgment circuits 15-18 determine the pulse width of the address change detection pulse signal ϕatd and the period until the sense amplifier activation control signal ϕsa is possible from the completion of the pulse change of the signal according to the fuse program state. Fuse blowing judging circuits 15-18 is programmed according to the measurement result using a circuit 30 where the drain/source current of the MOS transistor can be monitored from the outside of the chip.

6. 发明专利

JPH02103614A DYNAMIC CIRCUIT 失效
公开(公告)号：JPH02103614A
公开(公告)日：1990-04-16
申请号：JP25474988
申请日：1988-10-12
申请人： HITACHI LTD
发明人： TANAKA SHIGEYA , IWAMURA MASAHIRO , YAMAUCHI TATSUMI , NOJIRI TATSUO , TADA HISASHI , NAKANO TETSUO
IPC分类号： G06F7/00 , G06F3/00 , H03K19/0175 , H03K19/096 , H04L25/02
摘要： PURPOSE:To prevent malfunction of a dynamic circuit by accurately correcting data when the data are settled during a data transferring period. CONSTITUTION:Data are transferred to a logic circuit 107 by selecting any one of input signals 102-104. A data correction circuit 106 recharges an output signal line 108 with electric charges during a data transferring period upon finding settled data when transferring data are settle, namely, when, for example, the data change from '1' to '0' during the data transferring period. As a result, the output signal 108 is again set to the same state as that set in the initial state of the data transferring period and the settled data are accurately transferred. Therefore, the malfunction of this dynamic circuit can be prevented.

7. 发明专利

JPH0239232A DATA PROCESSOR 失效
公开(公告)号：JPH0239232A
公开(公告)日：1990-02-08
申请号：JP18885788
申请日：1988-07-28
申请人： HITACHI LTD
发明人： TANAKA SHIGEYA , IWAMURA MASAHIRO , YAMAUCHI TATSUMI , NOJIRI TATSUO , TADA HISASHI , NAKANO TETSUO
IPC分类号： G06F7/00 , G06F13/16 , G06F13/36 , G06F13/40 , G06F15/78
摘要： PURPOSE:To reduce the additional capacity of a bus connected to an arithmetic part by cutting off a read data transmission line connecting a subread bus and a main read bus and a write data transmission line connecting a subwrite bus and a main write bus at all times except the read and write access states respectively. CONSTITUTION:A bus output circuit 18 transmits the data received from a subread bus to a main read bus 201 with a read access and otherwise cuts off a read data transmission line. As a result, the load capacities of buses 201 and 202 are reduced as long as no access is given to a register group 16. Thus it is possible to perform the read and write access operations at a high speed owing to reduction of the load capacity in the case a computing element 14 transfers data to an external memory via the bus 201 or 202 and an input/output controller 17.

8. 发明专利

JPH0229813A CLOCK SIGNAL SUPPLYING SYSTEM 失效
公开(公告)号：JPH0229813A
公开(公告)日：1990-01-31
申请号：JP17902588
申请日：1988-07-20
申请人： HITACHI LTD
发明人： TADA HISASHI , IWAMURA MASAHIRO , TANAKA SEIYA , YAMAUCHI TATSUMI , NOJIRI TATSUO
IPC分类号： G06F1/10 , G06F1/04
摘要： PURPOSE:To minimize a clock skew by dividing a circuit group to be controlled at their operation by clock signals generated from the same driver and providing each of the divided circuit groups or circuits with a clock driver. CONSTITUTION:Both control signals C1, C2 are turned to 'H' and a clock signal CK is transmitted to circuit groups 13, 14 through clock drivers 15, 16. At that time, a difference of load values observed from clock drivers 15, 16 goes the difference of gate capacity between MOS transistors(TRs) 11 and 12. Thereby the shear of phases of clock signals practically supplied to the circuit groups 13, 14 is proportional to the capacity difference. In this case, the value is fixed independently of the number of circuits in the circuit groups 13, 14. Consequently, a skew between clock signals at the time of increasing the number of parallel processing bits in a digital system can be suppressed to the minimum.

9. 发明专利

JPH0714398A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH0714398A
公开(公告)日：1995-01-17
申请号：JP14193093
申请日：1993-06-14
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KUMAGAI TATSUHIKO , KIKUCHI TAKASHI , SAIE YASUHIKO , SATO MASAHIKO , NOJIRI TATSUO , IWATA MASAKI , WATANABE AKIO , MAKIYA MEGUMI
IPC分类号： G11C29/00 , G11C29/04 , H01L21/82 , H01L27/10
摘要： PURPOSE:To provide a semiconductor storage device capable of relieving a defective bit even when the defective bit is detected after the completion of the mounting process of a LSI chip. CONSTITUTION:In the memory cell array of a RAM, a storage unit of one block is constituted of a perscribed number of bits (16 bits) and the bits are assigned to a using situation flag bit, an address storage part, a main data storage part, a parity bit and a usable or not flag bit. In the block, a parity generating circuit 4 deciding whether the block itself functions normally or not and setting the usable or not flag to '1' when the unit is defective, a use block deciding circuit 5 selecting a nonuse block for a relief and a latch circuit 1 storing the address data of a defective block in the address storage part of a selected block are provided. Consequently, the relief of the defective block is possible by only alloting the address of the defective block to other nonuse blocks since the setting of the address is possible with a software regardless of the position on the chip of the memory cell.

10. 发明专利

JPH02108325A BUS PRECHARGING CIRCUIT AND HIGH-SPEED LOGICAL SYSTEM 失效
公开(公告)号：JPH02108325A
公开(公告)日：1990-04-20
申请号：JP26056688
申请日：1988-10-18
申请人： HITACHI LTD
发明人： IWAMURA MASAHIRO , TANAKA SHIGEYA , YAMAUCHI TATSUMI , NOJIRI TATSUO , TADA HISASHI , NAKANO TETSUO
IPC分类号： G06F3/00 , H03K17/16 , H03K17/687 , H03K19/096 , H04L25/02
摘要： PURPOSE:To shorten a precharging time by precharging a bus by means of a first precharging means, after a bus-reaches a certain potential, activating a second precharging means, and setting the bus potential at a prescribed value. CONSTITUTION:The precharging circuit consists of a pMOS 10 of the first precharging means, pMOSs 11 and 12 of the second precharging means, a pnp transistor(TR) 13, an inverter 14 of a bus potential identifying means, and they are linked to a power source terminal 7, a clock signal line 8 and a bus bit line 1-1 in a prescribed way. When the bus bit line 1-1 is at a potential '0', and phi is changed to '0', the pMOSs 10 and 11 are turned on, the output of the inverter 14 is '1', the pMOS is turned off, the npn TR 13 is turned off, the bus 1-1 is precharged only by the pMOS until it reaches a certain potential H, the concentration of a charging current is reduced, the inverter 14 is inverted by the potential H, the pMOS 12 and npn element 13 are turned on, since both precharge the bus, it can be completed in a period when phi is 0, the high-speed precharging and elimination of the current concentration are attained, and a high-speed logical system can be composed.

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