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1. 发明专利

JPH02103624A DATA PROCESSOR 失效
公开(公告)号：JPH02103624A
公开(公告)日：1990-04-16
申请号：JP25475088
申请日：1988-10-12
申请人： HITACHI LTD
发明人： NOJIRI TATSUO , IWAMURA MASAHIRO , TANAKA SHIGEYA , YAMAUCHI TATSUMI , TADA HISASHI , NAKANO TETSUO
IPC分类号： G06F7/00
摘要： PURPOSE:To perform bus access at a high speed by providing a buffer to a bus so that a load capacity can be separated. CONSTITUTION:The load capacity of the 3rd bus 106 connected to the output terminal (OUT) 803 of the bus output circuit 800 of an operator 103 is the input capacity of a buffer 109, namely, the sum of gate capacities of MOS transistors 501 and 502, input capacity of a by-pass, and wiring capacity for connecting the input capacity of the by-pass. That is, the load capacity of the 3rd bus 106 is reduced by the input capacities of all registers constituting a register file and the wiring capacity for connecting the input capacity as compared with the conventional system. Since the bus load capacity is separated to the operator side and the other side by providing the buffer 109 to the bus 106, high-speed bus access becomes possible.

2. 发明专利

JPH02108325A BUS PRECHARGING CIRCUIT AND HIGH-SPEED LOGICAL SYSTEM 失效
公开(公告)号：JPH02108325A
公开(公告)日：1990-04-20
申请号：JP26056688
申请日：1988-10-18
申请人： HITACHI LTD
发明人： IWAMURA MASAHIRO , TANAKA SHIGEYA , YAMAUCHI TATSUMI , NOJIRI TATSUO , TADA HISASHI , NAKANO TETSUO
IPC分类号： G06F3/00 , H03K17/16 , H03K17/687 , H03K19/096 , H04L25/02
摘要： PURPOSE:To shorten a precharging time by precharging a bus by means of a first precharging means, after a bus-reaches a certain potential, activating a second precharging means, and setting the bus potential at a prescribed value. CONSTITUTION:The precharging circuit consists of a pMOS 10 of the first precharging means, pMOSs 11 and 12 of the second precharging means, a pnp transistor(TR) 13, an inverter 14 of a bus potential identifying means, and they are linked to a power source terminal 7, a clock signal line 8 and a bus bit line 1-1 in a prescribed way. When the bus bit line 1-1 is at a potential '0', and phi is changed to '0', the pMOSs 10 and 11 are turned on, the output of the inverter 14 is '1', the pMOS is turned off, the npn TR 13 is turned off, the bus 1-1 is precharged only by the pMOS until it reaches a certain potential H, the concentration of a charging current is reduced, the inverter 14 is inverted by the potential H, the pMOS 12 and npn element 13 are turned on, since both precharge the bus, it can be completed in a period when phi is 0, the high-speed precharging and elimination of the current concentration are attained, and a high-speed logical system can be composed.

3. 发明专利

JPH0230215A SWITCHING CIRCUIT 失效
公开(公告)号：JPH0230215A
公开(公告)日：1990-01-31
申请号：JP17902488
申请日：1988-07-20
申请人： HITACHI LTD
发明人： TADA HISASHI , IWAMURA MASAHIRO , YAMAUCHI TATSUMI , TANAKA SEIYA , NOJIRI TATSUO
IPC分类号： H03K17/567 , H03K17/56 , H03K19/08
摘要： PURPOSE:To obtain an in-phase output from one logic stage by using a P- channel MOS and an N-channel MOS so as to control a base current of an NPN bipolar transistor(TR). CONSTITUTION:An N-channel TR 14 is conductive when a control signal C is logical H. A circuit 16 has a function of connecting a base node of a bipolar TR 15 and GND when an input signal IN is logical H or the control signal C is logical L. With the input signal IN going to L in this state, a P-channel TR 11 is conductive, a node of an output signal OUT is precharged and the bipolar TR 15 is conductive. The base current of the bipolar TR 15 is supplied via the P-channel TR 11 and the N-channel TR 14 in the first half of the discharging of the output signal OUT from the node and via the TRs 12, 14 in the latter half.

4. 发明专利

JPH01211014A BUS DRIVING SYSTEM AND POSITIVE FEEDBACK CIRCUIT 失效
公开(公告)号：JPH01211014A
公开(公告)日：1989-08-24
申请号：JP3526988
申请日：1988-02-19
申请人： HITACHI LTD
发明人： TADA HISASHI , IWAMURA MASAHIRO , YAMAUCHI TATSUMI
IPC分类号： G06F3/00 , H04L25/02
摘要： PURPOSE:To realize the amplitude of the power supply amplitude of a bus by securing the synchronization between the timing where a MOS bipolar transistor composite circuit drives the bus and the feedback action timing of a MOS type feedback circuit which is connected to the bus and applies the positive feedback to the bus potential. CONSTITUTION:A positive feedback circuit 103 consists of a MOS in a bus driving system where the synchronization is secured between the action timing of a bus driver and that of the circuit 103. Then a positive feedback action is applied to the voltage level of a bus only in a period while phi2 is kept at a level Vcc, i.e., a period when a MOS bipolar composite circuit drives the bus. As a result, the voltage level of the bus can be amplified at levels Vcc and GND. In addition, the circuit 103 does not work at all even though phi1 is set at the GND level and the precharge of the bus is started by a p channel transistor 101 because the phi2 is already equal to the GND level. Therefore the circuit 103 never prevent the precharge of the bus.

5. 发明专利

JPH02103614A DYNAMIC CIRCUIT 失效
公开(公告)号：JPH02103614A
公开(公告)日：1990-04-16
申请号：JP25474988
申请日：1988-10-12
申请人： HITACHI LTD
发明人： TANAKA SHIGEYA , IWAMURA MASAHIRO , YAMAUCHI TATSUMI , NOJIRI TATSUO , TADA HISASHI , NAKANO TETSUO
IPC分类号： G06F7/00 , G06F3/00 , H03K19/0175 , H03K19/096 , H04L25/02
摘要： PURPOSE:To prevent malfunction of a dynamic circuit by accurately correcting data when the data are settled during a data transferring period. CONSTITUTION:Data are transferred to a logic circuit 107 by selecting any one of input signals 102-104. A data correction circuit 106 recharges an output signal line 108 with electric charges during a data transferring period upon finding settled data when transferring data are settle, namely, when, for example, the data change from '1' to '0' during the data transferring period. As a result, the output signal 108 is again set to the same state as that set in the initial state of the data transferring period and the settled data are accurately transferred. Therefore, the malfunction of this dynamic circuit can be prevented.

6. 发明专利

JPH0239232A DATA PROCESSOR 失效
公开(公告)号：JPH0239232A
公开(公告)日：1990-02-08
申请号：JP18885788
申请日：1988-07-28
申请人： HITACHI LTD
发明人： TANAKA SHIGEYA , IWAMURA MASAHIRO , YAMAUCHI TATSUMI , NOJIRI TATSUO , TADA HISASHI , NAKANO TETSUO
IPC分类号： G06F7/00 , G06F13/16 , G06F13/36 , G06F13/40 , G06F15/78
摘要： PURPOSE:To reduce the additional capacity of a bus connected to an arithmetic part by cutting off a read data transmission line connecting a subread bus and a main read bus and a write data transmission line connecting a subwrite bus and a main write bus at all times except the read and write access states respectively. CONSTITUTION:A bus output circuit 18 transmits the data received from a subread bus to a main read bus 201 with a read access and otherwise cuts off a read data transmission line. As a result, the load capacities of buses 201 and 202 are reduced as long as no access is given to a register group 16. Thus it is possible to perform the read and write access operations at a high speed owing to reduction of the load capacity in the case a computing element 14 transfers data to an external memory via the bus 201 or 202 and an input/output controller 17.

7. 发明专利

JPH0229813A CLOCK SIGNAL SUPPLYING SYSTEM 失效
公开(公告)号：JPH0229813A
公开(公告)日：1990-01-31
申请号：JP17902588
申请日：1988-07-20
申请人： HITACHI LTD
发明人： TADA HISASHI , IWAMURA MASAHIRO , TANAKA SEIYA , YAMAUCHI TATSUMI , NOJIRI TATSUO
IPC分类号： G06F1/10 , G06F1/04
摘要： PURPOSE:To minimize a clock skew by dividing a circuit group to be controlled at their operation by clock signals generated from the same driver and providing each of the divided circuit groups or circuits with a clock driver. CONSTITUTION:Both control signals C1, C2 are turned to 'H' and a clock signal CK is transmitted to circuit groups 13, 14 through clock drivers 15, 16. At that time, a difference of load values observed from clock drivers 15, 16 goes the difference of gate capacity between MOS transistors(TRs) 11 and 12. Thereby the shear of phases of clock signals practically supplied to the circuit groups 13, 14 is proportional to the capacity difference. In this case, the value is fixed independently of the number of circuits in the circuit groups 13, 14. Consequently, a skew between clock signals at the time of increasing the number of parallel processing bits in a digital system can be suppressed to the minimum.

8. 发明专利

JPH035863A DIGITAL SYSTEM 失效
公开(公告)号：JPH035863A
公开(公告)日：1991-01-11
申请号：JP13905489
申请日：1989-06-02
申请人： HITACHI LTD
发明人： TADA HISASHI
IPC分类号： G06F13/36
摘要： PURPOSE:To multifunctionalize a system without impairing the high integration of the system by minimizing the number of signal lines to be used for data transfer between functional blocks and in addition executing inter-block data transfer without adding any additional function. CONSTITUTION:The functional block to generate address information transmits address signal to another functional block through a data signal line when a timing signal is of ''High'' level or ''Low'' level. The functional block which recognizes that itself was selected by this address signal sends a data signal or outputs the data signal to the data signal line when the following timing signal is of ''Low'' level or ''High'' level. Accordingly, even if the number of peripheral functional blocks increases, data transfer between the functional blocks can be executed without increasing the number of wirings and without adding any additional function. Thus, the multifunctionalization of digital system can be realized while satisfying the high integration of the system.

9. 发明专利

JPH02105611A D-TYPE LATCH CIRCUIT 失效
公开(公告)号：JPH02105611A
公开(公告)日：1990-04-18
申请号：JP25719888
申请日：1988-10-14
申请人： HITACHI LTD
发明人： YAMAUCHI TATSUMI , IWAMURA MASAHIRO , TADA HISASHI , TANAKA SHIGEYA , NOJIRI TATSUO , NAKANO TETSUO
IPC分类号： H03K3/037
摘要： PURPOSE:To supply a fast and stable data through time against the fluctuation of an output load by separating a positive feedback circuit for data storage from the output load, and using a BiCOS circuit as a separation means. CONSTITUTION:The output signal 102 of a clocked inverter 1 is brought into contact with the positive feedback circuit consisting of an inverter 2 and a clocked inverter 3. The locked inverter 3 is opened by a clock signal 202. A BiCMOS inverter 4 sets the signal as input and sets the output data 103 of a D-type latch circuit as output. Data through time is decided by the delay time of the clocked inverter 1 and the BiCMOS inverter 4. Also, data set-up time is decided by the delay time of the clocked inverter 1 and the inverter 2. Therefore, it is possible to supply the data through time and the data set-up time against the fluctuation of the output load at high speed and stably.

10. 发明专利

JPH01224819A BUS CONTROL SYSTEM 失效
公开(公告)号：JPH01224819A
公开(公告)日：1989-09-07
申请号：JP4955288
申请日：1988-03-04
申请人： HITACHI LTD
发明人： TADA HISASHI , IWAMURA MASAHIRO , YAMAUCHI TATSUMI
IPC分类号： G06F3/00 , G06F13/40
摘要： PURPOSE:To attain the simultaneous using of buses which have different polarities in the same digital system and to attain the independent parallel using of the buses by connecting the bus of a precharging type and the bus of a discharging type, and controlling. CONSTITUTION:A bus switch circuit 103 to control the discharging means of a bus BUS1 side of a precharging type by the data of a bus BUS2 of a discharg ing type and to control the precharging means of the bus BUS2 side of the discharging type by the data of the bus BUS1 of the precharging type is pro vided between the buses which have different polarities. Thus, the connecting and controlling of the bus of the precharging type and the bus of the discharging type which have the different 2,... polarities can be executed, and in a period when registers R1-1, R1-2, and R2-1, R2-2,... output the data to the BUS1 and the BUS2, the parallel using of the BUS1 and the BUS2 is attained by keeping a SW1 an 'L' and a SW2 an 'H'.

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