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1. 发明专利

DE69031365T2 未知
公开(公告)号：DE69031365T2
公开(公告)日：1998-04-02
申请号：DE69031365
申请日：1990-06-20
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： NISHII OSAMU , UCHIYAMA KUNIO , AOKI HIROKAZU , KIKUCHI TAKASHI , SAIGOU YASUHIKO
IPC分类号： G06F12/08
摘要： A non-shared system with respect to an outside and an inside cache in a multi-processor system has a multi-layer hierarchical cache. An invalidation address on a main memory address bus 31 in company with the rewriting of a main memory 30 is transmitted via a first and a second path 35, 36 to inside caches 11,21 so as to invalidate these inside caches 11, 21. The invalidation address is transmitted to the outside caches 12, 22 via the bidirectional connections between the main memory address bus 31 and outside caches 12, 22 so as to invalidate these outside caches 12, 22. It is extremely improbable for the address of access for writing to be transmitted to the main memory address bus 31 because the outside caches 12, 22 are operated either as a copy back or write once system. As a result, even though the invalidation address is transmitted to the outside caches 12, 22 via the bidirectional connections between the main memory address bus 31 and the outside caches 12, 22, it is extremely improbable for the address of access for writing to conflict with a signal on the bidirectional connection.

2. 发明专利

DE69031365D1 未知
公开(公告)号：DE69031365D1
公开(公告)日：1997-10-09
申请号：DE69031365
申请日：1990-06-20
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： NISHII OSAMU , UCHIYAMA KUNIO , AOKI HIROKAZU , KIKUCHI TAKASHI , SAIGOU YASUHIKO
IPC分类号： G06F12/08
摘要： A non-shared system with respect to an outside and an inside cache in a multi-processor system has a multi-layer hierarchical cache. An invalidation address on a main memory address bus 31 in company with the rewriting of a main memory 30 is transmitted via a first and a second path 35, 36 to inside caches 11,21 so as to invalidate these inside caches 11, 21. The invalidation address is transmitted to the outside caches 12, 22 via the bidirectional connections between the main memory address bus 31 and outside caches 12, 22 so as to invalidate these outside caches 12, 22. It is extremely improbable for the address of access for writing to be transmitted to the main memory address bus 31 because the outside caches 12, 22 are operated either as a copy back or write once system. As a result, even though the invalidation address is transmitted to the outside caches 12, 22 via the bidirectional connections between the main memory address bus 31 and the outside caches 12, 22, it is extremely improbable for the address of access for writing to conflict with a signal on the bidirectional connection.

3. 发明专利

JPH08314775A FILE MEMORY DEVICE 失效
公开(公告)号：JPH08314775A
公开(公告)日：1996-11-29
申请号：JP13739395
申请日：1995-05-11
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： YOKOBE CHIHOKO , KIKUCHI TAKASHI , HATANO SOICHI , SAIE YASUHIKO , OOKUBO CHIKAO , SUZUKI TAKESHI , KATAYAMA KUNIHIRO , KAKI KENICHI , KADOWAKI SHIGERU , KISHI MASAMICHI
IPC分类号： G06F12/00
摘要： PURPOSE: To save the effective data in a garbage collection processing object area and to increase the speed of data transfer for compaction of ineffective sectors in the pertinent area. CONSTITUTION: Data to be the garbage collection processing object is read out from a flash memory 5, and parallely, this data is supplied to a microcomputer 3 and made to be able to be written in a RAM in parallel with this read, and thereby, read and write of garbage collection processing object data are realized in the same memory cycle. Garbage collection processing object data is taken into the microcomputer, too, and sector management information included in this data is referred to perform the processing for compaction.

4. 发明专利

JPH06250914A MEMORY CONTROLLER AND DATA PROCESSOR 失效
公开(公告)号：JPH06250914A
公开(公告)日：1994-09-09
申请号：JP5773393
申请日：1993-02-23
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ETO YOICHIRO , KIKUCHI TAKASHI , SAIE YASUHIKO , EGAWA HIDEKAZU , WATANABE AKIO , KUMAGAI TATSUHIKO , OOKUBO CHIKAO , NISHIMOTO KENJI
IPC分类号： G06F12/06 , G06F12/00
摘要： PURPOSE:To simplify hardware constitution when plural memories different in cycle time can be used in a common system. CONSTITUTION:A memory controller 44 is formed by including an address register 3 holding wait information of cycle time for the respective memories different in cycle time and an RDY* signal generation circuit 1 generating RDY 3 for deciding a bus cycle in memory access based on holding information of the address register 3 at the time of memory access. Hardware constitution is simplified by using the memory controller compared to a case when a circuit having the similar signal generation function is formed by TTL and the like.

5. 发明专利

JPH06103156A REVERSIBLE MEMORY DEVICE 失效
公开(公告)号：JPH06103156A
公开(公告)日：1994-04-15
申请号：JP2278391
申请日：1991-01-23
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： OOKUBO CHIKAO , KIKUCHI TAKASHI
IPC分类号： G06F12/00
摘要： PURPOSE:To provide a reversible memory device which can construct a system in response to the due purpose of application and also to provide a semiconductor storage that can be applied to various uses. CONSTITUTION:A reversible memory device REM consists of a stack memory and its controller CONT, and an epock pointer EP is provided on a packing substrate to designate the logical time variables of the stack memory and the controller CONT. The storage capacity of the REM can be increased in response to the specifications of the system connected to the pointer EP. The common address and data buses secure the connection between plural memories constructing the stack memory and the CONT and the system side respectively. Thus a memory system can be constructed in response to the due to purpose of application with increase or decrease the number of memories provided on the substrate. Furthermore the number of terminals of the CONT can be decreased with use of the common buses. Then the CONT can be easily transformed into an LSI and also can be connected to the memories in response to each purpose of application.

6. 发明专利

JPH0635839A SYSTEM CONTROLLER 失效
公开(公告)号：JPH0635839A
公开(公告)日：1994-02-10
申请号：JP20735692
申请日：1992-07-10
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： WATANABE AKIO , KIKUCHI TAKASHI , OOKUBO CHIKAO , SAIE YASUHIKO , EGAWA HIDEKAZU , ETO YOICHIRO , KUMAGAI TATSUHIKO , NOJIRI TATSUO
IPC分类号： G06F13/16
摘要： PURPOSE:To improve the throughput of an MPU by asserting the signal showing the continuation of processing carried out by a peripheral circuit to the MPU and ending the bus cycle of the peripheral circuit. CONSTITUTION:The state of the signal transferred between an MPU 21 and a memory 23 is kept and at the same time the signal showing the continuation of processing carried out by the memory 23 is asserted to the MPU 21. Thus, the bus cycle is ended for the memory 23 by a memory controller 22. Then, the operation of the memory 23 can be controlled even after the bus cycle of the MPU 21 was completed for an access to the memory 23. Thus, the throughput is improved for the MPU 21 and an MPU bus 25.

7. 发明专利

JPH0481949A BUFFER STORAGE DEVICE 失效
公开(公告)号：JPH0481949A
公开(公告)日：1992-03-16
申请号：JP19588590
申请日：1990-07-24
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： FUSE YASUFUMI , KIKUCHI TAKASHI , OOKUBO CHIKAO , SAIKOU YASUHIKO , FURUNOMA TOSHIHIKO , NISHIMOTO KENJI , HATANO SUSUMU
IPC分类号： G06F12/08 , G06F9/46
摘要： PURPOSE:To improve the cache hit rate at the time of switching a task, and the throughput as the whole system by executing in a lump the transfer of program data of a new task at the time of switching the task. CONSTITUTION:A cache memory A consists of a directory memory 1 in which an address tag is stored, a data memory 2 in which data is stored, a block substitution control unit 3 of an LRU (Least Recently Used) system and a tag comparator 4, a control circuit 6 for controlling the inside of the memory, etc., and this cache memory A is connected between a CPU 20 and a main memory 21 through a CPU 10 and a system bus 11. In such a state, at the time of switching a task, program data of a new task is transferred in a lump. In such a way, although a processing speed immediately after switching the task decreases to some extent, the cache hit rate is enhanced to a saturation state at a stroke, and the throughput as the whole system is improved.

8. 发明专利

JPH0454653A CACHE MEMORY 失效
公开(公告)号：JPH0454653A
公开(公告)日：1992-02-21
申请号：JP16412190
申请日：1990-06-25
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： FURUNOMA TOSHIHIKO , SAIKOU YASUE , KIKUCHI TAKASHI , IWATA MASAKI , SASAKI KOTOKO , FUSE YASUFUMI , HATANO SUSUMU , NISHIMOTO KENJI , AOKI HIROKAZU , NISHII OSAMU
IPC分类号： G06F12/08
摘要： PURPOSE:To shorten the memory access time executed by a processor by allowing a cache memory to share a part of storage information of a main memory and hierarchizing the main memory. CONSTITUTION:A cache memory 3 is provided with an address store part 23, a data memory 24, and a control means 30. In the memory 24, a part of information stored in a main memory 6 is stored, and address information of this information is stored in the stored part 23. Accordingly, by referring to the store contents of this store part 23, whether access object data of a processor MPU 1 exists in the memory 24 or not is known. With respect to an access of the memory 6 from the processor 1, in the case its access object data does not exist in the memory 24 of the inside, a prescribed data group containing its access object data is transferred to the memory 24 form the memory 6. Such a transfer control is executed by a control means 30. In such a way, a system operation stop for initializing a register in the cache memory 3 becomes unnecessary, and the throughput of a cache memory application system is improved.

9. 发明专利

JPH023172A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH023172A
公开(公告)日：1990-01-08
申请号：JP14307888
申请日：1988-06-10
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SAIE YASUHIKO , FUKUDA HIROSHI , KIKUCHI TAKASHI , OOISHI KANJI , HATANO SUSUMU , UCHIYAMA KUNIO , AOKI HIROKAZU
IPC分类号： G06F12/08 , G11C11/34 , G11C11/401 , G11C11/413
摘要： PURPOSE:To improve the flexibility of a cache memory by selecting a system to provide a synchronizing circuit in the cache memory and a system composing the synchronizing circuit of an external circuit with a user as needed. CONSTITUTION:When the user constitutes the system so that a cache memory 1 and a main memory can be operated with a same clock, a SYNC signal of an L level is provided from a main storage controller. Then, an inputted MDC (memory bass data complete) signal is not passed through a synchronizing circuit 18 but supplied to a control logic 16. Thus, the processing speed of the system is improved. Next, when the user constitutes the system so that the memory 1 can be operated by the separate clock, the SYNC signal of an H level is given to the memory 1. Then, the MDC signal is passed through a changing-over switch 19 and inputted to the synchronizing circuit 18. Here, the signal goes to be a signal CM, which is synchronized to the clock in the memory 1 side, and the signal is supplied to the logic 16.

10. 发明专利

JPH08137736A STORAGE DEVICE 失效
公开(公告)号：JPH08137736A
公开(公告)日：1996-05-31
申请号：JP29878594
申请日：1994-11-08
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： OOKUBO CHIKAO , KIKUCHI TAKASHI , SUZUKI TAKESHI , KADOWAKI SHIGERU , KISHI MASAMICHI , KATAYAMA KUNIHIRO , KANNO TOSHIO
IPC分类号： G06F12/00
摘要： PURPOSE: To shorten the access waiting time of a system-side against a flash I/O card by preferentially executing read access request/write access request against flash memory file/write data buffer when they are given during the transfer processing of write data. CONSTITUTION: When the read access request for the flash memory file FMF from the system-side or the write access request for the flash memory file FMF are given while the transfer processing of write data is executed by a micro computer part MC, the micro computer part MC is interrupted so as to interrupt the transfer processing on condition that it is not on an address during the transfer processing. Then, read access and write access are preferentially executed. Thus, access waiting time as the system-side for flash I/O card FIO can be shortened.

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