专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPS5776634A Digital signal processor 失效
标题翻译：数字信号处理器
公开(公告)号：JPS5776634A
公开(公告)日：1982-05-13
申请号：JP15205180
申请日：1980-10-31
申请人： Hitachi Denshi Ltd , Hitachi Ltd
发明人： HAGIWARA YOSHIMUNE , SUGIYAMA SHIZUO , MAEDA SHIGEMICHI , YUMOTO OSAMU , AKAZAWA TAKASHI , KOBAYASHI SEIJI , KITA YASUHIRO , KIDA YUUZOU
IPC分类号： G06F7/00 , G06F5/01 , G06F7/50 , G06F7/57 , G06F7/76 , G06F17/10
CPC分类号： G06F7/483 , G06F5/012 , G06F7/485 , G06F7/49921 , G06F2207/3856
摘要： PURPOSE: To process a digital signal of a voice, ec., in real time at a high speed, by exercising pipeline control under which multipliation, and addition and subtraction are performed in parallel.
CONSTITUTION: A floating-point arithmetic type multiplier 14 is supplied with an exponent display part from an X bus 21 and a mantissa display part from a Y bus 22. The multiplier 14 calculates and outputs the product of those two data to a P bus 24, and also outputs the exponent display part and mantissa a display part, which are not operated, to an X bus 25 and an Y bus 26 as they are. A floating- point arithmetic type adder-subtractor 15, on the other hand, inputs and operates output data X, Y and P of the multiplier 14 and data D and A of data 20 and 27, and outputs the results to an accumulator 16. Floating-point data latched in the accumulator 16 is outputted to an A bus 27 and a D bus 20 through a switch circuit 17. The arithmetic results of the multiplier 14 and adder-subtractor 15 are stored in a state code register and outputted from an output register 30 in parallel.
COPYRIGHT: (C)1982,JPO&Japio
摘要翻译：目的：通过执行并行执行乘法和加法和减法的流水线控制，以高速实时处理语音的数字信号。构成：浮点运算型乘法器14从X总线21的指数显示部分和Y总线22的尾数显示部分提供。乘法器14计算并将这两个数据的乘积输出到P总线24 并且还将X指令显示部分和尾数未被操作的显示部分原样输出到X总线25和Y总线26。另一方面，浮点运算型加减法器15输入并运算乘法器14的输出数据X，Y和P，以及数据20和27的数据D和A，并将结果输出到累加器16。锁存在累加器16中的浮点数据通过开关电路17输出到A总线27和D总线20.乘法器14和加减法器15的算术结果存储在状态码寄存器中，并从输出寄存器30并联。

2. 发明专利

JPS5776635A Floating multiplying circuit 失效
标题翻译：浮动电路
公开(公告)号：JPS5776635A
公开(公告)日：1982-05-13
申请号：JP15205380
申请日：1980-10-31
申请人： Hitachi Denshi Ltd , Hitachi Ltd
发明人： KOBAYASHI SEIJI , MAEDA SHIGEMICHI , HAGIWARA YOSHIMUNE , AKAZAWA TAKASHI , SUGIYAMA SHIZUO
IPC分类号： G06F7/38 , G06F7/00 , G06F7/487 , G06F7/52 , G06F7/533 , G06F7/544 , G06F7/76
CPC分类号： G06F7/4876 , G06F7/49921 , G06F7/5443
摘要： PURPOSE: To handle a digit overflow in floating-point arithmetic at a high speed without performing program processing, by providing a digit overflow detection part to the mantissa part or exponential part of an input or an output and by driving a digit overflow correcting circuit by its detection signal.
CONSTITUTION: Twelve-bit mantissa data corresponding to mantissas M
1 and M
2 are applied as input signals l
1 and l
2 to a multiplying circuit 1, which outputs a multiplication result l
5 . Four-bit exponent data corresponding exponents e
1 and e
2 , on the other hand, are applied as input signals l
3 and l
4 to an adding circuit 2, which outputs a signal l
6 . Those input and output signals are represented by four- bit complements of "2", so restricted as indicated: -8≤l
3 , l
4 , l
6 ≤7. A correcting circuit 4 outputs a detection signal C
8 for detecting an exponent being 8, a signal CMC indicating an overflow of the high-order digit of an exponent, and a signal CMV indicating an overflow of the low-order digit of an exponent. Then, an arithmetic circuit II corrects an exponent and a mantissa in case of the overflow of the low-order digit of the exponent.
COPYRIGHT: (C)1982,JPO&Japio
摘要翻译：目的：为了在不执行程序处理的情况下以浮点运算来处理数字溢出，通过向输入或输出的尾数部分或指数部分提供数字溢出检测部分，并通过驱动数字溢出校正电路其检测信号。构成：对应于尾数M1和M2的十二位尾数数据作为输入信号l1和I2施加到乘法电路1，乘法电路1输出乘法结果15。另一方面，对应于指数e1和e2的四比特指数数据作为输入信号13和14施加到加法电路2，加法电路输出信号16。那些输入和输出信号由“2”的四位补码表示，因此受到限制：-8 <= 13，14，16 = 7。校正电路4输出用于检测指数为8的检测信号C8，指示指数的高位数字的溢出的信号CMC和指示指数的低位数字的溢出的信号CMV。然后，算术电路II在指数的低位数字的溢出的情况下校正指数和尾数。

3. 发明专利

JPS5776633A Signal processor 失效
标题翻译：信号处理器
公开(公告)号：JPS5776633A
公开(公告)日：1982-05-13
申请号：JP15205280
申请日：1980-10-31
申请人： Hitachi Denshi Ltd , Hitachi Ltd
发明人： SUGIYAMA SHIZUO , HAGIWARA YOSHIMUNE , MAEDA SHIGEMICHI , AKAZAWA TAKASHI , KOBAYASHI SEIJI , KITA YASUHIRO , KIDA YUUZOU
IPC分类号： G06F3/05 , G06F5/00 , G06F5/01 , G06F17/10
CPC分类号： G06F5/017
摘要： PURPOSE:To eliminate the limitations of the bit length and bit arrangement of an input signal by arranging the bits of the input signal inversely of the bit arrangement inputted to a shift register when the least significant digit bit arrives as an initial bit. CONSTITUTION:When the least significant digit bit LSB comes first, an AND circuit 206 is selected by a control signal 22. Input data stored in a shift register 209 with the LSB at the beginning is transmitted to a data bus output switching circuit 210. When the data is outputted to a line 25, the control signal 22 permits switching so that the 2 of the data bus 25 is assigned to the bit SR15 of the register, and the 2 to the bit SRO. When the most significant digit bit MSB comes first, an AND circuit 205 is signified and the input data is stored in the shift register 209 being shifted successively from the SRO to SR15. In this case, a bus output switching circuit 210 sends the output, as it is, without changing the bit arrangement.
摘要翻译：目的：为了消除输入信号的位长度和位排列的限制，通过将输入信号的位与输入到移位寄存器的比特排列相反，当最低有效位被作为初始位到达时。构成：当最低有效位LSB首先出现时，通过控制信号22选择与电路206.存储在移位寄存器209中的与开始的LSB的输入数据被发送到数据总线输出切换电路210.当数据被输出到行25，控制信号22允许切换，使得数据总线25的2 0被分配给寄存器的位SR15，而2 <15>分配给位SR0。当最高有效位MSB首先出现时，表示AND电路205，并且将输入数据存储在从SRO向SR15连续移位的移位寄存器209中。在这种情况下，总线输出切换电路210原样发送输出，而不改变位的布置。

4. 发明专利

JPH02224021A ADDING AND SUBTRACTING DEVICE 失效
公开(公告)号：JPH02224021A
公开(公告)日：1990-09-06
申请号：JP18737589
申请日：1989-07-21
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： HAGIWARA YOSHIMUNE , SUGIYAMA SHIZUO , MAEDA SHIGEMICHI , YUMOTO OSAMU , AKAZAWA TAKASHI , KOBAYASHI MASAHITO , KITA YASUHIRO , KIDA YUZO
IPC分类号： G06F7/485 , G06F7/50 , G06F7/527 , G06F7/53 , G06F17/10
摘要： PURPOSE:To obtain a fast adding and subtracting device which can be used without being aware of whether data to be added or subtracted is floating-point or fixed-point data by converting fixed-point data into floating-point data in response to 3rd floating-point data. CONSTITUTION:When a fixed-point display is converted (FXFL) into a floating- point display, a selecting circuit 61 selects an accumulator output supplied from an A bus 27, i.e. fixed-point data A as outputs alphaM and alphaE. A selecting circuit 60 selects data y2 for conversion, which is read out of a memory 5 or 6 to a (Y) bus 26 by being specified by the address part of an FXFL instruction, as output betaM and betaE. The data y2 for conversion is selected within a range wherein, for example, the mantissa part betaM is zero and the exponent part betaE is +7 - -8 and has a certain reference value. Consequently, the fast, high- accuracy OR arithmetic function is obtained.

5. 发明专利

JPS6115615B2 JPS6115615B2 - 失效
公开(公告)号：JPS6115615B2
公开(公告)日：1986-04-25
申请号：JP9720978
申请日：1978-08-11
申请人： Hitachi Ltd
发明人： ISHIZUKA KOHEI , KITA YASUHIRO , MAEDA SHIGEMICHI
IPC分类号： H03G3/02 , H03G3/00 , H03G3/12
CPC分类号： H03G3/001 , H03G3/00

6. 发明专利

JPS60100229A DATA PROCESSOR 失效
公开(公告)号：JPS60100229A
公开(公告)日：1985-06-04
申请号：JP20825584
申请日：1984-10-05
申请人： HITACHI LTD
发明人： HAGIWARA YOSHIMUNE , MAEDA SHIGEMICHI , AKAZAWA TAKASHI , KOBAYASHI MASAHITO , KIDA YUUZOU , KITA YASUHIRO
IPC分类号： G06F9/30 , G06F15/78
摘要： PURPOSE:To reduce the area of wiring for a control signal by arranging an instruction decoding circuit and an operation timing signal generating circuit dispersedly for every function block. CONSTITUTION:The address of an instruction word to be read is supplied from a program address counter 1 to a program memory 2 to read the instruction word for internal operation control, and the word is outputted as a control signal group to respective function blocks 6-13 formed on an integrated circuit substrate. In this case, instruction decoders i-4, instruction registers i-3, timing signal generating circuits i-5 are arranged dispersedly on the substrate adjacently to the function blocks 6-13. Further, instruction output lines 215 from the program memory 2 are laid as a bus connecting the respective blocks 6-13, and a basic timing signal line 214 is also arranged. Consequently, the occupation area of control signal woring among the blocks is reduced and the number of the signal lines 214 and 215 is decreased greatly.

7. 发明专利

JPS6055763A PHASE CONTROL METHOD 失效
公开(公告)号：JPS6055763A
公开(公告)日：1985-04-01
申请号：JP16364483
申请日：1983-09-06
申请人： HITACHI ELECTRONICS , HITACHI LTD
发明人： KAWASHIMA MASATOSHI , MAEDA SHIGEMICHI
IPC分类号： H04L27/22 , H04L27/227
摘要： PURPOSE:To correct a phase error momentarily by setting the value of a coefficient to 1 or a value approximating 1 when a phase is lead in initially and setting this value to a value requested by characteristics of a circuit after initial leading-in is completed. CONSTITUTION:When phase control is led in initially, a signal is not supplied to a terminal 5K, and a coefficient of k=1.0 generated by a coefficient generator 5i is supplied to a multiplier 5e through a switch 5j. The multiplier 5e supplies an input phase error signal to one input terminal of an adder 5g with size as it is. At this time, the output of a delay circuit 5h is not generated, and therefore, no signal is supplied to the other input terminal of the adder 5g. Therefore, the output of the multiplier 5e is supplied to a terminal 5b as it is, and this signal is supplied to a phase corrector 2. Thus, the phase error of a receiving signal is corrected momentarily, and initial leading-in is completed immediately.

8. 发明专利

JPS57181210A DEMODULATION SYSTEM 失效
公开(公告)号：JPS57181210A
公开(公告)日：1982-11-08
申请号：JP6643882
申请日：1982-04-20
申请人： HITACHI LTD
发明人： FURUYA MASAHIRO , MAEDA SHIGEMICHI , NAKAZAWA HIDEO , KITA YASUHIRO
IPC分类号： H04N1/40 , H03D1/22
摘要： PURPOSE:To achieve demodulation without increasing a sampling frequency by using a triangular wave as a carrier for synchronous detection. CONSTITUTION:A triangular wave is used as a carrier for synchronous detection. When this triangular wave is processed by Fourier series expansion, higher hamonics are reduced in order of 1/(n ). Thus, less-distortion demodulation is achieved without increasing a scampling frequency. In concrete, a transmitted modulated facsimile signal 5 while applied directly to a demodulator 4 is branched and inputted to a digital PLL1, which sends a carrier component signal 6 to a triangular wave generator 9 to regenerate a triangular-wave carrier 10 having a prescribed frequency, which is applied to the demodulator 4. The regenerated carrier 10 is multiplied by the directly-inputted modulated facsimile signal 5, thereby sending out a demodulated facsimile signal 11.

9. 发明专利

JPS5441614A IDENTIFYING CIRCUIT OF SIGNAL FOR MODEM 失效
公开(公告)号：JPS5441614A
公开(公告)日：1979-04-03
申请号：JP10781977
申请日：1977-09-09
申请人： HITACHI LTD
发明人： MAEDA SHIGEMICHI , KITA YASUHIRO
IPC分类号： H04N1/40 , H04N1/00 , H04N1/411
摘要： PURPOSE:To establish the signal identifying circuit less in circuit scale, by digitally performing the signal operation in a MODEM for facsimile.

10. 发明专利

JPS5187943A 失效
公开(公告)号：JPS5187943A
公开(公告)日：1976-07-31
申请号：JP1254875
申请日：1975-01-31
申请人： HITACHI LTD
发明人： ISHIZUKA KOHEI , KITA YASUHIRO , NAKAGAWA KOIICHI , TAKAHASHI YOSHITAKA , MAEDA SHIGEMICHI
IPC分类号： H03H11/04

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式