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1. 实用新型

KR840000044Y1 공기 조화기의 제어회로 失效
公开(公告)号：KR840000044Y1
公开(公告)日：1984-01-25
申请号：KR830009165
申请日：1983-10-27
申请人： HITACHI LTD
发明人： ABE YUHEI , YABE YUHIKO , AZUMA NOBUO , HAGIWARA YOSHIMUNE
IPC分类号： F24F11/76 , F24F11/053
摘要： 내용없음.

2. 发明专利

DE68927907T2 未知
公开(公告)号：DE68927907T2
公开(公告)日：1997-10-09
申请号：DE68927907
申请日：1989-09-29
申请人： HITACHI LTD
发明人： SAWASE TERUMI , HAGIWARA YOSHIMUNE , NAKAMURA HIDEO , HATORI HIROYUKI , BABA SHIROU , AKAO YASUSHI
IPC分类号： G06F9/24 , G06F9/38 , G06F11/267 , G06F15/78
摘要： A single chip microcomputer comprises a control circuit (12a, 12b), a processing circuit (13a, 13b) and a plurality of address register - status register pairs. A logical unit formed within the control circuit (12a, 12b) comprises an electrically writable non-volatile semiconductor memory device. Information can be externally written into the non-volatile semiconductor memory included in the logical unit, and the plurality of address register - status register pairs can be arbitrarily selected. As a result, logic function of the logical unit can be arbitrarily established in accordance with externally supplied information. Demanded specifications of various users can be satisfied by the logic function thus arbitrarily formed.

3. 发明专利

HK1003582A1 Single chip microcomputer 未知
公开(公告)号：HK1003582A1
公开(公告)日：1998-10-30
申请号：HK98102616
申请日：1998-03-27
申请人： HITACHI LTD
发明人： SAWASE TERUMI , HAGIWARA YOSHIMUNE , NAKAMURA HIDEO , HATORI HIROYUKI , BABA SHIROU , AKAO YASUSHI
IPC分类号： G06F9/24 , G06F9/38 , G06F11/267 , G06F15/78 , G06F
摘要： A single chip microcomputer comprises a control circuit (12a, 12b), a processing circuit (13a, 13b) and a plurality of address register - status register pairs. A logical unit formed within the control circuit (12a, 12b) comprises an electrically writable non-volatile semiconductor memory device. Information can be externally written into the non-volatile semiconductor memory included in the logical unit, and the plurality of address register - status register pairs can be arbitrarily selected. As a result, logic function of the logical unit can be arbitrarily established in accordance with externally supplied information. Demanded specifications of various users can be satisfied by the logic function thus arbitrarily formed.

4. 发明专利

DE3856139D1 未知
公开(公告)号：DE3856139D1
公开(公告)日：1998-04-09
申请号：DE3856139
申请日：1988-11-02
申请人： HITACHI LTD , HITACHI VLSI ENG , HITACHI MICROCOMPUTER SYST
发明人： NOGUCHI KOUKI , TSUCHIYA FUMIO , TSUKAMOTO TAKASHI , MASUMURA SHIGEKI , NAKAMURA HIDEO , BABA SHIRO , HAGIWARA YOSHIMUNE
IPC分类号： G06F9/22 , G06F9/26 , G06F9/30
摘要： In a microprocessor, a minimum instruction code length is set to a predetermined number of bits (e.g. one byte) length, an instruction set which can expand the instruction code length at a unit of the predetermined number of bits is used, an operand addressing mode and a type of operation for an operand are designated by separate predetermined number of code bits which are coded in a common coding scheme so that an instruction decoder is shared by those codes.

5. 发明专利

DE2935104A1 未知
公开(公告)号：DE2935104A1
公开(公告)日：1980-03-13
申请号：DE2935104
申请日：1979-08-30
申请人： HITACHI LTD
发明人： HAGIWARA YOSHIMUNE , SAWASE TERUMI , TAKAI ATSUSHI , KITA YUZO , HONDA AKIRA
IPC分类号： H03J5/02 , H03J5/00
摘要： A television receiver of electronic tuning type employing a variable capacitance diode in a local oscillator of its tuning circuit, which comprises a memory storing a plurality of digital data indicative of tuning voltages corresponding to a plurality of channels respectively so that a tuning voltage corresponding to a selected channel can be applied to the variable capacitance diode in the tuning circuit, a D/A converter converting a digital data corresponding to a selected channel into an analog voltage to be supplied to the variable capacitance diode, and a tuning voltage control circuit which functions to sequentially modify, at a predetermined rate, the digital data of the selected channel read out from the memory until the tuning point is reached in the tuning circuit, and which applies sequentially such a signal to the D/A converter, whereby the tuning circuit can be tuned to the selected channel regardless of secular and other variations in the operating characteristic of the variable capacitance diode.

6. 发明专利

DE68927907D1 未知
公开(公告)号：DE68927907D1
公开(公告)日：1997-04-30
申请号：DE68927907
申请日：1989-09-29
申请人： HITACHI LTD
发明人： SAWASE TERUMI , HAGIWARA YOSHIMUNE , NAKAMURA HIDEO , HATORI HIROYUKI , BABA SHIROU , AKAO YASUSHI
IPC分类号： G06F9/24 , G06F9/38 , G06F11/267 , G06F15/78
摘要： A single chip microcomputer comprises a control circuit (12a, 12b), a processing circuit (13a, 13b) and a plurality of address register - status register pairs. A logical unit formed within the control circuit (12a, 12b) comprises an electrically writable non-volatile semiconductor memory device. Information can be externally written into the non-volatile semiconductor memory included in the logical unit, and the plurality of address register - status register pairs can be arbitrarily selected. As a result, logic function of the logical unit can be arbitrarily established in accordance with externally supplied information. Demanded specifications of various users can be satisfied by the logic function thus arbitrarily formed.

7. 发明专利

DE3852251T2 未知
公开(公告)号：DE3852251T2
公开(公告)日：1995-06-22
申请号：DE3852251
申请日：1988-09-08
申请人： HITACHI LTD
发明人： SAWASE TERUMI , NOGUCHI KOUKI , NAKAMURA HIDEO , AKAO YASUSHI , BABA SHIRO , HAGIWARA YOSHIMUNE
IPC分类号： G11C29/00 , G06F7/00 , G06F9/22 , G06F9/24 , G06F15/78 , G11C16/02 , G11C17/00
摘要： A logic circuit (6) built in a single-chip microprocessor is configured of electrically-programmable memory elements, and information is written into the memory elements from outside, whereby a logic circuit having any desired logical functions can be constructed. The writing operation of the memory elements can be executed in a short time, and a user can obtain the single-chip microprocessor having hardware of peculiar prescribed specifications, in a short period.

8. 发明专利

DE3177238D1 未知
公开(公告)号：DE3177238D1
公开(公告)日：1991-02-07
申请号：DE3177238
申请日：1981-10-27
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： HAGIWARA YOSHIMUNE , SUGIYAMA SHIZUO , MAEDA NARIMICHI , YUMOTO OSAMU , AKAZAWA TAKASHI , KOBAYASHI MASAHITO , KITA YASUHIRO , KITA YUZO
IPC分类号： G06F7/00 , G06F5/01 , G06F7/50 , G06F7/57 , G06F7/76 , G06F17/10 , G06F5/00 , H03M7/24
摘要： In a digital signal processor comprising interface means for data input/output with an external device; data buses (21, 22); data memories (5, 6); floating point multiplier (14) for adding exponent parts and multiplying mantissa parts of a pair of data applied; a floating adder/subtracter (15); an accumulator (16); a switching circuit (17) and a control circuit (4), the floating adder/subtracter comprising adjusting means (67 to 69, 63 to 65) for adjusting two floating point data; an adder (75) for adding the two adjusted mantissa parts of the two floating point data; a leftwards shift circuit (76) for shifting output data from the adder; a zero detector (79) to provide a first shift data signal; a correction circuit (85) and a control circuit (89) to generate an underflow signal and provide a normalized exponent part of the sum of the two data; a constant adder circuit (77) and a selector (81) for providing the shift circuit with a second shift data signal, or the first shift data signal depending on whether or not the underflow signal is generated.

9. 发明专利

DE3143223A1 未知
公开(公告)号：DE3143223A1
公开(公告)日：1982-05-19
申请号：DE3143223
申请日：1981-10-30
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： KOBAYASHI MASAHITO , MAEDA NARIMICHI , HAGIWARA YOSHIMUNE , AKAZAWA TAKASHI , SUGIYAMA SHIZUO
IPC分类号： G06F7/38 , G06F7/00 , G06F7/487 , G06F7/52 , G06F7/533 , G06F7/544 , G06F7/76

10. 发明专利

DE3856139T2 未知
公开(公告)号：DE3856139T2
公开(公告)日：1998-11-05
申请号：DE3856139
申请日：1988-11-02
申请人： HITACHI LTD , HITACHI VLSI ENG , HITACHI MICROCOMPUTER SYST
发明人： NOGUCHI KOUKI , TSUCHIYA FUMIO , TSUKAMOTO TAKASHI , MASUMURA SHIGEKI , NAKAMURA HIDEO , BABA SHIRO , HAGIWARA YOSHIMUNE
IPC分类号： G06F9/22 , G06F9/26 , G06F9/30
摘要： In a microprocessor, a minimum instruction code length is set to a predetermined number of bits (e.g. one byte) length, an instruction set which can expand the instruction code length at a unit of the predetermined number of bits is used, an operand addressing mode and a type of operation for an operand are designated by separate predetermined number of code bits which are coded in a common coding scheme so that an instruction decoder is shared by those codes.

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