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1. 发明专利

JPS5776635A Floating multiplying circuit 失效
标题翻译：浮动电路
公开(公告)号：JPS5776635A
公开(公告)日：1982-05-13
申请号：JP15205380
申请日：1980-10-31
申请人： Hitachi Denshi Ltd , Hitachi Ltd
发明人： KOBAYASHI SEIJI , MAEDA SHIGEMICHI , HAGIWARA YOSHIMUNE , AKAZAWA TAKASHI , SUGIYAMA SHIZUO
IPC分类号： G06F7/38 , G06F7/00 , G06F7/487 , G06F7/52 , G06F7/533 , G06F7/544 , G06F7/76
CPC分类号： G06F7/4876 , G06F7/49921 , G06F7/5443
摘要： PURPOSE: To handle a digit overflow in floating-point arithmetic at a high speed without performing program processing, by providing a digit overflow detection part to the mantissa part or exponential part of an input or an output and by driving a digit overflow correcting circuit by its detection signal.
CONSTITUTION: Twelve-bit mantissa data corresponding to mantissas M
1 and M
2 are applied as input signals l
1 and l
2 to a multiplying circuit 1, which outputs a multiplication result l
5 . Four-bit exponent data corresponding exponents e
1 and e
2 , on the other hand, are applied as input signals l
3 and l
4 to an adding circuit 2, which outputs a signal l
6 . Those input and output signals are represented by four- bit complements of "2", so restricted as indicated: -8≤l
3 , l
4 , l
6 ≤7. A correcting circuit 4 outputs a detection signal C
8 for detecting an exponent being 8, a signal CMC indicating an overflow of the high-order digit of an exponent, and a signal CMV indicating an overflow of the low-order digit of an exponent. Then, an arithmetic circuit II corrects an exponent and a mantissa in case of the overflow of the low-order digit of the exponent.
COPYRIGHT: (C)1982,JPO&Japio
摘要翻译：目的：为了在不执行程序处理的情况下以浮点运算来处理数字溢出，通过向输入或输出的尾数部分或指数部分提供数字溢出检测部分，并通过驱动数字溢出校正电路其检测信号。构成：对应于尾数M1和M2的十二位尾数数据作为输入信号l1和I2施加到乘法电路1，乘法电路1输出乘法结果15。另一方面，对应于指数e1和e2的四比特指数数据作为输入信号13和14施加到加法电路2，加法电路输出信号16。那些输入和输出信号由“2”的四位补码表示，因此受到限制：-8 <= 13，14，16 = 7。校正电路4输出用于检测指数为8的检测信号C8，指示指数的高位数字的溢出的信号CMC和指示指数的低位数字的溢出的信号CMV。然后，算术电路II在指数的低位数字的溢出的情况下校正指数和尾数。

2. 发明专利

JPS5776633A Signal processor 失效
标题翻译：信号处理器
公开(公告)号：JPS5776633A
公开(公告)日：1982-05-13
申请号：JP15205280
申请日：1980-10-31
申请人： Hitachi Denshi Ltd , Hitachi Ltd
发明人： SUGIYAMA SHIZUO , HAGIWARA YOSHIMUNE , MAEDA SHIGEMICHI , AKAZAWA TAKASHI , KOBAYASHI SEIJI , KITA YASUHIRO , KIDA YUUZOU
IPC分类号： G06F3/05 , G06F5/00 , G06F5/01 , G06F17/10
CPC分类号： G06F5/017
摘要： PURPOSE:To eliminate the limitations of the bit length and bit arrangement of an input signal by arranging the bits of the input signal inversely of the bit arrangement inputted to a shift register when the least significant digit bit arrives as an initial bit. CONSTITUTION:When the least significant digit bit LSB comes first, an AND circuit 206 is selected by a control signal 22. Input data stored in a shift register 209 with the LSB at the beginning is transmitted to a data bus output switching circuit 210. When the data is outputted to a line 25, the control signal 22 permits switching so that the 2 of the data bus 25 is assigned to the bit SR15 of the register, and the 2 to the bit SRO. When the most significant digit bit MSB comes first, an AND circuit 205 is signified and the input data is stored in the shift register 209 being shifted successively from the SRO to SR15. In this case, a bus output switching circuit 210 sends the output, as it is, without changing the bit arrangement.
摘要翻译：目的：为了消除输入信号的位长度和位排列的限制，通过将输入信号的位与输入到移位寄存器的比特排列相反，当最低有效位被作为初始位到达时。构成：当最低有效位LSB首先出现时，通过控制信号22选择与电路206.存储在移位寄存器209中的与开始的LSB的输入数据被发送到数据总线输出切换电路210.当数据被输出到行25，控制信号22允许切换，使得数据总线25的2 0被分配给寄存器的位SR15，而2 <15>分配给位SR0。当最高有效位MSB首先出现时，表示AND电路205，并且将输入数据存储在从SRO向SR15连续移位的移位寄存器209中。在这种情况下，总线输出切换电路210原样发送输出，而不改变位的布置。

3. 发明专利

JPS5776634A Digital signal processor 失效
标题翻译：数字信号处理器
公开(公告)号：JPS5776634A
公开(公告)日：1982-05-13
申请号：JP15205180
申请日：1980-10-31
申请人： Hitachi Denshi Ltd , Hitachi Ltd
发明人： HAGIWARA YOSHIMUNE , SUGIYAMA SHIZUO , MAEDA SHIGEMICHI , YUMOTO OSAMU , AKAZAWA TAKASHI , KOBAYASHI SEIJI , KITA YASUHIRO , KIDA YUUZOU
IPC分类号： G06F7/00 , G06F5/01 , G06F7/50 , G06F7/57 , G06F7/76 , G06F17/10
CPC分类号： G06F7/483 , G06F5/012 , G06F7/485 , G06F7/49921 , G06F2207/3856
摘要： PURPOSE: To process a digital signal of a voice, ec., in real time at a high speed, by exercising pipeline control under which multipliation, and addition and subtraction are performed in parallel.
CONSTITUTION: A floating-point arithmetic type multiplier 14 is supplied with an exponent display part from an X bus 21 and a mantissa display part from a Y bus 22. The multiplier 14 calculates and outputs the product of those two data to a P bus 24, and also outputs the exponent display part and mantissa a display part, which are not operated, to an X bus 25 and an Y bus 26 as they are. A floating- point arithmetic type adder-subtractor 15, on the other hand, inputs and operates output data X, Y and P of the multiplier 14 and data D and A of data 20 and 27, and outputs the results to an accumulator 16. Floating-point data latched in the accumulator 16 is outputted to an A bus 27 and a D bus 20 through a switch circuit 17. The arithmetic results of the multiplier 14 and adder-subtractor 15 are stored in a state code register and outputted from an output register 30 in parallel.
COPYRIGHT: (C)1982,JPO&Japio
摘要翻译：目的：通过执行并行执行乘法和加法和减法的流水线控制，以高速实时处理语音的数字信号。构成：浮点运算型乘法器14从X总线21的指数显示部分和Y总线22的尾数显示部分提供。乘法器14计算并将这两个数据的乘积输出到P总线24 并且还将X指令显示部分和尾数未被操作的显示部分原样输出到X总线25和Y总线26。另一方面，浮点运算型加减法器15输入并运算乘法器14的输出数据X，Y和P，以及数据20和27的数据D和A，并将结果输出到累加器16。锁存在累加器16中的浮点数据通过开关电路17输出到A总线27和D总线20.乘法器14和加减法器15的算术结果存储在状态码寄存器中，并从输出寄存器30并联。

4. 发明专利

DE3176788D1 HIGH SPEED DIGITAL PROCESSOR 未知
公开(公告)号：DE3176788D1
公开(公告)日：1988-07-21
申请号：DE3176788
申请日：1981-10-27
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： HAGIWARA YOSHIMUNE , SUGIYAMA SHIZUO , MAEDA NARIMICHI , YUMOTO OSAMU , AKAZAWA TAKASHI , KOBAYASHI MASAHITO , KITA YASUHIRO , KITA YUZO
IPC分类号： G06F7/00 , G06F5/01 , G06F7/50 , G06F7/57 , G06F7/76 , G06F17/10 , G06F7/48 , G06F7/38
摘要： In a digital signal processor comprising interface means for data input/output with an external device; data buses (21, 22); data memories (5, 6); floating point multiplier (14) for adding exponent parts and multiplying mantissa parts of a pair of data applied; a floating adder/subtracter (15); an accumulator (16); a switching circuit (17) and a control circuit (4), the floating adder/subtracter comprising adjusting means (67 to 69, 63 to 65) for adjusting two floating point data; an adder (75) for adding the two adjusted mantissa parts of the two floating point data; a leftwards shift circuit (76) for shifting output data from the adder; a zero detector (79) to provide a first shift data signal; a correction circuit (85) and a control circuit (89) to generate an underflow signal and provide a normalized exponent part of the sum of the two data; a constant adder circuit (77) and a selector (81) for providing the shift circuit with a second shift data signal, or the first shift data signal depending on whether or not the underflow signal is generated.

5. 发明专利

DE3177238D1 未知
公开(公告)号：DE3177238D1
公开(公告)日：1991-02-07
申请号：DE3177238
申请日：1981-10-27
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： HAGIWARA YOSHIMUNE , SUGIYAMA SHIZUO , MAEDA NARIMICHI , YUMOTO OSAMU , AKAZAWA TAKASHI , KOBAYASHI MASAHITO , KITA YASUHIRO , KITA YUZO
IPC分类号： G06F7/00 , G06F5/01 , G06F7/50 , G06F7/57 , G06F7/76 , G06F17/10 , G06F5/00 , H03M7/24
摘要： In a digital signal processor comprising interface means for data input/output with an external device; data buses (21, 22); data memories (5, 6); floating point multiplier (14) for adding exponent parts and multiplying mantissa parts of a pair of data applied; a floating adder/subtracter (15); an accumulator (16); a switching circuit (17) and a control circuit (4), the floating adder/subtracter comprising adjusting means (67 to 69, 63 to 65) for adjusting two floating point data; an adder (75) for adding the two adjusted mantissa parts of the two floating point data; a leftwards shift circuit (76) for shifting output data from the adder; a zero detector (79) to provide a first shift data signal; a correction circuit (85) and a control circuit (89) to generate an underflow signal and provide a normalized exponent part of the sum of the two data; a constant adder circuit (77) and a selector (81) for providing the shift circuit with a second shift data signal, or the first shift data signal depending on whether or not the underflow signal is generated.

6. 发明专利

DE3143223A1 未知
公开(公告)号：DE3143223A1
公开(公告)日：1982-05-19
申请号：DE3143223
申请日：1981-10-30
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： KOBAYASHI MASAHITO , MAEDA NARIMICHI , HAGIWARA YOSHIMUNE , AKAZAWA TAKASHI , SUGIYAMA SHIZUO
IPC分类号： G06F7/38 , G06F7/00 , G06F7/487 , G06F7/52 , G06F7/533 , G06F7/544 , G06F7/76

7. 发明专利

JPS6312025A ADDING AND SUBTRACTING DEVICE 失效
公开(公告)号：JPS6312025A
公开(公告)日：1988-01-19
申请号：JP2459087
申请日：1987-02-06
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： HAGIWARA YOSHIMUNE , SUGIYAMA SHIZUO , MAEDA SHIGEMICHI , YUMOTO OSAMU , AKAZAWA TAKASHI , KOBAYASHI MASAHITO , KITA YASUHIRO , KIDA YUZO
IPC分类号： G06F7/485 , G06F7/00 , G06F7/50 , G06F7/508 , G06F7/527 , G06F7/76 , G06F17/10
摘要： PURPOSE:To process a digital signal at a real time at a high speed by providing a means to determine the number of the bit necessary to a shifting in accordance with the adding result and the data of the difference of the index displaying part of respective data. CONSTITUTION:An output gamma of a latch circuit 71 is inputted tone side input terminal of a constant adding circuit 77 and a subtracting circuit 78. A zero detecting circuit 79 to decide an output UM of an adder 75, when the output UM of an adder given by a complement displaying is a positive number, counts the continuous number of the '0' bit continuous to the sign bit at the upper-most order of the output UM. When the output UM is a negative number, the continuous number of the '1' bit continuous to the sign bit is counted. An output theta1 of the zero detecting circuit 79 is given through an output correcting circuit 80 provided for the regularization of the data and the overflowing countermeasure to a shifting circuit 76 and the number of the shifting bit of the data by the shifting circuit is determined. Thus, the digital signal can be processed at a high speed.

8. 发明专利

JPS6195652A Digital tone generating circuit 失效
标题翻译：数字音调发生电路
公开(公告)号：JPS6195652A
公开(公告)日：1986-05-14
申请号：JP21618984
申请日：1984-10-17
申请人： Hitachi Ltd
发明人： AKAZAWA TAKASHI
IPC分类号： H04Q1/45 , H03K4/02 , H04L27/26 , H04M1/50
摘要： PURPOSE: To form a staircase tone signal having a desired frequency by changing over a count of a program counter counting a reference frequency signal according to a key input signal into a correction value in a specific step.
CONSTITUTION: When one of key inputs 1∼4 is applied, an output of a gate circuit G2 brings logical 0 and a counter circuit CONT starts the count operation of a reference frequency ϕ. The key inputs 1∼4 and outputs 2∼32 of the circuit CONT are used to change an output Q of a flip-flop circuit 1 as logical 0 → logical 1 of circuit G2 → reset of circuit CONT → logical value 1 of ROM → logical 1 of circuit F1 synchronously with the frequency ϕ. Thus, a frequency division output of the frequency ϕ according to the frequency division ratio by the key inputs 1∼4 is obtained from the output Q, and a Jonson counter circuit J-CONT forms pulse signals delayed by a half period each by using the pulse A subjected to frequency division. Thus, a step tone signal is formed in this way.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过在特定步骤中将根据键输入信号计数参考频率信号的程序计数器的计数改变为校正值来形成具有期望频率的阶梯音信号。构成：当应用键输入1-4之一时，门电路G2的输出使逻辑0，并且计数电路CONT开始参考频率phi的计数操作。电路CONT的键输入1-4和输出2-32用于将触发器电路1的输出Q改变为电路ROM逻辑1的电路CONT逻辑值1的电路G2复位的逻辑0逻辑1 F1与频率phi同步。因此，从输出端Q获得根据键输入1-4的分频比的频率phi的分频输出，并且Jonson计数器电路J-CONT通过使用脉冲A进行分频。因此，以这种方式形成阶梯音信号。

9. 发明专利

JPS6195601A Cmos oscillating circuit 失效
标题翻译： CMOS振荡电路
公开(公告)号：JPS6195601A
公开(公告)日：1986-05-14
申请号：JP21618584
申请日：1984-10-17
申请人： Hitachi Ltd
发明人： AKAZAWA TAKASHI
IPC分类号： H03B5/32
摘要： PURPOSE: To widen the operating voltage range by using P-channel and N- channel MOSFETs connected in parallel taking a power supply voltage or a common potential as a reference voltage and activated at a constant voltage as a feedback resistor means of a CMOS amplifier circuit.
CONSTITUTION: An input and an output of a CMOS inverter circuit IV acting like an inverse amplifier are connected respectively to external terminals P1, P2, which are connected to externally mounted capacitors with respect to the common potential. Further, a crystal oscillator X is connected between the terminals P1 and P2. As the feedback resistor of the inverter circuit IV, the N-channel MOSFETQ1 and a P-channel MOSFETQ2 connected in parallel are provided, which are activated by a constant voltage circuit comprising MOSFETs Q3∼Q8. Thus, the operating voltage of the inverter circuit IV is made nearly constant independently of the fluctuation of the power supply voltage and a stable oscillation output is obtained.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过使用并联连接的P沟道和N沟道MOSFET来扩展工作电压范围，将电源电压或公共电位作为参考电压，并以恒定电压激活，作为CMOS放大器电路的反馈电阻器。构成：像反向放大器那样的CMOS反相器电路IV的输入和输出分别连接到相对于共同电位连接到外部安装的电容器的外部端子P1，P2。此外，晶体振荡器X连接在端子P1和P2之间。作为反相器电路IV的反馈电阻，提供并联连接的N沟道MOSFETQ1和P沟道MOSFETQ2，其由包括MOSFET Q3-Q8的恒定电压电路激活。因此，与电源电压的波动无关地使逆变器电路IV的工作电压保持不变，得到稳定的振荡输出。

10. 发明专利

JPS60167342A AGING DEVICE 失效
公开(公告)号：JPS60167342A
公开(公告)日：1985-08-30
申请号：JP2162684
申请日：1984-02-10
申请人： HITACHI LTD
发明人： AKAZAWA TAKASHI
IPC分类号： H01L21/66
摘要： PURPOSE:To effectively utilize the aging time of ICs by a method wherein a proper screening inspection of the ICs is contrived so as to be able to perform during the aging time, and at the same time, some ICs determined to be defective are made to be destroyed during the aging time. CONSTITUTION:Aging substrates 2, on each of which plural ICs 3 have been set, are housed in an aging stove, and at the same time, a tester 16 and a breaking unit 17 are respectively connected to the prescribed connector parts of the aging substrates 2. A test signal is inputted in each IC3 from the tester 16 through connector parts 15 for each signal and wirings 14 for each signal and the desired screening inspection of the ICs 3 is performed. During such the test, the tester 16 performs a decision on non-defective and defective of each IC3 on the basis of the response signal, which is sent from each IC3, specifies the positions of defective ICs 3 decided to be a defective on the aging substrates 2 and gives a breaking instruction to the breaking unit 17. The breaking unit 17 changes over a first and a second change-over switches 8 and 9 corresponding to an appointed position on the basis of the breaking instruction, turns off a third and a fourth wirings 6 and 7, impresses a reverse bias on the defective IC3 through the two wirings 6 and 7 and makes the defective IC3 destroy electrically.

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