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1. 发明授权

US08541830B1 Nonvolatile semiconductor memory device and method for manufacturing the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08541830B1
公开(公告)日：2013-09-24
申请号：US13601468
申请日：2012-08-31
申请人： Satoshi Nagashima , Fumitaka Arai , Hisataka Meguro
发明人： Satoshi Nagashima , Fumitaka Arai , Hisataka Meguro
IPC分类号： H01L29/788 , H01L21/336 , G11C11/34
CPC分类号： H01L27/088 , H01L21/28273 , H01L27/11524 , H01L27/11551 , H01L29/788 , H01L29/7881
摘要： A nonvolatile semiconductor memory device according to an embodiment includes a plurality of cell array layers, each cell array layer including: a plurality of semiconductor layers that extends in a first direction; gate insulating layers; a plurality of floating gates arranged in the first direction; inter-gate insulating layers; and a plurality of control gates that extends in a second direction intersecting semiconductor layers, and faces the floating gates via the inter-gate insulating layers, in which, in the cell array layers adjacent each other in a stacking direction, the control gates of a lower cell array layer and the control gates of the an upper cell array layer are intersecting each other, and the floating gates within the lower cell array layer and the semiconductor layers within the upper cell array layer are aligned in position with each other.
摘要翻译：根据实施例的非易失性半导体存储器件包括多个单元阵列层，每个单元阵列层包括：沿第一方向延伸的多个半导体层; 栅绝缘层; 沿所述第一方向布置的多个浮动栅极; 栅极间绝缘层; 以及多个控制栅极，其在与半导体层交叉的第二方向上延伸，并且经由所述栅极间绝缘层面向所述浮置栅极，其中，在层叠方向上彼此相邻的所述单元阵列层中，所述控制栅极下单元阵列层和上单元阵列层的控制栅极彼此相交，并且下单元阵列层内的浮置栅极和上单元阵列层内的半导体层彼此对准。

2. 发明授权

US07868376B2 Semiconductor storage device and method for manufacturing the same 失效
公开(公告)号：US07868376B2
公开(公告)日：2011-01-11
申请号：US12354271
申请日：2009-01-15
申请人： Kenji Aoyama , Hisataka Meguro , Satoshi Nagashima
发明人： Kenji Aoyama , Hisataka Meguro , Satoshi Nagashima
IPC分类号： H01L29/792
CPC分类号： H01L21/28247 , H01L21/76229 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A semiconductor storage device has a plurality of word lines formed with a predetermined interval on a semiconductor substrate, a selection transistor provided at an end portion of the plurality of word lines, a first insulating film formed so as to cover side surfaces of the word lines, a side surface of the selection transistor, and a surface of the semiconductor substrate between the word lines, a high-permittivity film formed on the first insulation film, a second insulating film formed so as to cover the upper surface of the word lines and the selection transistor, a first air-gap portion located between the word lines and surrounded by the high-permittivity film and the second insulating film, and a second air-gap portion formed via the first insulating film and the high-permittivity film at a sidewall portion, which opposes the selection transistor, of the word line adjacent to the selection transistor, an upper portion of the second air-gap portion being covered by the second insulating film.

3. 发明申请

US20090218614A1 SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20090218614A1
公开(公告)日：2009-09-03
申请号：US12354271
申请日：2009-01-15
申请人： Kenji AOYAMA , Hisataka Meguro , Satoshi Nagashima
发明人： Kenji AOYAMA , Hisataka Meguro , Satoshi Nagashima
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L21/28247 , H01L21/76229 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A semiconductor storage device has a plurality of word lines formed with a predetermined interval on a semiconductor substrate, a selection transistor provided at an end portion of the plurality of word lines, a first insulating film formed so as to cover side surfaces of the word lines, a side surface of the selection transistor, and a surface of the semiconductor substrate between the word lines, a high-permittivity film formed on the first insulation film, a second insulating film formed so as to cover the upper surface of the word lines and the selection transistor, a first air-gap portion located between the word lines and surrounded by the high-permittivity film and the second insulating film, and a second air-gap portion formed via the first insulating film and the high-permittivity film at a sidewall portion, which opposes the selection transistor, of the word line adjacent to the selection transistor, an upper portion of the second air-gap portion being covered by the second insulating film.
摘要翻译：半导体存储装置具有在半导体衬底上形成有预定间隔的多个字线，设置在多个字线的端部的选择晶体管，形成为覆盖字线的侧面的第一绝缘膜所述选择晶体管的侧面以及所述字线之间的所述半导体基板的表面，形成在所述第一绝缘膜上的高电容率膜，形成为覆盖所述字线的上表面的第二绝缘膜，以及选择晶体管，位于字线之间并被高电容率膜和第二绝缘膜包围的第一气隙部分和经由第一绝缘膜和高介电常数膜形成的第二气隙部分，与选择晶体管相邻的字线相对的选择晶体管的侧壁部分，第二气隙部分的上部被第二i 记录膜。

4. 发明授权

US08592885B2 Nonvolatile semiconductor memory device and method for manufacturing the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08592885B2
公开(公告)日：2013-11-26
申请号：US13365470
申请日：2012-02-03
申请人： Shigeru Kinoshita , Hisataka Meguro , Minori Kajimoto
发明人： Shigeru Kinoshita , Hisataka Meguro , Minori Kajimoto
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/28273 , H01L29/42336 , H01L29/66825
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a tunneling insulating film, a floating gate, a leak suppression unit, an inter-gate insulating film, and a control gate. The substrate includes silicon. The tunneling insulating film is provided on the substrate. The floating gate is provided on the tunneling insulating film. The leak suppression unit is provided on the floating gate. The inter-gate insulating film is provided on the leak suppression unit. The control gate is provided on the inter-gate insulating film. The dielectric constant of the leak suppression unit is higher than a dielectric constant of the inter-gate insulating film.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括衬底，隧道绝缘膜，浮动栅极，泄漏抑制单元，栅极间绝缘膜和控制栅极。衬底包括硅。隧道绝缘膜设置在基板上。浮动栅极设置在隧道绝缘膜上。泄漏抑制单元设置在浮动栅极上。栅极间绝缘膜设置在泄漏抑制单元上。控制栅极设置在栅极间绝缘膜上。泄漏抑制单元的介电常数高于栅极间绝缘膜的介电常数。

5. 发明申请

US20110097887A1 Semiconductor storage device and method for manufacturing the same 失效
公开(公告)号：US20110097887A1
公开(公告)日：2011-04-28
申请号：US12926677
申请日：2010-12-03
申请人： Kenji Aoyama , Hisataka Meguro , Satoshi Nagashima
发明人： Kenji Aoyama , Hisataka Meguro , Satoshi Nagashima
IPC分类号： H01L21/28
CPC分类号： H01L21/28247 , H01L21/76229 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A semiconductor storage device has a plurality of word lines formed with a predetermined interval on a semiconductor substrate, a selection transistor provided at an end portion of the plurality of word lines, a first insulating film formed so as to cover side surfaces of the word lines, a side surface of the selection transistor, and a surface of the semiconductor substrate between the word lines, a high-permittivity film formed on the first insulation film, a second insulating film formed so as to cover the upper surface of the word lines and the selection transistor, a first air-gap portion located between the word lines and surrounded by the high-permittivity film and the second insulating film, and a second air-gap portion formed via the first insulating film and the high-permittivity film at a sidewall portion, which opposes the selection transistor, of the word line adjacent to the selection transistor, an upper portion of the second air-gap portion being covered by the second insulating film.

6. 发明授权

US07718483B2 Method of manufacturing non-volatile semiconductor memory 失效
标题翻译：制造非易失性半导体存储器的方法
公开(公告)号：US07718483B2
公开(公告)日：2010-05-18
申请号：US11399655
申请日：2006-04-07
申请人： Ichiro Mizushima , Hajime Nagano , Yoshio Ozawa , Hisataka Meguro , Takashi Suzuki
发明人： Ichiro Mizushima , Hajime Nagano , Yoshio Ozawa , Hisataka Meguro , Takashi Suzuki
IPC分类号： H01L21/8238
CPC分类号： H01L27/115 , H01L21/76229 , H01L27/1052 , H01L27/11521
摘要： In a method for manufacturing a non-volatile semiconductor device according to this invention, steps are provided for forming a plurality of first semiconductor portions over a substrate; selectively growing a plurality of second semiconductor portions in contacting with said plurality of first semiconductor portions respectively; partially removing said plurality of second semiconductor portions to prepare a plurality of floating gates with substantially flat surfaces; forming an insulating layer over said plurality of floating gates; and forming a control gate over said insulating layer.
摘要翻译：在根据本发明的用于制造非易失性半导体器件的方法中，提供了用于在衬底上形成多个第一半导体部分的步骤; 选择性地生长与所述多个第一半导体部分接触的多个第二半导体部分; 部分地去除所述多个第二半导体部分以制备具有基本平坦表面的多个浮动栅极; 在所述多个浮动栅极上形成绝缘层; 以及在所述绝缘层上形成控制栅极。

7. 发明申请

US20060258076A1 Method of manufacturing non-volatile semiconductor memory 失效
标题翻译：制造非易失性半导体存储器的方法
公开(公告)号：US20060258076A1
公开(公告)日：2006-11-16
申请号：US11399655
申请日：2006-04-07
申请人： Ichiro Mizushima , Hajime Nagano , Yoshio Ozawa , Hisataka Meguro , Takashi Suzuki
发明人： Ichiro Mizushima , Hajime Nagano , Yoshio Ozawa , Hisataka Meguro , Takashi Suzuki
IPC分类号： H01L21/8238
CPC分类号： H01L27/115 , H01L21/76229 , H01L27/1052 , H01L27/11521
摘要： In a method for manufacturing a non-volatile semiconductor device according to this invention, steps are provided for forming a plurality of first semiconductor portions over a substrate; selectively growing a plurality of second semiconductor portions in contacting with said plurality of first semiconductor portions respectively; partially removing said plurality of second semiconductor portions to prepare a plurality of floating gates with substantially flat surfaces; forming an insulating layer over said plurality of floating gates; and forming a control gate over said insulating layer.
摘要翻译：在根据本发明的用于制造非易失性半导体器件的方法中，提供了用于在衬底上形成多个第一半导体部分的步骤; 选择性地生长与所述多个第一半导体部分接触的多个第二半导体部分; 部分地去除所述多个第二半导体部分以制备具有基本平坦表面的多个浮动栅极; 在所述多个浮动栅极上形成绝缘层; 以及在所述绝缘层上形成控制栅极。

8. 发明授权

US06878985B2 Nonvolatile semiconductor memory device having a memory cell that includes a floating gate electrode and control gate electrode 失效
标题翻译：具有包括浮置栅电极和控制栅电极的存储单元的非易失性半导体存储器件
公开(公告)号：US06878985B2
公开(公告)日：2005-04-12
申请号：US10382772
申请日：2003-03-07
申请人： Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Akira Shimizu , Yasuhiko Matsunaga , Masayuki Ichige , Hisataka Meguro
发明人： Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Akira Shimizu , Yasuhiko Matsunaga , Masayuki Ichige , Hisataka Meguro
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115
摘要： Element isolation insulating layers have an STI structure, and their upper surfaces are flat. A floating gate electrode is formed in a recess which is formed by projections of the element isolation insulating layers. The two opposing side surfaces of the floating gate electrode are covered with the element isolation insulating layers. The upper surface of the floating gate electrode is substantially leveled with the upper surfaces of the element isolation insulating layers. A gate insulating layer is formed on the floating gate electrode and element isolation insulating layers. The underlayer of this gate insulating layer is flat. A control gate electrode is formed on the gate insulating layer.
摘要翻译：元件隔离绝缘层具有STI结构，其上表面是平坦的。浮栅电极形成在由元件隔离绝缘层的突起形成的凹部中。浮置栅电极的两个相对的侧表面被元件隔离绝缘层覆盖。浮栅电极的上表面与元件隔离绝缘层的上表面基本平齐。在浮栅电极和元件隔离绝缘层上形成栅极绝缘层。该栅极绝缘层的底层是平坦的。在栅极绝缘层上形成控制栅电极。

9. 发明授权

US06235589B1 Method of making non-volatile memory with polysilicon spacers 失效
标题翻译：制造具有多晶硅间隔物的非易失性存储器的方法
公开(公告)号：US06235589B1
公开(公告)日：2001-05-22
申请号：US09494435
申请日：2000-01-31
申请人： Hisataka Meguro
发明人： Hisataka Meguro
IPC分类号： H01L218247
CPC分类号： H01L27/11521
摘要： Sidewall spacers comprised of a second polycrystalline silicon film are formed on the sides of a first polycrystalline silicon film in such a way that a relationship of b≦a=x
摘要翻译：在第一多晶硅膜的侧面上形成由第二多晶硅膜构成的侧壁间隔物，其中满足b <= a = x

10. 发明申请

US20120217569A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20120217569A1
公开(公告)日：2012-08-30
申请号：US13365470
申请日：2012-02-03
申请人： Shigeru KINOSHITA , Hisataka Meguro , Minori Kajimoto
发明人： Shigeru KINOSHITA , Hisataka Meguro , Minori Kajimoto
IPC分类号： H01L29/788 , H01L21/28
CPC分类号： H01L21/28273 , H01L29/42336 , H01L29/66825
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a tunneling insulating film, a floating gate, a leak suppression unit, an inter-gate insulating film, and a control gate. The substrate includes silicon. The tunneling insulating film is provided on the substrate. The floating gate is provided on the tunneling insulating film. The leak suppression unit is provided on the floating gate. The inter-gate insulating film is provided on the leak suppression unit. The control gate is provided on the inter-gate insulating film. The dielectric constant of the leak suppression unit is higher than a dielectric constant of the inter-gate insulating film.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括衬底，隧道绝缘膜，浮动栅极，泄漏抑制单元，栅极间绝缘膜和控制栅极。衬底包括硅。隧道绝缘膜设置在基板上。浮动栅极设置在隧道绝缘膜上。泄漏抑制单元设置在浮动栅极上。栅极间绝缘膜设置在泄漏抑制单元上。控制栅极设置在栅极间绝缘膜上。泄漏抑制单元的介电常数高于栅极间绝缘膜的介电常数。

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