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1. 发明授权

US06878985B2 Nonvolatile semiconductor memory device having a memory cell that includes a floating gate electrode and control gate electrode 失效
标题翻译：具有包括浮置栅电极和控制栅电极的存储单元的非易失性半导体存储器件
公开(公告)号：US06878985B2
公开(公告)日：2005-04-12
申请号：US10382772
申请日：2003-03-07
申请人： Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Akira Shimizu , Yasuhiko Matsunaga , Masayuki Ichige , Hisataka Meguro
发明人： Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Akira Shimizu , Yasuhiko Matsunaga , Masayuki Ichige , Hisataka Meguro
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115
摘要： Element isolation insulating layers have an STI structure, and their upper surfaces are flat. A floating gate electrode is formed in a recess which is formed by projections of the element isolation insulating layers. The two opposing side surfaces of the floating gate electrode are covered with the element isolation insulating layers. The upper surface of the floating gate electrode is substantially leveled with the upper surfaces of the element isolation insulating layers. A gate insulating layer is formed on the floating gate electrode and element isolation insulating layers. The underlayer of this gate insulating layer is flat. A control gate electrode is formed on the gate insulating layer.
摘要翻译：元件隔离绝缘层具有STI结构，其上表面是平坦的。浮栅电极形成在由元件隔离绝缘层的突起形成的凹部中。浮置栅电极的两个相对的侧表面被元件隔离绝缘层覆盖。浮栅电极的上表面与元件隔离绝缘层的上表面基本平齐。在浮栅电极和元件隔离绝缘层上形成栅极绝缘层。该栅极绝缘层的底层是平坦的。在栅极绝缘层上形成控制栅电极。

2. 发明授权

US08541830B1 Nonvolatile semiconductor memory device and method for manufacturing the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08541830B1
公开(公告)日：2013-09-24
申请号：US13601468
申请日：2012-08-31
申请人： Satoshi Nagashima , Fumitaka Arai , Hisataka Meguro
发明人： Satoshi Nagashima , Fumitaka Arai , Hisataka Meguro
IPC分类号： H01L29/788 , H01L21/336 , G11C11/34
CPC分类号： H01L27/088 , H01L21/28273 , H01L27/11524 , H01L27/11551 , H01L29/788 , H01L29/7881
摘要： A nonvolatile semiconductor memory device according to an embodiment includes a plurality of cell array layers, each cell array layer including: a plurality of semiconductor layers that extends in a first direction; gate insulating layers; a plurality of floating gates arranged in the first direction; inter-gate insulating layers; and a plurality of control gates that extends in a second direction intersecting semiconductor layers, and faces the floating gates via the inter-gate insulating layers, in which, in the cell array layers adjacent each other in a stacking direction, the control gates of a lower cell array layer and the control gates of the an upper cell array layer are intersecting each other, and the floating gates within the lower cell array layer and the semiconductor layers within the upper cell array layer are aligned in position with each other.
摘要翻译：根据实施例的非易失性半导体存储器件包括多个单元阵列层，每个单元阵列层包括：沿第一方向延伸的多个半导体层; 栅绝缘层; 沿所述第一方向布置的多个浮动栅极; 栅极间绝缘层; 以及多个控制栅极，其在与半导体层交叉的第二方向上延伸，并且经由所述栅极间绝缘层面向所述浮置栅极，其中，在层叠方向上彼此相邻的所述单元阵列层中，所述控制栅极下单元阵列层和上单元阵列层的控制栅极彼此相交，并且下单元阵列层内的浮置栅极和上单元阵列层内的半导体层彼此对准。

3. 发明申请

US20100295134A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20100295134A1
公开(公告)日：2010-11-25
申请号：US12560313
申请日：2009-09-15
申请人： Satoshi Nagashima , Fumitaka Arai , Hisataka Meguro , Hiroshi Akahori
发明人： Satoshi Nagashima , Fumitaka Arai , Hisataka Meguro , Hiroshi Akahori
IPC分类号： H01L27/11 , H01L21/8239
CPC分类号： H01L27/11524 , H01L27/11519 , H01L27/11521
摘要： A semiconductor memory device according to one embodiment includes: a semiconductor substrate having an active region divided by an element isolation region; a plurality of stacked-gate type memory cell transistors connected in series on the active region; select transistors connected to both ends of the plurality of memory cell transistors on the active region; and a bit line contact connected to a drain region belonging to the select transistor in the active region, a vertical cross sectional shape of a lower portion of the bit line contact in a channel width direction of the plurality of memory cell transistors being in a skirt shape.
摘要翻译：根据一个实施例的半导体存储器件包括：半导体衬底，其具有由元件隔离区域划分的有源区域; 在有源区上串联连接的多个堆叠栅型存储单元晶体管; 连接到有源区上的多个存储单元晶体管的两端的选择晶体管; 以及与有源区域中属于选择晶体管的漏极区域连接的位线接触部，位于多个存储单元晶体管的沟道宽度方向上的位线接触的下部的垂直截面形状位于裙部形状。

4. 发明申请

US20070187743A1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070187743A1
公开(公告)日：2007-08-16
申请号：US11656382
申请日：2007-01-23
申请人： Shoichi Miyazaki , Hisataka Meguro , Fumitaka Arai
发明人： Shoichi Miyazaki , Hisataka Meguro , Fumitaka Arai
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A semiconductor device includes a pair of select gate structures which are opposed to each other and which are formed in a select transistor formation area, each of the select gate structures including a gate insulating film formed on a semiconductor substrate and a gate electrode formed on the gate insulating film, and a pair of memory cell gate structure groups which are formed in a pair of memory cell formation areas between which the select transistor formation area is interposed and each of which has a plurality of memory cell gate structures arranged at the same pitch, the pair of select gate structures having sides which are opposed to each other, and at least the upper portion of each of the opposed sides of the select gate structures being inclined.
摘要翻译：半导体器件包括彼此相对并且形成在选择晶体管形成区域中的一对选择栅极结构，每个选择栅极结构包括形成在半导体衬底上的栅极绝缘膜和形成在栅极电极上的栅电极栅极绝缘膜和一对存储单元栅极结构组，其形成在一对存储单元形成区域中，在该对存储单元形成区域之间插入选择晶体管形成区域，并且每个存储单元栅极结构组具有以相同间距排列的多个存储单元栅极结构所述一对选择栅极结构具有彼此相对的侧面，并且至少所述选择栅极结构的每个相对侧的上部是倾斜的。

5. 发明授权

US09059035B2 Nonvolatile semiconductor device and its manufacturing method having memory cells with multiple layers 有权
标题翻译：非易失性半导体器件及其具有多层存储单元的制造方法
公开(公告)号：US09059035B2
公开(公告)日：2015-06-16
申请号：US13606757
申请日：2012-09-07
申请人： Satoshi Nagashima , Fumitaka Arai , Hisataka Meguro
发明人： Satoshi Nagashima , Fumitaka Arai , Hisataka Meguro
IPC分类号： H01L29/788 , H01L27/115 , H01L21/28 , H01L29/66 , H01L29/423 , G11C16/04
CPC分类号： H01L21/28273 , G11C16/0408 , H01L27/11524 , H01L27/11551 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： A nonvolatile semiconductor memory device a first memory cell array layer, a first insulation layer formed on top of the first memory cell array layer, a second memory cell array layer formed on the first insulation layer, and a control gate. The first and second memory cell array layers have first and second NAND cell units provided with multiple first and second memory cells connected in series in a first direction and the first and second selection gates connected at both ends of the multiple first and second memory cells. The control gate is formed via an insulation layer between gates of the memory cells on both sides thereof in the first direction, and extends in the second direction perpendicular to the first direction.
摘要翻译：非易失性半导体存储器件，第一存储单元阵列层，形成在第一存储单元阵列层顶部的第一绝缘层，形成在第一绝缘层上的第二存储单元阵列层和控制栅极。第一和第二存储单元阵列层具有第一和第二NAND单元单元，其具有在第一方向上串联连接的多个第一和第二存储单元，并且第一和第二选择栅极连接在多个第一和第二存储单元的两端。控制栅极是通过在其第一方向的两侧的存储单元的栅极之间的绝缘层形成的，并且在垂直于第一方向的第二方向上延伸。

6. 发明授权

US08624317B2 Nonvolatile semiconductor memory device and method for manufacturing same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08624317B2
公开(公告)日：2014-01-07
申请号：US13402477
申请日：2012-02-22
申请人： Fumitaka Arai , Satoshi Nagashima , Hisataka Meguro , Hideto Takekida , Kenta Yamada
发明人： Fumitaka Arai , Satoshi Nagashima , Hisataka Meguro , Hideto Takekida , Kenta Yamada
IPC分类号： H01L29/792
CPC分类号： H01L27/11524 , G11C16/0466 , H01L27/11551 , H01L29/66825 , H01L29/7881
摘要： Nonvolatile semiconductor memory device includes first memory cell array layer, first insulating layer formed thereabove, and second memory cell array layer formed thereabove. First memory cell array layer includes first NAND cell units each including plural first memory cells. The first memory cell includes first semiconductor layer, first gate insulating film formed thereabove, and first charge accumulation layer formed thereabove. The second memory cell array layer includes second NAND cell units each including plural second memory cells. The second memory cell includes second charge accumulation layer, second gate insulating film formed thereabove, and second semiconductor layer formed thereabove. Control gates are formed, via an inter-gate insulating film, on first-direction both sides of the first and second charge accumulation layers positioned the latter above the former via the first insulating layer. The control gates extend in a second direction perpendicular to the first direction.
摘要翻译：非易失性半导体存储器件包括第一存储单元阵列层，形成在其上的第一绝缘层和形成在其上的第二存储单元阵列层。第一存储单元阵列层包括每个包括多个第一存储单元的第一NAND单元单元。第一存储单元包括形成在其上的第一半导体层，第一栅极绝缘膜和在其上形成的第一电荷累积层。第二存储单元阵列层包括每个包括多个第二存储单元的第二NAND单元单元。第二存储单元包括第二电荷累积层，在其上形成的第二栅极绝缘膜，以及在其上形成的第二半导体层。控制栅极经由栅极间绝缘膜，在第一和第二电荷累积层的第一方向两侧经由第一绝缘层位于前者之上。控制门在垂直于第一方向的第二方向延伸。

7. 发明申请

US20130228844A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20130228844A1
公开(公告)日：2013-09-05
申请号：US13601468
申请日：2012-08-31
申请人： Satoshi NAGASHIMA , Fumitaka Arai , Hisataka Meguro
发明人： Satoshi NAGASHIMA , Fumitaka Arai , Hisataka Meguro
IPC分类号： H01L27/088 , H01L21/28 , H01L29/788
CPC分类号： H01L27/088 , H01L21/28273 , H01L27/11524 , H01L27/11551 , H01L29/788 , H01L29/7881
摘要： A nonvolatile semiconductor memory device according to an embodiment includes a plurality of cell array layers, each cell array layer including: a plurality of semiconductor layers that extends in a first direction; gate insulating layers; a plurality of floating gates arranged in the first direction; inter-gate insulating layers; and a plurality of control gates that extends in a second direction intersecting semiconductor layers, and faces the floating gates via the inter-gate insulating layers, in which, in the cell array layers adjacent each other in a stacking direction, the control gates of a lower cell array layer and the control gates of the an upper cell array layer are intersecting each other, and the floating gates within the lower cell array layer and the semiconductor layers within the upper cell array layer are aligned in position with each other.
摘要翻译：根据实施例的非易失性半导体存储器件包括多个单元阵列层，每个单元阵列层包括：沿第一方向延伸的多个半导体层; 栅绝缘层; 沿所述第一方向布置的多个浮动栅极; 栅极间绝缘层; 以及多个控制栅极，其在与半导体层交叉的第二方向上延伸，并且经由所述栅极间绝缘层面向所述浮置栅极，其中，在层叠方向上彼此相邻的所述单元阵列层中，所述控制栅极下单元阵列层和上单元阵列层的控制栅极彼此相交，并且下单元阵列层内的浮置栅极和上单元阵列层内的半导体层彼此对准。

8. 发明授权

US07718474B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07718474B2
公开(公告)日：2010-05-18
申请号：US11656382
申请日：2007-01-23
申请人： Shoichi Miyazaki , Hisataka Meguro , Fumitaka Arai
发明人： Shoichi Miyazaki , Hisataka Meguro , Fumitaka Arai
IPC分类号： H01L21/335
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A semiconductor device includes a pair of select gate structures which are opposed to each other and which are formed in a select transistor formation area, each of the select gate structures including a gate insulating film formed on a semiconductor substrate and a gate electrode formed on the gate insulating film, and a pair of memory cell gate structure groups which are formed in a pair of memory cell formation areas between which the select transistor formation area is interposed and each of which has a plurality of memory cell gate structures arranged at the same pitch, the pair of select gate structures having sides which are opposed to each other, and at least the upper portion of each of the opposed sides of the select gate structures being inclined.
摘要翻译：半导体器件包括彼此相对并且形成在选择晶体管形成区域中的一对选择栅极结构，每个选择栅极结构包括形成在半导体衬底上的栅极绝缘膜和形成在栅极电极上的栅电极栅极绝缘膜和一对存储单元栅极结构组，其形成在一对存储单元形成区域中，在该对存储单元形成区域之间插入选择晶体管形成区域，并且每个存储单元栅极结构组具有以相同间距排列的多个存储单元栅极结构所述一对选择栅极结构具有彼此相对的侧面，并且至少所述选择栅极结构的每个相对侧的上部是倾斜的。

9. 发明申请

US20120217571A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20120217571A1
公开(公告)日：2012-08-30
申请号：US13402477
申请日：2012-02-22
申请人： Fumitaka ARAI , Satoshi Nagashima , Hisataka Meguro , Hideto Takekida , Kenta Yamada
发明人： Fumitaka ARAI , Satoshi Nagashima , Hisataka Meguro , Hideto Takekida , Kenta Yamada
IPC分类号： H01L29/792 , H01L21/76
CPC分类号： H01L27/11524 , G11C16/0466 , H01L27/11551 , H01L29/66825 , H01L29/7881
摘要： Nonvolatile semiconductor memory device includes first memory cell array layer, first insulating layer formed thereabove, and second memory cell array layer formed thereabove. First memory cell array layer includes first NAND cell units each including plural first memory cells. The first memory cell includes first semiconductor layer, first gate insulating film formed thereabove, and first charge accumulation layer formed thereabove. The second memory cell array layer includes second NAND cell units each including plural second memory cells. The second memory cell includes second charge accumulation layer, second gate insulating film formed thereabove, and second semiconductor layer formed thereabove. Control gates are formed, via an inter-gate insulating film, on first-direction both sides of the first and second charge accumulation layers positioned the latter above the former via the first insulating layer. The control gates extend in a second direction perpendicular to the first direction.
摘要翻译：非易失性半导体存储器件包括第一存储单元阵列层，形成在其上的第一绝缘层和形成在其上的第二存储单元阵列层。第一存储单元阵列层包括每个包括多个第一存储单元的第一NAND单元单元。第一存储单元包括形成在其上的第一半导体层，第一栅极绝缘膜和在其上形成的第一电荷累积层。第二存储单元阵列层包括每个包括多个第二存储单元的第二NAND单元单元。第二存储单元包括第二电荷累积层，在其上形成的第二栅极绝缘膜，以及在其上形成的第二半导体层。控制栅极经由栅极间绝缘膜，在第一和第二电荷累积层的第一方向两侧经由第一绝缘层位于前者之上。控制门在垂直于第一方向的第二方向延伸。

10. 发明申请

US20100176433A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100176433A1
公开(公告)日：2010-07-15
申请号：US12729383
申请日：2010-03-23
申请人： Shoichi Miyazaki , Hisataka Meguro , Fumitaka Arai
发明人： Shoichi Miyazaki , Hisataka Meguro , Fumitaka Arai
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A semiconductor device includes a pair of select gate structures which are opposed to each other and which are formed in a select transistor formation area, each of the select gate structures including a gate insulating film formed on a semiconductor substrate and a gate electrode formed on the gate insulating film, and a pair of memory cell gate structure groups which are formed in a pair of memory cell formation areas between which the select transistor formation area is interposed and each of which has a plurality of memory cell gate structures arranged at the same pitch, the pair of select gate structures having sides which are opposed to each other, and at least the upper portion of each of the opposed sides of the select gate structures being inclined.
摘要翻译：半导体器件包括彼此相对并且形成在选择晶体管形成区域中的一对选择栅极结构，每个选择栅极结构包括形成在半导体衬底上的栅极绝缘膜和形成在栅极电极上的栅电极栅极绝缘膜和一对存储单元栅极结构组，其形成在一对存储单元形成区域中，在该对存储单元形成区域之间插入选择晶体管形成区域，并且每个存储单元栅极结构组具有以相同间距排列的多个存储单元栅极结构所述一对选择栅极结构具有彼此相对的侧面，并且至少所述选择栅极结构的每个相对侧的上部是倾斜的。

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