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1. 发明授权

US08895952B2 Nonvolatile storage device 有权
标题翻译：非易失存储设备
公开(公告)号：US08895952B2
公开(公告)日：2014-11-25
申请号：US13404678
申请日：2012-02-24
申请人： Shigeki Kobayashi , Kazuhiko Yamamoto , Kenji Aoyama , Shigeto Oshino , Kei Watanabe , Shinichi Nakao , Satoshi Ishikawa , Takeshi Yamaguchi
发明人： Shigeki Kobayashi , Kazuhiko Yamamoto , Kenji Aoyama , Shigeto Oshino , Kei Watanabe , Shinichi Nakao , Satoshi Ishikawa , Takeshi Yamaguchi
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L27/2481 , H01L27/2409 , H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/149
摘要： A nonvolatile storage device is formed by laminating a plurality of memory cell arrays, the memory cell array including a plurality of word lines, a plurality of bit lines, and memory cells. The memory cell includes a current rectifying device and a variable resistance device, the variable resistance device includes a lower electrode, an upper electrode, and a resistance change layer including a conductive nano material formed between the lower electrode and the upper electrode, one of the variable resistance devices provided adjacent to each other in the laminating direction has titanium oxide (TiOx) between the resistance change layer and the lower electrode serving as a cathode, the other of the variable resistance devices provided adjacent to each other in the laminating direction has titanium oxide (TiOx) between the resistance change layer and the upper electrode serving as a cathode.
摘要翻译：通过层叠多个存储单元阵列形成非易失性存储装置，所述存储单元阵列包括多个字线，多个位线和存储单元。存储单元包括电流整流装置和可变电阻装置，可变电阻装置包括下电极，上电极和包括形成在下电极和上电极之间的导电纳米材料的电阻变化层，在层叠方向上彼此相邻设置的可变电阻装置在电阻变化层和作为阴极的下部电极之间具有钛氧化物（TiOx），另外在层叠方向上彼此相邻设置的可变电阻装置具有钛电阻变化层和作为阴极的上部电极之间的氧化物（TiOx）。

2. 发明授权

US08416603B2 Nonvolatile memory device 失效
标题翻译：非易失性存储器件
公开(公告)号：US08416603B2
公开(公告)日：2013-04-09
申请号：US12973064
申请日：2010-12-20
申请人： Kenji Aoyama , Kazuhiko Yamamoto
发明人： Kenji Aoyama , Kazuhiko Yamamoto
IPC分类号： G11C11/00 , H01L45/00
CPC分类号： B82Y30/00 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1226 , H01L45/149
摘要： According to one embodiment, a nonvolatile memory device includes a first conductive member and a second conductive member. The first conductive member extends in a first direction. The second conductive member extends in a second direction intersecting the first direction. A portion of the first conductive member connected to the second conductive member protrudes toward the second conductive member. A resistivity of the first conductive member in the first direction is lower than a resistivity of the first conductive member in a third direction of the protrusion of the first conductive member. A resistance value of the first conductive member in the third direction changes. A resistivity of the second conductive member in the second direction is lower than a resistivity of the second conductive member in the third direction. A resistance value of the second conductive member in the third direction changes.
摘要翻译：根据一个实施例，非易失性存储器件包括第一导电构件和第二导电构件。第一导电构件沿第一方向延伸。第二导电构件沿与第一方向相交的第二方向延伸。连接到第二导电构件的第一导电构件的一部分朝向第二导电构件突出。第一导电构件在第一方向上的电阻率低于第一导电构件在第一导电构件的突起的第三方向上的电阻率。第一导电构件在第三方向上的电阻值改变。第二导电构件在第二方向上的电阻率低于第二导电构件在第三方向上的电阻率。第二导电构件在第三方向上的电阻值改变。

3. 发明申请

US20120064693A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20120064693A1
公开(公告)日：2012-03-15
申请号：US13277261
申请日：2011-10-20
申请人： Kenji Aoyama
发明人： Kenji Aoyama
IPC分类号： H01L45/00
CPC分类号： H01L27/1021 , H01L27/24
摘要： A semiconductor memory device includes a word line interconnect layer having a plurality of word lines extending in a word line direction and a bit line interconnect layer having a plurality of bit lines extending in a bit line direction alternately stacked on a silicon substrate. A variable resistance film is disposed between the word line and the bit line. A first pin diode extending in the word line direction is provided between the word line and the variable resistance film, and a second pin diode extending in the bit line direction is provided between the bit line and the variable resistance film. A region of an upper surface of the pin diode other than an immediately underlying region of the variable resistance film is located lower than the immediately underlying region.
摘要翻译：半导体存储器件包括具有在字线方向上延伸的多个字线的字线互连层和具有交替层叠在硅衬底上的位线方向延伸的多个位线的位线互连层。可变电阻膜设置在字线和位线之间。在字线方向和可变电阻膜之间设置有沿字线方向延伸的第一PIN二极管，并且在位线和可变电阻膜之间设置沿位线方向延伸的第二pin二极管。引脚二极管的上表面的区域不同于可变电阻膜的紧邻下方区域的位置低于紧邻的下方区域。

4. 发明申请

US20120025159A1 NONVOLATILE MEMORY DEVICE 失效
标题翻译：非易失性存储器件
公开(公告)号：US20120025159A1
公开(公告)日：2012-02-02
申请号：US12973064
申请日：2010-12-20
申请人： Kenji AOYAMA , Kazuhiko Yamamoto
发明人： Kenji AOYAMA , Kazuhiko Yamamoto
IPC分类号： H01L45/00 , B82Y99/00
CPC分类号： B82Y30/00 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1226 , H01L45/149
摘要： According to one embodiment, a nonvolatile memory device includes a first conductive member and a second conductive member. The first conductive member extends in a first direction. The second conductive member extends in a second direction intersecting the first direction. A portion of the first conductive member connected to the second conductive member protrudes toward the second conductive member. A resistivity of the first conductive member in the first direction is lower than a resistivity of the first conductive member in a third direction of the protrusion of the first conductive member. A resistance value of the first conductive member in the third direction changes. A resistivity of the second conductive member in the second direction is lower than a resistivity of the second conductive member in the third direction. A resistance value of the second conductive member in the third direction changes.
摘要翻译：根据一个实施例，非易失性存储器件包括第一导电构件和第二导电构件。第一导电构件沿第一方向延伸。第二导电构件沿与第一方向相交的第二方向延伸。连接到第二导电构件的第一导电构件的一部分朝向第二导电构件突出。第一导电构件在第一方向上的电阻率低于第一导电构件在第一导电构件的突起的第三方向上的电阻率。第一导电构件在第三方向上的电阻值改变。第二导电构件在第二方向上的电阻率低于第二导电构件在第三方向上的电阻率。第二导电构件在第三方向上的电阻值改变。

5. 发明授权

US08071969B2 Semiconductor memory device and method for manufacturing same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08071969B2
公开(公告)日：2011-12-06
申请号：US12491296
申请日：2009-06-25
申请人： Kenji Aoyama
发明人： Kenji Aoyama
IPC分类号： H01L45/00 , G11C11/00
CPC分类号： H01L27/1021 , H01L27/24
摘要： A semiconductor memory device includes a word line interconnect layer having a plurality of word lines extending in a word line direction and a bit line interconnect layer having a plurality of bit lines extending in a bit line direction alternately stacked on a silicon substrate. A variable resistance film is disposed between the word line and the bit line. A first pin diode extending in the word line direction is provided between the word line and the variable resistance film, and a second pin diode extending in the bit line direction is provided between the bit line and the variable resistance film. A region of an upper surface of the pin diode other than an immediately underlying region of the variable resistance film is located lower than the immediately underlying region.
摘要翻译：半导体存储器件包括具有在字线方向上延伸的多个字线的字线互连层和具有交替层叠在硅衬底上的位线方向延伸的多个位线的位线互连层。可变电阻膜设置在字线和位线之间。在字线方向和可变电阻膜之间设置有沿字线方向延伸的第一PIN二极管，并且在位线和可变电阻膜之间设置沿位线方向延伸的第二pin二极管。引脚二极管的上表面的区域不同于可变电阻膜的紧邻下方区域的位置低于紧邻的下方区域。

6. 发明申请

US20110147822A1 Semiconductor memory device and method for manufacturing the same 审中-公开
公开(公告)号：US20110147822A1
公开(公告)日：2011-06-23
申请号：US12929894
申请日：2011-02-23
申请人： Kenji Aoyama , Eiji Ito , Masahiro Kiyotoshi , Tadashi Iguchi , Moto Yabuki
发明人： Kenji Aoyama , Eiji Ito , Masahiro Kiyotoshi , Tadashi Iguchi , Moto Yabuki
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/764 , H01L29/40114 , H01L29/66825
摘要： A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed at predetermined intervals on the semiconductor substrate, each word line having a gate insulating film, a charge storage layer, a first insulating film, and a controlling gate electrode which are stacked in order, and including a metal oxide layer above the level of the gate insulating film, a second insulating film covering a side of the word line and a surface of the semiconductor substrate between the word lines, and having a film thickness of 15 nm or less, and a third insulating film formed between the word lines adjacent to each other such that a region below the level of the metal oxide layer has a cavity.

7. 发明授权

US07868376B2 Semiconductor storage device and method for manufacturing the same 失效
公开(公告)号：US07868376B2
公开(公告)日：2011-01-11
申请号：US12354271
申请日：2009-01-15
申请人： Kenji Aoyama , Hisataka Meguro , Satoshi Nagashima
发明人： Kenji Aoyama , Hisataka Meguro , Satoshi Nagashima
IPC分类号： H01L29/792
CPC分类号： H01L21/28247 , H01L21/76229 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A semiconductor storage device has a plurality of word lines formed with a predetermined interval on a semiconductor substrate, a selection transistor provided at an end portion of the plurality of word lines, a first insulating film formed so as to cover side surfaces of the word lines, a side surface of the selection transistor, and a surface of the semiconductor substrate between the word lines, a high-permittivity film formed on the first insulation film, a second insulating film formed so as to cover the upper surface of the word lines and the selection transistor, a first air-gap portion located between the word lines and surrounded by the high-permittivity film and the second insulating film, and a second air-gap portion formed via the first insulating film and the high-permittivity film at a sidewall portion, which opposes the selection transistor, of the word line adjacent to the selection transistor, an upper portion of the second air-gap portion being covered by the second insulating film.

8. 发明申请

US20090218614A1 SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20090218614A1
公开(公告)日：2009-09-03
申请号：US12354271
申请日：2009-01-15
申请人： Kenji AOYAMA , Hisataka Meguro , Satoshi Nagashima
发明人： Kenji AOYAMA , Hisataka Meguro , Satoshi Nagashima
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L21/28247 , H01L21/76229 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A semiconductor storage device has a plurality of word lines formed with a predetermined interval on a semiconductor substrate, a selection transistor provided at an end portion of the plurality of word lines, a first insulating film formed so as to cover side surfaces of the word lines, a side surface of the selection transistor, and a surface of the semiconductor substrate between the word lines, a high-permittivity film formed on the first insulation film, a second insulating film formed so as to cover the upper surface of the word lines and the selection transistor, a first air-gap portion located between the word lines and surrounded by the high-permittivity film and the second insulating film, and a second air-gap portion formed via the first insulating film and the high-permittivity film at a sidewall portion, which opposes the selection transistor, of the word line adjacent to the selection transistor, an upper portion of the second air-gap portion being covered by the second insulating film.
摘要翻译：半导体存储装置具有在半导体衬底上形成有预定间隔的多个字线，设置在多个字线的端部的选择晶体管，形成为覆盖字线的侧面的第一绝缘膜所述选择晶体管的侧面以及所述字线之间的所述半导体基板的表面，形成在所述第一绝缘膜上的高电容率膜，形成为覆盖所述字线的上表面的第二绝缘膜，以及选择晶体管，位于字线之间并被高电容率膜和第二绝缘膜包围的第一气隙部分和经由第一绝缘膜和高介电常数膜形成的第二气隙部分，与选择晶体管相邻的字线相对的选择晶体管的侧壁部分，第二气隙部分的上部被第二i 记录膜。

9. 发明申请

US20090206391A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20090206391A1
公开(公告)日：2009-08-20
申请号：US12350658
申请日：2009-01-08
申请人： Kyoko ANDO , Satoshi Nagashima , Kenji Aoyama
发明人： Kyoko ANDO , Satoshi Nagashima , Kenji Aoyama
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/42324 , H01L21/76229 , H01L27/105 , H01L27/11526 , H01L27/11529 , H01L29/66825 , H01L29/7883
摘要： A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed on the semiconductor substrate at predetermined intervals, a selecting transistor arranged on each of two sides of each of the plurality of word lines in which a spacing between the selecting transistor and an adjacent one of the word lines is not less than three times a width of each of the word lines, an interlayer insulating film formed to cover upper surfaces of the word lines and selecting transistors, a first cavity portion which is located between each pair of adjacent ones of the word lines and whose upper portion is covered with the interlayer insulating film, a second cavity portion which is formed at a side wall portion of the word line adjacent to each selecting transistor which faces the selecting transistor and whose upper portion is covered with the interlayer insulating film, and a third cavity portion which is formed at a side wall portion of each of the selecting transistors and whose upper portion is covered with the interlayer insulating film.
摘要翻译：半导体存储器件具有半导体衬底，以预定间隔形成在半导体衬底上的多条字线，选择晶体管布置在多个字线中的每一个的两侧中，其中选择晶体管和字线的相邻一方的字线宽度不小于每条字线的宽度的三倍，形成为覆盖字线的上表面并选择晶体管的层间绝缘膜，第一空腔部分位于每对相邻的所述字线中的一个并且其上部被所述层间绝缘膜覆盖;第二空腔部分，形成在所述字线的与所述选择晶体管相对并且其上部被覆盖的相邻的字线的侧壁部分处层间绝缘膜和形成在每个选择晶体管的侧壁部分的第三空腔部分并且其上部被层间绝缘膜覆盖。

10. 发明授权

US08551852B2 Semiconductor memory device and method for manufacturing same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08551852B2
公开(公告)日：2013-10-08
申请号：US13277261
申请日：2011-10-20
申请人： Kenji Aoyama
发明人： Kenji Aoyama
IPC分类号： H01L45/00
CPC分类号： H01L27/1021 , H01L27/24
摘要： A semiconductor memory device includes a word line interconnect layer having a plurality of word lines extending in a word line direction and a bit line interconnect layer having a plurality of bit lines extending in a bit line direction alternately stacked on a silicon substrate. A variable resistance film is disposed between the word line and the bit line. A first pin diode extending in the word line direction is provided between the word line and the variable resistance film, and a second pin diode extending in the bit line direction is provided between the bit line and the variable resistance film. A region of an upper surface of the pin diode other than an immediately underlying region of the variable resistance film is located lower than the immediately underlying region.
摘要翻译：半导体存储器件包括具有在字线方向上延伸的多个字线的字线互连层和具有交替层叠在硅衬底上的位线方向延伸的多个位线的位线互连层。可变电阻膜设置在字线和位线之间。在字线方向和可变电阻膜之间设置有沿字线方向延伸的第一PIN二极管，并且在位线和可变电阻膜之间设置沿位线方向延伸的第二pin二极管。引脚二极管的上表面的区域不同于可变电阻膜的紧邻下方区域的位置低于紧邻的下方区域。

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