专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06421530B1 Radio circuit having a local oscillator frequency which differs from the transmit frequency or the receive frequency and mobile radio apparatus 失效
标题翻译：具有与发送频率或接收频率以及移动无线电设备不同的本地振荡器频率的无线电电路
公开(公告)号：US06421530B1
公开(公告)日：2002-07-16
申请号：US08933848
申请日：1997-09-19
申请人： Hisashi Adachi , Hiroaki Kosugi , Kaoru Ishida , Hiroshi Haruki , Junichi Yasuno , Kazuhiko Ikeda
发明人： Hisashi Adachi , Hiroaki Kosugi , Kaoru Ishida , Hiroshi Haruki , Junichi Yasuno , Kazuhiko Ikeda
IPC分类号： H04B140
CPC分类号： H04B1/403
摘要： The present invention concerns a radio circuit including a local oscillator, a first receive frequency converter, a frequency divider and a demodulator. A receive signal and an output of the local oscillator are input to the first receive frequency converter. The receive signal is converted into a first intermediate signal by the first receive frequency converter, and the first intermediate frequency signal is input to the demodulator. The output of the local oscillator is frequency-divided by the frequency divider and also input to the demodulator. The signal converted into the first intermediate frequency is demodulated into a baseband signal by the demodulator.
摘要翻译：本发明涉及包括本地振荡器，第一接收频率转换器，分频器和解调器的无线电电路。接收信号和本地振荡器的输出被输入到第一接收变频器。接收信号由第一接收频率转换器转换成第一中间信号，第一中频信号被输入到解调器。本地振荡器的输出由分频器分频，并输入到解调器。转换成第一中频的信号由解调器解调为基带信号。

2. 发明授权

US06441692B1 PLL frequency synthesizer 失效
标题翻译： PLL频率合成器
公开(公告)号：US06441692B1
公开(公告)日：2002-08-27
申请号：US09154740
申请日：1998-09-17
申请人： Toshifumi Nakatani , Hisashi Adachi , Hiroaki Kosugi , Yuji Saito , Shunsuke Hirano , Hiroshi Haruki
发明人： Toshifumi Nakatani , Hisashi Adachi , Hiroaki Kosugi , Yuji Saito , Shunsuke Hirano , Hiroshi Haruki
IPC分类号： H03B2100
CPC分类号： H03L7/18 , H03L2207/10
摘要： The invention provides a high-speed PLL frequency synthesizer in which the frequency of a reference signal can be made larger than a frequency interval of an external output with a simple configuration. An n-th harmonic of an output of a voltage-controlled oscillator is caused to pass through a band pass filter. The frequency of an output of the band pass filter is divided by M in a variable frequency divider. The phase of an output of the variable frequency divider is compared with that of the reference signal in a phase comparator. An output of the phase comparator is smoothed by a loop filter. The output of the voltage-controlled oscillator is controlled by an output of the loop filter. The fundamental wave of the output of the voltage-controlled oscillator is caused to pass through another band pass filter, and then output to the outside. At this time, the frequency of the reference signal is n times a frequency interval of the fundamental wave of the output of the voltage-controlled oscillator.
摘要翻译：本发明提供了一种高速PLL频率合成器，其中参考信号的频率可以被制成大于具有简单配置的外部输出的频率间隔。使压控振荡器的输出的n次谐波通过带通滤波器。带通滤波器的输出频率由可分频器M分频。在相位比较器中，可变分频器的输出相位与参考信号的相位相比较。相位比较器的输出由环路滤波器平滑。压控振荡器的输出由环路滤波器的输出控制。使压控振荡器的输出的基波通过另一个带通滤波器，然后输出到外部。此时，参考信号的频率是压控振荡器的输出的基波的频率间隔的n倍。

3. 发明授权

US06259895B1 Receiver and transmitter-receiver 失效
标题翻译：接收机和发射机 - 接收机
公开(公告)号：US06259895B1
公开(公告)日：2001-07-10
申请号：US09141854
申请日：1998-08-28
申请人： Yoshishige Yoshikawa , Yoshio Horiike , Hisashi Adachi , Hiroaki Kosugi
发明人： Yoshishige Yoshikawa , Yoshio Horiike , Hisashi Adachi , Hiroaki Kosugi
IPC分类号： H04B138
CPC分类号： H04B1/403 , H04B1/44
摘要： In the receiver using a PLL synthesizer, there is a limit in reducing boot-up time or frequency switching time, which shortens battery life. A first local frequency L01 from a multiplier 22 and a receiving signal are input to a first frequency converter 10 to convert it to a first intermediate frequency IF1. The first intermediate frequency IF1 is converted in a second frequency converter 12 by a frequency L02 of an N1 frequency divider 24 to a second intermediate frequency IF2. Also, the outputs of the N1 frequency divider 24 and N2 frequency divider 26 are mixed in the frequency converter for transmission 34, and L04 and the local frequency L01 are added to a lower-side-band cancel mixer 50 to extract the upper side band of the transmission frequency. With the configuration in which a frequency may be varied by one channel interval by varying the frequency division number of the N1 frequency divider 24 by one, switching of frequency division number permits channel switching for both transmission and reception.
摘要翻译：在使用PLL合成器的接收机中，减少启动时间或频率切换时间有限制，这缩短了电池寿命。来自乘法器22的第一本地频率L01和接收信号被输入到第一变频器10至将其转换为第一中间频IF1。第一中频IF1在第二频率转换器12中被N1分频器24的频率L02转换到第二中频IF2。此外，N1分频器24和N2分频器26的输出在变频器34中混合，用于变速器34，并且将L04和本地频率L01相加到下侧带取消混频器50以提取上侧频带的传输频率。通过将N1分频器24的分频数改变1，频率可以变化一个信道间隔的配置，分频数的切换允许发送和接收的信道切换。

4. 发明授权

US5815036A Apparatus and method for controlling feedforward amplifier 失效
标题翻译：用于控制前馈放大器的装置和方法
公开(公告)号：US5815036A
公开(公告)日：1998-09-29
申请号：US684384
申请日：1996-07-19
申请人： Yoshishige Yoshikawa , Hiroaki Kosugi , Hisashi Adachi , Kazuo Nagao
发明人： Yoshishige Yoshikawa , Hiroaki Kosugi , Hisashi Adachi , Kazuo Nagao
IPC分类号： H03F1/32 , H03F1/42 , H04B1/10 , H03F3/66
CPC分类号： H03F1/3235 , H03F2201/3218
摘要： A method and apparatus for controlling a feedforward amplifier, wherein a superior distortion compensation characteristic is maintained over a wide frequency range, with the influence due to temperature variation and weathering minimized. A pilot signal generated by a pilot signal generator circuit is injected into the output of the main amplifier of a feedforward amplifier, and then the signal is sampled at the output of a first circuit and a second circuit, which is then low-range converted by a frequency converter and demodulated into I and Q components by a quadrature demodulator, and amplified and shaped into a pilot monitor signal; and a control circuit controls the vector adjusters within the distortion suppression circuit of the first and the second circuits using the I and Q signal components as the error signal so that as the amplitude level of pilot monitor signal is mininized the control value is maintained.
摘要翻译：一种用于控制前馈放大器的方法和装置，其中在宽的频率范围内保持优异的失真补偿特性，由于温度变化和耐候性的影响最小化。由导频信号发生器电路产生的导频信号被注入前馈放大器的主放大器的输出端，然后在第一电路和第二电路的输出端对该信号进行采样，然后由第一电路和第二电路进行低范围转换频率转换器，并通过正交解调器解调成I和Q分量，并放大并成形为先导监控信号; 并且控制电路使用I和Q信号分量作为误差信号来控制第一和第二电路的失真抑制电路内的矢量调节器，使得当导频监控信号的幅度电平被微调时，保持控制值。

5. 发明授权

US06717998B2 Frequency synthesizer apparatus equipped with fraction part control circuit, communication apparatus, frequency modulator apparatus, and frequency modulating method 有权
$Frequency synthesizer apparatus equipped with fraction part control circuit, communication apparatus, frequency modulator apparatus, and frequency modulating method$
公开(公告)号：US06717998B2
公开(公告)日：2004-04-06
申请号：US09733949
申请日：2000-12-12
申请人： Hisashi Adachi , Toshifumi Nakatani , Hiroaki Kosugi , Masakatsu Maeda , Shunsuke Hirano
发明人： Hisashi Adachi , Toshifumi Nakatani , Hiroaki Kosugi , Masakatsu Maeda , Shunsuke Hirano
IPC分类号： H03D324
CPC分类号： H03L7/1976
摘要： A fraction part control circuit of a frequency synthesizer apparatus including a PLL circuit is of a plural-n-th-order delta-sigma modulator circuit for controlling a fraction part of a number of frequency division to a variable frequency divider of the PLL circuit. An adder adds data of the fraction part to an output data from a multiplier and outputs the resultant data to a quantizer through a second-order integrator. The quantizer quantizes input data with a quantization step and outputs the quantized data to the multiplier through a feedback circuit. The quantized data is used as data of the controlled fraction part. The multiplier multiplies data from the feedback circuit by the quantization step and outputs the resultant data to the adder. The fraction part control circuit periodically changes the data of the fraction part, thereby setting a frequency of an output signal from a VCO according to an average value of the period.

6. 发明授权

US5272452A PLL frequency synthesizer with variable bandwidth loop filter 失效
标题翻译：具有可变带宽环路滤波器的PLL频率合成器
公开(公告)号：US5272452A
公开(公告)日：1993-12-21
申请号：US932877
申请日：1992-08-20
申请人： Hisashi Adachi , Hiroaki Kosugi
发明人： Hisashi Adachi , Hiroaki Kosugi
IPC分类号： H03L7/107 , H03L7/18 , H03L7/183 , H03L7/093
CPC分类号： H03L7/107 , H03L7/183
摘要： A voltage controlled oscillator (VCO), a frequency divider, a phase detector, and a loop filter are connected to form a phase-locked loop. The input line of the loop filter is branched into two. One branch is connected to the ground through a first resistor, a second resistor and a capacitor which are connected in series. The other branch is connected between the second resistor and the capacitor through a switch and a bypass resistor which are connected in series. The connection point of the first resistor and second resistor are connected to the VCO as the output terminal of the loop filter. When the switch is off, the bandwidth of the loop filter is narrow, and when the switch is on, the bandwidth of the loop filter is broad.
摘要翻译：压控振荡器（VCO），分频器，相位检测器和环路滤波器被连接以形成锁相环。环路滤波器的输入线分为两部分。一个分支通过串联连接的第一电阻器，第二电阻器和电容器连接到地。另一个分支通过串联连接的开关和旁路电阻连接在第二电阻器和电容器之间。第一个电阻和第二个电阻的连接点连接到VCO作为环路滤波器的输出端。当交换机关闭时，环路滤波器的带宽较窄，当交换机开启时，环路滤波器的带宽较宽。

7. 发明授权

US07050525B2 Frequency synthesizer apparatus equipped with fraction part control circuit, communication apparatus, frequency modulator apparatus, and frequency modulating method 有权
$Frequency synthesizer apparatus equipped with fraction part control circuit, communication apparatus, frequency modulator apparatus, and frequency modulating method$
公开(公告)号：US07050525B2
公开(公告)日：2006-05-23
申请号：US10728863
申请日：2003-12-08
申请人： Hisashi Adachi , Toshifumi Nakatani , Hiroaki Kosugi , Masakatsu Maeda , Shunsuke Hirano
发明人： Hisashi Adachi , Toshifumi Nakatani , Hiroaki Kosugi , Masakatsu Maeda , Shunsuke Hirano
IPC分类号： H03D3/24 , H03L7/00 , H03C3/06
CPC分类号： H03L7/1976
摘要： A fraction part control circuit of a frequency synthesizer apparatus including a PLL circuit is of a plural-n-th-order delta-sigma modulator circuit for controlling a fraction part of a number of frequency division to a variable frequency divider of the PLL circuit. An adder adds data of the fraction part to an output data from a multiplier and outputs the resultant data to a quantizer through a second-order integrator. The quantizer quantizes input data with a quantization step and outputs the quantized data to the multiplier through a feedback circuit. The quantized data is used as data of the controlled fraction part. The multiplier multiplies data from the feedback circuit by the quantization step and outputs the resultant data to the adder. The fraction part control circuit periodically changes the data of the fraction part, thereby setting a frequency of an output signal from a VCO according to an average value of the period.

8. 发明授权

US07110486B2 Frequency synthesizer apparatus equipped with fraction part control circuit, communication apparatus, frequency modulator apparatus, and frequency modulating method 有权
$Frequency synthesizer apparatus equipped with fraction part control circuit, communication apparatus, frequency modulator apparatus, and frequency modulating method$
公开(公告)号：US07110486B2
公开(公告)日：2006-09-19
申请号：US11333245
申请日：2006-01-18
申请人： Hisashi Adachi , Toshifumi Nakatani , Hiroaki Kosugi , Masakatsu Maeda , Shunsuke Hirano
发明人： Hisashi Adachi , Toshifumi Nakatani , Hiroaki Kosugi , Masakatsu Maeda , Shunsuke Hirano
IPC分类号： H03D3/24 , H03L7/00 , H03C3/06
CPC分类号： H03L7/1976
摘要： A fraction part control circuit of a frequency synthesizer apparatus including a PLL circuit is of a plural-n-th-order delta-sigma modulator circuit for controlling a fraction part of a number of frequency division to a variable frequency divider of the PLL circuit. An adder adds data of the fraction part to an output data from a multiplier and outputs the resultant data to a quantizer through a second-order integrator. The quantizer quantizes input data with a quantization step and outputs the quantized data to the multiplier through a feedback circuit. The quantized data is used as data of the controlled fraction part. The multiplier multiplies data from the feedback circuit by the quantization step and outputs the resultant data to the adder. The fraction part control circuit periodically changes the data of the fraction part, thereby setting a frequency of an output signal from a VCO according to an average value of the period.

9. 发明授权

US07038557B2 Antenna duplexer and mobile communication device using the same 失效
公开(公告)号：US07038557B2
公开(公告)日：2006-05-02
申请号：US10085264
申请日：2002-02-27
申请人： Hiroyuki Nakamura , Toshio Ishizaki , Hisashi Adachi , Makoto Sakakura , Hiroaki Kosugi , Hiroyuki Itokawa , Toshiaki Nakamura
发明人： Hiroyuki Nakamura , Toshio Ishizaki , Hisashi Adachi , Makoto Sakakura , Hiroaki Kosugi , Hiroyuki Itokawa , Toshiaki Nakamura
IPC分类号： H03H7/46
CPC分类号： H04B1/0057 , H04B1/48 , H04B1/52
摘要： An antenna duplexer has an antenna terminal; a transmitting phase-shift circuit, one side of which is connected to the antenna terminal; a receiving phase-shift circuit, one side of which is connected to the antenna terminal; a transmitting filter connected to the other side of the transmitting phase-shift circuit and a transmitting terminal; and a receiving filter connected to the other side of the receiving phase-shift circuit and a receiving terminal; wherein the transmitting filter and/or the receiving filter is a composite filter, and the composite filter attains a characteristic having an attenuation pole at simultaneous transmission and reception time when transmission and reception are simultaneously performed, and controls respective impedances by the transmitting phase-shift circuit and the receiving phase-shift circuit to operate as a sharing unit and attains a characteristic where the attenuation pole is removed at non simultaneous transmission and reception time when transmission and reception are not performed simultaneously.

10. 发明授权

US06226499B1 Radio circuit apparatus and radio communication equipment 有权
标题翻译：无线电电路设备和无线电通信设备
公开(公告)号：US06226499B1
公开(公告)日：2001-05-01
申请号：US09359663
申请日：1999-07-26
申请人： Toshifumi Nakatani , Hisashi Adachi , Hiroaki Kosugi , Youichi Morinaga , Hiroyuki Itokawa , Shunsuke Hirano
发明人： Toshifumi Nakatani , Hisashi Adachi , Hiroaki Kosugi , Youichi Morinaga , Hiroyuki Itokawa , Shunsuke Hirano
IPC分类号： H04B140
CPC分类号： H04B1/403
摘要： When the radio circuit apparatus is transmitting, the output signal of the first local oscillator 102 is inputted to the transmitted frequency converter 112 as well as to the frequency divider 104, and then the output signal of the frequency divider 104 is inputted to the modulator 111. The modulator 111 modulates the output signal of the frequency divider 104 with a base band signal. The output signal of the modulator 111 is inputted to the transmitted frequency converter 112, to be converted to the frequency of a transmitted signal by the output signal of the first local oscillator 102. When the radio circuit apparatus is receiving, the output signal of the low noise amplifier 121 is inputted to the first frequency converter 122 to be converted to the first intermediate frequency by the output signal of the first local oscillator 102. The output signal of the filter 123 is inputted to the second frequency converter circuit 124 to be converted to the second intermediate frequency by the output signal of the second local oscillator 103. Thereby, unnecessary components for transmission can be easily lowered to make it possible to miniaturize the radio circuit apparatus.
摘要翻译：当无线电电路装置正在发送时，第一本地振荡器102的输出信号也被输入到发射的频率转换器112以及分频器104，然后分频器104的输出信号被输入到调制器111 调制器111用基带信号调制分频器104的输出信号。调制器111的输出信号通过第一本地振荡器102的输出信号被输入到发送的频率转换器112，以转换为发送信号的频率。当无线电电路装置正在接收时，输出信号低噪声放大器121被输入到第一频率转换器122，以通过第一本地振荡器102的输出信号转换成第一中频。滤波器123的输出信号被输入到第二频率转换器电路124进行转换通过第二本地振荡器103的输出信号输出到第二中频。由此，可以容易地降低用于传输的不必要的部件，使得可以使无线电电路装置小型化。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式