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1. 发明授权

US06259895B1 Receiver and transmitter-receiver 失效
标题翻译：接收机和发射机 - 接收机
公开(公告)号：US06259895B1
公开(公告)日：2001-07-10
申请号：US09141854
申请日：1998-08-28
申请人： Yoshishige Yoshikawa , Yoshio Horiike , Hisashi Adachi , Hiroaki Kosugi
发明人： Yoshishige Yoshikawa , Yoshio Horiike , Hisashi Adachi , Hiroaki Kosugi
IPC分类号： H04B138
CPC分类号： H04B1/403 , H04B1/44
摘要： In the receiver using a PLL synthesizer, there is a limit in reducing boot-up time or frequency switching time, which shortens battery life. A first local frequency L01 from a multiplier 22 and a receiving signal are input to a first frequency converter 10 to convert it to a first intermediate frequency IF1. The first intermediate frequency IF1 is converted in a second frequency converter 12 by a frequency L02 of an N1 frequency divider 24 to a second intermediate frequency IF2. Also, the outputs of the N1 frequency divider 24 and N2 frequency divider 26 are mixed in the frequency converter for transmission 34, and L04 and the local frequency L01 are added to a lower-side-band cancel mixer 50 to extract the upper side band of the transmission frequency. With the configuration in which a frequency may be varied by one channel interval by varying the frequency division number of the N1 frequency divider 24 by one, switching of frequency division number permits channel switching for both transmission and reception.
摘要翻译：在使用PLL合成器的接收机中，减少启动时间或频率切换时间有限制，这缩短了电池寿命。来自乘法器22的第一本地频率L01和接收信号被输入到第一变频器10至将其转换为第一中间频IF1。第一中频IF1在第二频率转换器12中被N1分频器24的频率L02转换到第二中频IF2。此外，N1分频器24和N2分频器26的输出在变频器34中混合，用于变速器34，并且将L04和本地频率L01相加到下侧带取消混频器50以提取上侧频带的传输频率。通过将N1分频器24的分频数改变1，频率可以变化一个信道间隔的配置，分频数的切换允许发送和接收的信道切换。

2. 发明授权

US5815036A Apparatus and method for controlling feedforward amplifier 失效
标题翻译：用于控制前馈放大器的装置和方法
公开(公告)号：US5815036A
公开(公告)日：1998-09-29
申请号：US684384
申请日：1996-07-19
申请人： Yoshishige Yoshikawa , Hiroaki Kosugi , Hisashi Adachi , Kazuo Nagao
发明人： Yoshishige Yoshikawa , Hiroaki Kosugi , Hisashi Adachi , Kazuo Nagao
IPC分类号： H03F1/32 , H03F1/42 , H04B1/10 , H03F3/66
CPC分类号： H03F1/3235 , H03F2201/3218
摘要： A method and apparatus for controlling a feedforward amplifier, wherein a superior distortion compensation characteristic is maintained over a wide frequency range, with the influence due to temperature variation and weathering minimized. A pilot signal generated by a pilot signal generator circuit is injected into the output of the main amplifier of a feedforward amplifier, and then the signal is sampled at the output of a first circuit and a second circuit, which is then low-range converted by a frequency converter and demodulated into I and Q components by a quadrature demodulator, and amplified and shaped into a pilot monitor signal; and a control circuit controls the vector adjusters within the distortion suppression circuit of the first and the second circuits using the I and Q signal components as the error signal so that as the amplitude level of pilot monitor signal is mininized the control value is maintained.
摘要翻译：一种用于控制前馈放大器的方法和装置，其中在宽的频率范围内保持优异的失真补偿特性，由于温度变化和耐候性的影响最小化。由导频信号发生器电路产生的导频信号被注入前馈放大器的主放大器的输出端，然后在第一电路和第二电路的输出端对该信号进行采样，然后由第一电路和第二电路进行低范围转换频率转换器，并通过正交解调器解调成I和Q分量，并放大并成形为先导监控信号; 并且控制电路使用I和Q信号分量作为误差信号来控制第一和第二电路的失真抑制电路内的矢量调节器，使得当导频监控信号的幅度电平被微调时，保持控制值。

3. 发明授权

US5691668A Feedforward amplifier 失效
标题翻译：前馈放大器
公开(公告)号：US5691668A
公开(公告)日：1997-11-25
申请号：US599799
申请日：1996-02-12
申请人： Yoshishige Yoshikawa , Hiroaki Kosugi , Hisashi Adachi , Kazuo Nagao , Shinichi Kugou
发明人： Yoshishige Yoshikawa , Hiroaki Kosugi , Hisashi Adachi , Kazuo Nagao , Shinichi Kugou
IPC分类号： H03F1/32 , H03F1/42 , H04B15/00
CPC分类号： H03F1/3235 , H03F2201/3212 , H03F2201/3218
摘要： A feedforward amplifier comprises a first feedforward circuit and a second feedforward circuit. The first feedforward circuit detects the distortion component of the output of a main amplifier through a first distortion detection circuit, and inserts the detected distortion component into the output signal of the main amplifier in a first distortion cancellation circuit to cancel the distortion component. The second feedforward circuit detects the distortion component of the output of the first feedforward circuit through a second distortion detection circuit, and inserts the detected distortion component into the output signal of the first feedforward circuit in a second distortion cancellation circuit, to perform distortion cancellation over a wide range of frequencies.
摘要翻译：前馈放大器包括第一前馈电路和第二前馈电路。第一前馈电路通过第一失真检测电路检测主放大器的输出的失真分量，并将检测到的失真分量插入到第一失真消除电路中的主放大器的输出信号中，以消除失真分量。第二前馈电路通过第二失真检测电路检测第一前馈电路的输出的失真分量，并将检测到的失真分量插入到第二失真消除电路中的第一前馈电路的输出信号中，以执行失真消除频率范围很广。

4. 发明授权

US5371477A Linear amplifier 失效
标题翻译：线性放大器
公开(公告)号：US5371477A
公开(公告)日：1994-12-06
申请号：US924937
申请日：1992-08-05
申请人： Hikaru Ikeda , Toshio Ishizaki , Hiroaki Kosugi , Yoshishige Yoshikawa , Kunihiko Kanazawa
发明人： Hikaru Ikeda , Toshio Ishizaki , Hiroaki Kosugi , Yoshishige Yoshikawa , Kunihiko Kanazawa
IPC分类号： H03F3/193 , H03G3/30 , H03G3/10
CPC分类号： H03G3/3047 , H03F3/1935
摘要： A linear amplifier has an input signal controller for controlling the level of an input signal to a field-effect transistor (FET) using a DC gate current measured by a gate current detector arranged between a gate bias terminal and a drain bias terminal of the FET and a nonlinear resistor whose resistance can be varied corresponding to an inter-terminal voltage between the gate and the drain of the FET, in which the voltage at the gate of the FET is adjusted to a rate such that a particular drain current which has been determined just before the starting of burst signal transmission corresponding to the level of a power output of the linear amplifier is obtained, and is maintained for a given period of time.
摘要翻译：线性放大器具有输入信号控制器，用于使用布置在FET的栅极偏置端子和漏极偏置端子之间的栅极电流检测器测量的DC栅极电流来控制到场效应晶体管（FET）的输入信号的电平以及一个非线性电阻，其电阻可以相应于FET的栅极和漏极之间的端子间电压而变化，其中FET的栅极处的电压被调节到使得具有特定的漏极电流的速率在与线性放大器的功率输出的电平相对应的脉冲串信号传输开始之前确定，并且保持给定的时间段。

5. 发明授权

US5095542A Apparatus for controlling transmission output level for burst signal 失效
标题翻译：用于控制传输信号输出电平的装置
公开(公告)号：US5095542A
公开(公告)日：1992-03-10
申请号：US546758
申请日：1990-07-02
申请人： Takayuki Suematsu , Yoshio Horiike , Hiroaki Kosugi
发明人： Takayuki Suematsu , Yoshio Horiike , Hiroaki Kosugi
IPC分类号： H03G3/30 , H03G3/20 , H04B1/04
CPC分类号： H03G3/3047
摘要： An apparatus for controlling a transmission output level for a burst signal which is used in a communication of the TDMA system in which a transmission output level can be arbitrarily set. The apparatus comprises a variable gain amplifier whose gain can be varied by a control voltage which is inputted to a control terminal; a variable gain amplifier whose gain can be varied by a control voltage which is inputted to a control terminal; a detecting circuit in which the variable gain amplifiers and are cascade connected to an input terminal to which a signal of a predetermined amplitude is inputted and to which an output electric power of the amplifier at the post stage is inputted and which extracts and detects a part of a voltage which is proportional to the output electric power; an attenuator which receives the voltage detected by the detecting circuit and can output at an arbitrary attenuation ratio; a reference waveform generating apparatus for outputting an envelope for a burst signal; a comparison amplifier which amplifies a different voltage between an output voltage of the attenuator and an output voltage of the reference waveform generating apparatus and whose output is connected to the control terminal of the variable gain amplifier; a control unit for controlling the control voltage of the variable gain amplifier and the attenuation ratio of the attenuator; and an output terminal for outputting a burst waveform from the detecting circuit.

6. 发明授权

US07050525B2 Frequency synthesizer apparatus equipped with fraction part control circuit, communication apparatus, frequency modulator apparatus, and frequency modulating method 有权
$Frequency synthesizer apparatus equipped with fraction part control circuit, communication apparatus, frequency modulator apparatus, and frequency modulating method$
公开(公告)号：US07050525B2
公开(公告)日：2006-05-23
申请号：US10728863
申请日：2003-12-08
申请人： Hisashi Adachi , Toshifumi Nakatani , Hiroaki Kosugi , Masakatsu Maeda , Shunsuke Hirano
发明人： Hisashi Adachi , Toshifumi Nakatani , Hiroaki Kosugi , Masakatsu Maeda , Shunsuke Hirano
IPC分类号： H03D3/24 , H03L7/00 , H03C3/06
CPC分类号： H03L7/1976
摘要： A fraction part control circuit of a frequency synthesizer apparatus including a PLL circuit is of a plural-n-th-order delta-sigma modulator circuit for controlling a fraction part of a number of frequency division to a variable frequency divider of the PLL circuit. An adder adds data of the fraction part to an output data from a multiplier and outputs the resultant data to a quantizer through a second-order integrator. The quantizer quantizes input data with a quantization step and outputs the quantized data to the multiplier through a feedback circuit. The quantized data is used as data of the controlled fraction part. The multiplier multiplies data from the feedback circuit by the quantization step and outputs the resultant data to the adder. The fraction part control circuit periodically changes the data of the fraction part, thereby setting a frequency of an output signal from a VCO according to an average value of the period.

7. 发明授权

US06717998B2 Frequency synthesizer apparatus equipped with fraction part control circuit, communication apparatus, frequency modulator apparatus, and frequency modulating method 有权
$Frequency synthesizer apparatus equipped with fraction part control circuit, communication apparatus, frequency modulator apparatus, and frequency modulating method$
公开(公告)号：US06717998B2
公开(公告)日：2004-04-06
申请号：US09733949
申请日：2000-12-12
申请人： Hisashi Adachi , Toshifumi Nakatani , Hiroaki Kosugi , Masakatsu Maeda , Shunsuke Hirano
发明人： Hisashi Adachi , Toshifumi Nakatani , Hiroaki Kosugi , Masakatsu Maeda , Shunsuke Hirano
IPC分类号： H03D324
CPC分类号： H03L7/1976
摘要： A fraction part control circuit of a frequency synthesizer apparatus including a PLL circuit is of a plural-n-th-order delta-sigma modulator circuit for controlling a fraction part of a number of frequency division to a variable frequency divider of the PLL circuit. An adder adds data of the fraction part to an output data from a multiplier and outputs the resultant data to a quantizer through a second-order integrator. The quantizer quantizes input data with a quantization step and outputs the quantized data to the multiplier through a feedback circuit. The quantized data is used as data of the controlled fraction part. The multiplier multiplies data from the feedback circuit by the quantization step and outputs the resultant data to the adder. The fraction part control circuit periodically changes the data of the fraction part, thereby setting a frequency of an output signal from a VCO according to an average value of the period.

8. 发明授权

US06441692B1 PLL frequency synthesizer 失效
标题翻译： PLL频率合成器
公开(公告)号：US06441692B1
公开(公告)日：2002-08-27
申请号：US09154740
申请日：1998-09-17
申请人： Toshifumi Nakatani , Hisashi Adachi , Hiroaki Kosugi , Yuji Saito , Shunsuke Hirano , Hiroshi Haruki
发明人： Toshifumi Nakatani , Hisashi Adachi , Hiroaki Kosugi , Yuji Saito , Shunsuke Hirano , Hiroshi Haruki
IPC分类号： H03B2100
CPC分类号： H03L7/18 , H03L2207/10
摘要： The invention provides a high-speed PLL frequency synthesizer in which the frequency of a reference signal can be made larger than a frequency interval of an external output with a simple configuration. An n-th harmonic of an output of a voltage-controlled oscillator is caused to pass through a band pass filter. The frequency of an output of the band pass filter is divided by M in a variable frequency divider. The phase of an output of the variable frequency divider is compared with that of the reference signal in a phase comparator. An output of the phase comparator is smoothed by a loop filter. The output of the voltage-controlled oscillator is controlled by an output of the loop filter. The fundamental wave of the output of the voltage-controlled oscillator is caused to pass through another band pass filter, and then output to the outside. At this time, the frequency of the reference signal is n times a frequency interval of the fundamental wave of the output of the voltage-controlled oscillator.
摘要翻译：本发明提供了一种高速PLL频率合成器，其中参考信号的频率可以被制成大于具有简单配置的外部输出的频率间隔。使压控振荡器的输出的n次谐波通过带通滤波器。带通滤波器的输出频率由可分频器M分频。在相位比较器中，可变分频器的输出相位与参考信号的相位相比较。相位比较器的输出由环路滤波器平滑。压控振荡器的输出由环路滤波器的输出控制。使压控振荡器的输出的基波通过另一个带通滤波器，然后输出到外部。此时，参考信号的频率是压控振荡器的输出的基波的频率间隔的n倍。

9. 发明授权

US5272452A PLL frequency synthesizer with variable bandwidth loop filter 失效
标题翻译：具有可变带宽环路滤波器的PLL频率合成器
公开(公告)号：US5272452A
公开(公告)日：1993-12-21
申请号：US932877
申请日：1992-08-20
申请人： Hisashi Adachi , Hiroaki Kosugi
发明人： Hisashi Adachi , Hiroaki Kosugi
IPC分类号： H03L7/107 , H03L7/18 , H03L7/183 , H03L7/093
CPC分类号： H03L7/107 , H03L7/183
摘要： A voltage controlled oscillator (VCO), a frequency divider, a phase detector, and a loop filter are connected to form a phase-locked loop. The input line of the loop filter is branched into two. One branch is connected to the ground through a first resistor, a second resistor and a capacitor which are connected in series. The other branch is connected between the second resistor and the capacitor through a switch and a bypass resistor which are connected in series. The connection point of the first resistor and second resistor are connected to the VCO as the output terminal of the loop filter. When the switch is off, the bandwidth of the loop filter is narrow, and when the switch is on, the bandwidth of the loop filter is broad.
摘要翻译：压控振荡器（VCO），分频器，相位检测器和环路滤波器被连接以形成锁相环。环路滤波器的输入线分为两部分。一个分支通过串联连接的第一电阻器，第二电阻器和电容器连接到地。另一个分支通过串联连接的开关和旁路电阻连接在第二电阻器和电容器之间。第一个电阻和第二个电阻的连接点连接到VCO作为环路滤波器的输出端。当交换机关闭时，环路滤波器的带宽较窄，当交换机开启时，环路滤波器的带宽较宽。

10. 发明授权

US07110486B2 Frequency synthesizer apparatus equipped with fraction part control circuit, communication apparatus, frequency modulator apparatus, and frequency modulating method 有权
$Frequency synthesizer apparatus equipped with fraction part control circuit, communication apparatus, frequency modulator apparatus, and frequency modulating method$
公开(公告)号：US07110486B2
公开(公告)日：2006-09-19
申请号：US11333245
申请日：2006-01-18
申请人： Hisashi Adachi , Toshifumi Nakatani , Hiroaki Kosugi , Masakatsu Maeda , Shunsuke Hirano
发明人： Hisashi Adachi , Toshifumi Nakatani , Hiroaki Kosugi , Masakatsu Maeda , Shunsuke Hirano
IPC分类号： H03D3/24 , H03L7/00 , H03C3/06
CPC分类号： H03L7/1976
摘要： A fraction part control circuit of a frequency synthesizer apparatus including a PLL circuit is of a plural-n-th-order delta-sigma modulator circuit for controlling a fraction part of a number of frequency division to a variable frequency divider of the PLL circuit. An adder adds data of the fraction part to an output data from a multiplier and outputs the resultant data to a quantizer through a second-order integrator. The quantizer quantizes input data with a quantization step and outputs the quantized data to the multiplier through a feedback circuit. The quantized data is used as data of the controlled fraction part. The multiplier multiplies data from the feedback circuit by the quantization step and outputs the resultant data to the adder. The fraction part control circuit periodically changes the data of the fraction part, thereby setting a frequency of an output signal from a VCO according to an average value of the period.

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