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1. 发明授权

US07110486B2 Frequency synthesizer apparatus equipped with fraction part control circuit, communication apparatus, frequency modulator apparatus, and frequency modulating method 有权
$Frequency synthesizer apparatus equipped with fraction part control circuit, communication apparatus, frequency modulator apparatus, and frequency modulating method$
公开(公告)号：US07110486B2
公开(公告)日：2006-09-19
申请号：US11333245
申请日：2006-01-18
申请人： Hisashi Adachi , Toshifumi Nakatani , Hiroaki Kosugi , Masakatsu Maeda , Shunsuke Hirano
发明人： Hisashi Adachi , Toshifumi Nakatani , Hiroaki Kosugi , Masakatsu Maeda , Shunsuke Hirano
IPC分类号： H03D3/24 , H03L7/00 , H03C3/06
CPC分类号： H03L7/1976
摘要： A fraction part control circuit of a frequency synthesizer apparatus including a PLL circuit is of a plural-n-th-order delta-sigma modulator circuit for controlling a fraction part of a number of frequency division to a variable frequency divider of the PLL circuit. An adder adds data of the fraction part to an output data from a multiplier and outputs the resultant data to a quantizer through a second-order integrator. The quantizer quantizes input data with a quantization step and outputs the quantized data to the multiplier through a feedback circuit. The quantized data is used as data of the controlled fraction part. The multiplier multiplies data from the feedback circuit by the quantization step and outputs the resultant data to the adder. The fraction part control circuit periodically changes the data of the fraction part, thereby setting a frequency of an output signal from a VCO according to an average value of the period.

2. 发明授权

US06717998B2 Frequency synthesizer apparatus equipped with fraction part control circuit, communication apparatus, frequency modulator apparatus, and frequency modulating method 有权
$Frequency synthesizer apparatus equipped with fraction part control circuit, communication apparatus, frequency modulator apparatus, and frequency modulating method$
公开(公告)号：US06717998B2
公开(公告)日：2004-04-06
申请号：US09733949
申请日：2000-12-12
申请人： Hisashi Adachi , Toshifumi Nakatani , Hiroaki Kosugi , Masakatsu Maeda , Shunsuke Hirano
发明人： Hisashi Adachi , Toshifumi Nakatani , Hiroaki Kosugi , Masakatsu Maeda , Shunsuke Hirano
IPC分类号： H03D324
CPC分类号： H03L7/1976
摘要： A fraction part control circuit of a frequency synthesizer apparatus including a PLL circuit is of a plural-n-th-order delta-sigma modulator circuit for controlling a fraction part of a number of frequency division to a variable frequency divider of the PLL circuit. An adder adds data of the fraction part to an output data from a multiplier and outputs the resultant data to a quantizer through a second-order integrator. The quantizer quantizes input data with a quantization step and outputs the quantized data to the multiplier through a feedback circuit. The quantized data is used as data of the controlled fraction part. The multiplier multiplies data from the feedback circuit by the quantization step and outputs the resultant data to the adder. The fraction part control circuit periodically changes the data of the fraction part, thereby setting a frequency of an output signal from a VCO according to an average value of the period.

3. 发明申请

US20060115036A1 Frequency synthesizer apparatus equipped with fraction part control circuit, communication apparatus, frequency modulator apparatus, and frequency modulating method 有权
$Frequency synthesizer apparatus equipped with fraction part control circuit, communication apparatus, frequency modulator apparatus, and frequency modulating method$
标题翻译：配有分数部分控制电路，通信装置，调频装置和频率调制方法的频率合成装置
公开(公告)号：US20060115036A1
公开(公告)日：2006-06-01
申请号：US11333245
申请日：2006-01-18
申请人： Hisashi Adachi , Toshifumi Nakatani , Hiroaki Kosugi , Masakatsu Maeda , Shunsuke Hirano
发明人： Hisashi Adachi , Toshifumi Nakatani , Hiroaki Kosugi , Masakatsu Maeda , Shunsuke Hirano
IPC分类号： H03D3/24
CPC分类号： H03L7/1976
摘要： A fraction part control circuit of a frequency synthesizer apparatus including a PLL circuit is of a plural-n-th-order delta-sigma modulator circuit for controlling a fraction part of a number of frequency division to a variable frequency divider of the PLL circuit. An adder adds data of the fraction part to an output data from a multiplier and outputs the resultant data to a quantizer through a second-order integrator. The quantizer quantizes input data with a quantization step and outputs the quantized data to the multiplier through a feedback circuit. The quantized data is used as data of the controlled fraction part. The multiplier multiplies data from the feedback circuit by the quantization step and outputs the resultant data to the adder. The fraction part control circuit periodically changes the data of the fraction part, thereby setting a frequency of an output signal from a VCO according to an average value of the period.
摘要翻译：包括PLL电路的频率合成器装置的分数部分控制电路是用于控制与PLL电路的可变分频器分频的分数部分的多n-Δ级Δ-Σ调制器电路。加法器将分数部分的数据与来自乘法器的输出数据相加，并将结果数据通过二阶积分器输出到量化器。量化器用量化步长量化输入数据，并通过反馈电路将量化的数据输出到乘法器。量化数据用作受控分数部分的数据。乘法器将来自反馈电路的数据乘以量化步长，并将结果数据输出到加法器。分数部分控制电路周期性地改变分数部分的数据，从而根据周期的平均值设置来自VCO的输出信号的频率。

4. 发明授权

US07050525B2 Frequency synthesizer apparatus equipped with fraction part control circuit, communication apparatus, frequency modulator apparatus, and frequency modulating method 有权
$Frequency synthesizer apparatus equipped with fraction part control circuit, communication apparatus, frequency modulator apparatus, and frequency modulating method$
公开(公告)号：US07050525B2
公开(公告)日：2006-05-23
申请号：US10728863
申请日：2003-12-08
申请人： Hisashi Adachi , Toshifumi Nakatani , Hiroaki Kosugi , Masakatsu Maeda , Shunsuke Hirano
发明人： Hisashi Adachi , Toshifumi Nakatani , Hiroaki Kosugi , Masakatsu Maeda , Shunsuke Hirano
IPC分类号： H03D3/24 , H03L7/00 , H03C3/06
CPC分类号： H03L7/1976
摘要： A fraction part control circuit of a frequency synthesizer apparatus including a PLL circuit is of a plural-n-th-order delta-sigma modulator circuit for controlling a fraction part of a number of frequency division to a variable frequency divider of the PLL circuit. An adder adds data of the fraction part to an output data from a multiplier and outputs the resultant data to a quantizer through a second-order integrator. The quantizer quantizes input data with a quantization step and outputs the quantized data to the multiplier through a feedback circuit. The quantized data is used as data of the controlled fraction part. The multiplier multiplies data from the feedback circuit by the quantization step and outputs the resultant data to the adder. The fraction part control circuit periodically changes the data of the fraction part, thereby setting a frequency of an output signal from a VCO according to an average value of the period.

5. 发明授权

US06226499B1 Radio circuit apparatus and radio communication equipment 有权
标题翻译：无线电电路设备和无线电通信设备
公开(公告)号：US06226499B1
公开(公告)日：2001-05-01
申请号：US09359663
申请日：1999-07-26
申请人： Toshifumi Nakatani , Hisashi Adachi , Hiroaki Kosugi , Youichi Morinaga , Hiroyuki Itokawa , Shunsuke Hirano
发明人： Toshifumi Nakatani , Hisashi Adachi , Hiroaki Kosugi , Youichi Morinaga , Hiroyuki Itokawa , Shunsuke Hirano
IPC分类号： H04B140
CPC分类号： H04B1/403
摘要： When the radio circuit apparatus is transmitting, the output signal of the first local oscillator 102 is inputted to the transmitted frequency converter 112 as well as to the frequency divider 104, and then the output signal of the frequency divider 104 is inputted to the modulator 111. The modulator 111 modulates the output signal of the frequency divider 104 with a base band signal. The output signal of the modulator 111 is inputted to the transmitted frequency converter 112, to be converted to the frequency of a transmitted signal by the output signal of the first local oscillator 102. When the radio circuit apparatus is receiving, the output signal of the low noise amplifier 121 is inputted to the first frequency converter 122 to be converted to the first intermediate frequency by the output signal of the first local oscillator 102. The output signal of the filter 123 is inputted to the second frequency converter circuit 124 to be converted to the second intermediate frequency by the output signal of the second local oscillator 103. Thereby, unnecessary components for transmission can be easily lowered to make it possible to miniaturize the radio circuit apparatus.
摘要翻译：当无线电电路装置正在发送时，第一本地振荡器102的输出信号也被输入到发射的频率转换器112以及分频器104，然后分频器104的输出信号被输入到调制器111 调制器111用基带信号调制分频器104的输出信号。调制器111的输出信号通过第一本地振荡器102的输出信号被输入到发送的频率转换器112，以转换为发送信号的频率。当无线电电路装置正在接收时，输出信号低噪声放大器121被输入到第一频率转换器122，以通过第一本地振荡器102的输出信号转换成第一中频。滤波器123的输出信号被输入到第二频率转换器电路124进行转换通过第二本地振荡器103的输出信号输出到第二中频。由此，可以容易地降低用于传输的不必要的部件，使得可以使无线电电路装置小型化。

6. 发明授权

US06441692B1 PLL frequency synthesizer 失效
标题翻译： PLL频率合成器
公开(公告)号：US06441692B1
公开(公告)日：2002-08-27
申请号：US09154740
申请日：1998-09-17
申请人： Toshifumi Nakatani , Hisashi Adachi , Hiroaki Kosugi , Yuji Saito , Shunsuke Hirano , Hiroshi Haruki
发明人： Toshifumi Nakatani , Hisashi Adachi , Hiroaki Kosugi , Yuji Saito , Shunsuke Hirano , Hiroshi Haruki
IPC分类号： H03B2100
CPC分类号： H03L7/18 , H03L2207/10
摘要： The invention provides a high-speed PLL frequency synthesizer in which the frequency of a reference signal can be made larger than a frequency interval of an external output with a simple configuration. An n-th harmonic of an output of a voltage-controlled oscillator is caused to pass through a band pass filter. The frequency of an output of the band pass filter is divided by M in a variable frequency divider. The phase of an output of the variable frequency divider is compared with that of the reference signal in a phase comparator. An output of the phase comparator is smoothed by a loop filter. The output of the voltage-controlled oscillator is controlled by an output of the loop filter. The fundamental wave of the output of the voltage-controlled oscillator is caused to pass through another band pass filter, and then output to the outside. At this time, the frequency of the reference signal is n times a frequency interval of the fundamental wave of the output of the voltage-controlled oscillator.
摘要翻译：本发明提供了一种高速PLL频率合成器，其中参考信号的频率可以被制成大于具有简单配置的外部输出的频率间隔。使压控振荡器的输出的n次谐波通过带通滤波器。带通滤波器的输出频率由可分频器M分频。在相位比较器中，可变分频器的输出相位与参考信号的相位相比较。相位比较器的输出由环路滤波器平滑。压控振荡器的输出由环路滤波器的输出控制。使压控振荡器的输出的基波通过另一个带通滤波器，然后输出到外部。此时，参考信号的频率是压控振荡器的输出的基波的频率间隔的n倍。

7. 发明授权

US07109793B2 High frequency differential circuit, differential amplifier, differential mixer, differential oscillator, and radio circuit using same 失效
标题翻译：高频差分电路，差分放大器，差分混频器，差分振荡器和使用相同的无线电电路
公开(公告)号：US07109793B2
公开(公告)日：2006-09-19
申请号：US10848212
申请日：2004-05-19
申请人： Toshifumi Nakatani , Hisashi Adachi
发明人： Toshifumi Nakatani , Hisashi Adachi
IPC分类号： H03F3/45
CPC分类号： H03F3/45094 , H03F3/45089 , H03F2200/294 , H03F2200/372 , H03F2203/45386 , H03F2203/45464 , H03F2203/45546 , H03F2203/45638
摘要： In order to enhance a reverse isolation characteristic of a differential amplifier, which is used as, for example, an RE amplifier or a local amplifier of a mobile telephone, differential amplifier is provided which includes a differential amplification circuit for amplifying a difference in potential between two input signals in reverse phase with each other, which are inputted into Port1 and Port2, and for outputting two output signals in reverse phase with each other from Port3 and Port4; a feedback capacitor connected between Port and Port4; and a feedback capacitor connected between Port2 and Port3. Signals for canceling feedback signals are inputted into input terminals via the feedback capacitors, whereby it is possible to the reverse isolation characteristic of the differential amplifier.
摘要翻译：为了增强用作例如移动电话的RE放大器或本地放大器的差分放大器的反向隔离特性，提供了差分放大器，其包括差分放大电路，用于放大电位差两个输入信号彼此反相，输入端口1和端口2，并从端口3和端口4彼此反相输出两个输出信号; 端口4之间连接反馈电容; 以及连接在端口2和端口3之间的反馈电容器。用于消除反馈信号的信号通过反馈电容器输入到输入端，从而可以实现差分放大器的反向隔离特性。

8. 发明授权

US07079829B2 Semiconductor differential circuit, oscillation apparatus, switching apparatus, amplifying apparatus, mixer apparatus and circuit apparatus using same, and semiconductor differential circuit placement method 失效
标题翻译：半导体差分电路，振荡装置，开关装置，放大装置，混频装置及其使用的电路装置以及半导体差分电路配置方法
公开(公告)号：US07079829B2
公开(公告)日：2006-07-18
申请号：US10712971
申请日：2003-11-13
申请人： Toshifumi Nakatani , Hisashi Adachi , Yukio Hiraoka
发明人： Toshifumi Nakatani , Hisashi Adachi , Yukio Hiraoka
IPC分类号： H04B1/28 , H01L27/01
CPC分类号： H03K3/354 , H01L27/0203 , H01L27/0738
摘要： A semiconductor differential circuit comprising a semiconductor substrate, a first semiconductor device on the semiconductor substrate having a gate electrode for having one of differential signals conveyed thereto and a drain electrode for outputting one of the differential signals controlled by the gate electrode, a second semiconductor device formed on the semiconductor substrate having a gate electrode for having the other of the differential signals conveyed thereto and a drain electrode for outputting the other of the differential signals controlled by the gate electrode, and wherein the drain electrode and drain electrode are placed in the proximity so that, at a predetermined frequency, it is equivalent to the one in which the drain electrode is grounded via a predetermined resistance, and the drain electrode is grounded via the predetermined resistance.
摘要翻译：一种半导体差分电路，包括半导体衬底，半导体衬底上的第一半导体器件，具有用于传送差分信号中的一个的栅极电极和用于输出由栅电极控制的差分信号之一的漏极;第二半导体器件形成在具有用于传送其中的另一个差分信号的栅电极的半导体衬底和用于输出由栅电极控制的另一个差分信号的漏电极，并且其中漏电极和漏极被放置在接近使得在预定频率下，等效于经由预定电阻使漏极接地的漏极，并且通过预定电阻将漏电极接地。

9. 发明授权

US06940707B2 Differential capacitor, differential antenna element, and differential resonator 失效
标题翻译：差分电容，差分天线元件和差分谐振器
公开(公告)号：US06940707B2
公开(公告)日：2005-09-06
申请号：US10880531
申请日：2004-07-01
申请人： Toshifumi Nakatani , Hisashi Adachi , Kayo Nakanishi
发明人： Toshifumi Nakatani , Hisashi Adachi , Kayo Nakanishi
IPC分类号： H01G2/22 , H01G4/005 , H01G4/38 , H01L27/00 , H01L27/04 , H01P1/203 , H01P7/08 , H01Q1/52 , H01Q9/04 , H01Q9/06 , H01Q15/00 , H01Q23/00
CPC分类号： H01L23/5223 , H01L2924/0002 , H01L2924/3011 , H01P1/203 , H01Q1/526 , H01Q15/0013 , H01Q23/00 , H01L2924/00
摘要： In a differential capacitor1, first and second capacitors 1003 and 1004 are formed in substantially symmetrical positions from each other with respect to a vertical plane B-B′, on a semiconductor substrate 1020. The differential capacitor 1 further includes a shield plate 1022 interposed between the semiconductor substrate 1020 and the lower electrodes 1016 and 1018. When each of the lower electrodes 1016 and 1018 is projected onto the shield plate 1022 along the vertical direction, each projected lower electrode 1016 or 1018 has a partial overlap with the shield plate 1022.
摘要翻译：在差分电容器1中，第一和第二电容器1003和1004在半导体衬底1020上相对于垂直平面B-B'形成为基本对称的位置。差分电容器1还包括插入在半导体衬底1020和下部电极1016和1018之间的屏蔽板1022。当下电极1016和1018中的每一个沿着垂直方向投影到屏蔽板1022上时，每个突出的下电极1016或1018与屏蔽板1022具有部分重叠。

10. 发明申请

US20050020227A1 High frequency variable gain amplification device, control device, high frequency variable gain frequency-conversion device, and communication device 失效
标题翻译：高频可变增益放大装置，控制装置，高频可变增益变频装置及通讯装置
公开(公告)号：US20050020227A1
公开(公告)日：2005-01-27
申请号：US10895380
申请日：2004-07-21
申请人： Masahiro Kumagawa , Toshifumi Nakatani , Hisashi Adachi
发明人： Masahiro Kumagawa , Toshifumi Nakatani , Hisashi Adachi
IPC分类号： H03G3/30 , H04B1/06
CPC分类号： H03G3/3052 , H03G3/3063
摘要： A high frequency variable gain amplification device 100 includes: a feedback circuit 103 capable of changing a feedback impedance to adjust the gain of an amplifier 101 in accordance with a control signal from a control device 200; and a current consumption adjustment circuit 102 capable of adjusting current consumption of the amplifier 101. The control device 200 controls the feedback impedance and the current consumption based on a desired signal power level and an undesired signal power level. If the desired signal power level exceeds a predetermined value, the control device 200 reduces the feedback impedance to increase the amount of a feedback signal, thereby allowing the amplifier 101 to operate with low gain so as to prevent the distortion characteristic from being reduced and to reduce the current consumption.
摘要翻译：高频可变增益放大装置100包括：能够根据来自控制装置200的控制信号改变反馈阻抗以调整放大器101的增益的反馈电路103; 以及能够调整放大器101的电流消耗的电流消耗调整电路102.控制装置200基于期望的信号功率电平和不期望的信号功率电平来控制反馈阻抗和电流消耗。如果期望的信号功率电平超过预定值，则控制装置200减小反馈阻抗以增加反馈信号的量，从而允许放大器101以低增益工作，以防止失真特性被减小，并且降低电流消耗。

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