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1. 发明授权

US3996565A Programmable sequence controller 失效
标题翻译：可编程序控制器
公开(公告)号：US3996565A
公开(公告)日：1976-12-07
申请号：US485575
申请日：1974-07-03
申请人： Hisaji Nakao , Yasufumi Tokura , Toshihiko Yomogida , Kazuo Matsuura
发明人： Hisaji Nakao , Yasufumi Tokura , Toshihiko Yomogida , Kazuo Matsuura
IPC分类号： G05B19/05 , G05B11/32
CPC分类号： G05B19/05 , G05B2219/13092 , G05B2219/15105
摘要： A sequence controller comprising a logic operation circuit for examining an external input with an examine command in accordance with a program. The logic operation circuit comprises block means for discontinuing a next examination of a logical function of a group of logical functions in response to a preceeding examination result of a logical function to thereby execute a logic operation non-sequentially.
摘要翻译：一种序列控制器，包括用于根据程序用检查命令检查外部输入的逻辑运算电路。逻辑运算电路包括块装置，用于响应于逻辑功能的先前检查结果而中断对一组逻辑功能的逻辑功能的下一次检查，从而非依次执行逻辑运算。

2. 发明授权

US4019175A Program changeable sequence controller 失效
标题翻译：程序可变序列控制器
公开(公告)号：US4019175A
公开(公告)日：1977-04-19
申请号：US568249
申请日：1975-04-15
申请人： Hisaji Nakao , Yasufumi Tokura , Kazuo Matsuno , Toshihiko Yomogida
发明人： Hisaji Nakao , Yasufumi Tokura , Kazuo Matsuno , Toshihiko Yomogida
IPC分类号： G11C17/00 , G05B19/05 , G06F9/06 , G06F17/50 , G07D5/08 , G11C16/02 , G11C17/18 , G05B19/18
CPC分类号： G05B19/056 , G11C17/18 , G05B2219/13006 , G05B2219/13013 , G05B2219/13153 , Y02P90/265
摘要： A programmable sequence controller is disclosed which includes a controller memory having at least one read-only memory unit for storing a sequence program comprising a series of instructions each including an operation code and address information. An operation control device is also provided for examining an external input in accordance with an appropriate instruction. An input network permits application of external inputs designated by the address information to the operation control device, and an output network is provided for transmitting a control signal based on the examination result from the operation control device. A program input network including a read-write memory is provided for storing a part of the sequence program, which part is loadable in one read-only memory unit. A program changing device is provided for changing the partial sequence program loaded in the read-write memory, and a transfer system is included for immediately transferring the changed sequence program into a read-only memory unit.
摘要翻译：公开了一种可编程顺序控制器，其包括具有至少一个只读存储器单元的控制器存储器，用于存储包括一系列指令的序列程序，每个指令包括操作代码和地址信息。还提供操作控制装置，用于根据适当的指令检查外部输入。输入网络允许将由地址信息指定的外部输入应用于操作控制装置，并且提供输出网络，用于基于来自操作控制装置的检查结果发送控制信号。提供包括读写存储器的程序输入网络，用于存储顺序程序的一部分，该部分可加载到一个只读存储器单元中。提供一种程序改变装置，用于改变加载在读写存储器中的部分顺序程序，并且包括用于立即将改变的顺序程序传送到只读存储单元的传送系统。

3. 发明授权

US4385367A Sequence block display system 失效
标题翻译：序列块显示系统
公开(公告)号：US4385367A
公开(公告)日：1983-05-24
申请号：US215373
申请日：1980-12-11
申请人： Hisaji Nakao , Hideo Nishimura , Toshihiko Yomogida , Masaharu Fujisaki
发明人： Hisaji Nakao , Hideo Nishimura , Toshihiko Yomogida , Masaharu Fujisaki
IPC分类号： G05B23/02 , G05B19/048 , G05B19/05 , G06F3/048 , G06F3/14
CPC分类号： G05B19/056 , G05B2219/13037 , G05B2219/13052
摘要： A sequence block display system used with a programmable sequence controller for displaying a sequence block on a screen of a cathode-ray tube display unit in the form of ladder diagram. The sequence block display system is provided with a data processor and a buffer memory which includes first, second and third memories. The first memory is capable of storing the whole of sequence programs stored in the sequence controller and the second memory is capable of storing at least one sequence block. The third memory is adapted to store output instructions, which are used to designate a sequence block, in the same order as each designated sequence block is displayed on the screen and further to read out the output instructions in the reverse order for displaying the sequence blocks which are put out of the screen.
摘要翻译：一种与可编程序列控制器一起使用的序列块显示系统，用于以梯形图的形式在阴极射线管显示单元的屏幕上显示序列块。序列块显示系统设置有数据处理器和包括第一，第二和第三存储器的缓冲存储器。第一存储器能够存储存储在序列控制器中的整个序列程序，并且第二存储器能够存储至少一个序列块。第三存储器适于以与每个指定的序列块显示在屏幕上相同的顺序存储用于指定序列块的输出指令，并且还以相反的顺序读出输出指令以显示序列块它们被放出屏幕。

4. 发明授权

US4510580A Programmable sequence controller 失效
标题翻译：可编程序控制器
公开(公告)号：US4510580A
公开(公告)日：1985-04-09
申请号：US384763
申请日：1982-06-03
申请人： Toshihiko Yomogida , Yasuo Suzuki , Kyoji Ito
发明人： Toshihiko Yomogida , Yasuo Suzuki , Kyoji Ito
IPC分类号： G05B19/05 , G06F3/04
CPC分类号： G05B19/05 , G05B2219/13083 , G05B2219/15103 , Y02P90/265
摘要： A programmable sequence controller using a technique called microprogramming, including a microprogram memory having a plurality of memory sections each storing a set of microinstructions corresponding to the command word of a sequence instruction. The operation code of the sequence instruction is applied to the upper bits of the microprogram memory so as to select one of the memory sections. The remaining bits are determined by a counter and the ON/OFF state of an I/O element so that one of the microinstructions is read out from the selected memory section.
摘要翻译：一种使用称为微程序技术的可编程顺序控制器，包括具有多个存储器部分的微程序存储器，每个存储部分存储与序列指令的命令字相对应的一组微指令。序列指令的操作码被应用于微程序存储器的高位，以便选择一个存储器部分。剩余的位由计数器和I / O元件的ON / OFF状态确定，使得从所选择的存储器部分读出微指令之一。

5. 发明授权

US4253141A Programmable sequence controller with counting function 失效
标题翻译：具有计数功能的可编程序列控制器
公开(公告)号：US4253141A
公开(公告)日：1981-02-24
申请号：US20048
申请日：1979-03-13
申请人： Isao Suzuki , Toshihiko Yomogida , Tsuyoshi Yokota
发明人： Isao Suzuki , Toshihiko Yomogida , Tsuyoshi Yokota
IPC分类号： G05B15/02 , G05B19/05 , G05B23/02 , G06F7/02 , G05B11/32 , G06F9/06
CPC分类号： G05B19/054 , G05B2219/15049
摘要： A programmable sequence controller with a counting function comprises an addressable latch circuit including at least one flip flop. A counter is connected to the flip flop such that the content of the counter is changed by one each time the flip flop is set. A setting device is provided for manually setting a count-up value of the counter. A comparator generates a count-up value signal when the counting-up of the counter to the count-up value is detected. A data selector is connected to receive the count-up value signal for supplying a logical value indicative of the status of the comparator. A logic operation circuit is responsive to a test command of a first instruction for testing a logical value of one of a plurality of external input devices and the data selector specified by address data in the first instruction and also responsive to an output command in a second instruction for generating an output command signal based upon the result of the test. The flip flop is set in response to the output command signal generated from the logic operation circuit when the flip flop is designated by the address data.
摘要翻译：具有计数功能的可编程序列控制器包括可寻址锁存电路，其包括至少一个触发器。计数器连接到触发器，使得每次触发器被设置时计数器的内容改变一个。提供了一种用于手动设置计数器的计数值的设置装置。当检测到计数器向上计数值的计数时，比较器产生计数上升值信号。连接数据选择器以接收用于提供指示比较器的状态的逻辑值的递增值信号。逻辑运算电路响应于第一指令的测试命令，用于测试多个外部输入设备之一的逻辑值和由第一指令中的地址数据指定的数据选择器，并且还响应于第二指令中的输出命令基于测试结果产生输出命令信号的指令。当触发器由地址数据指定时，响应于从逻辑运算电路产生的输出命令信号来设置触发器。

6. 发明授权

US4212081A Programmable sequence controller with auxiliary function decoding circuit 失效
标题翻译：具有辅助功能解码电路的可编程序列控制器
公开(公告)号：US4212081A
公开(公告)日：1980-07-08
申请号：US923205
申请日：1978-07-10
申请人： Isao Suzuki , Toshihiko Yomogida , Sadamu Kato
发明人： Isao Suzuki , Toshihiko Yomogida , Sadamu Kato
IPC分类号： G05D3/00 , G05B19/05 , G05B19/414 , G05B19/28 , G06F3/00
CPC分类号： G05B19/054 , G05B19/4147 , G05B2219/1125
摘要： In a programmable sequence controller, a memory stores an auxiliary function decoding program comprising command information and address information. A comparator circuit capable of a simultaneous comparison of a plurality of bits is operatively connected to an external numerical control device to receive auxiliary function data therefrom and connected to receive address information of the decoding program for comparing the auxiliary function data with the address information of the decoding program. A logic operation circuit included in the programmable sequence contoller is operatively connected to the comparator circuit to examine the comparison result of the comparator circuit based upon command information of the decoding program, whereby the auxiliary function data is decoded.
摘要翻译：在可编程顺序控制器中，存储器存储包括命令信息和地址信息的辅助功能解码程序。能够同时比较多个比特的比较器电路可操作地连接到外部数字控制装置以从其接收辅助功能数据，并连接到接收解码程序的地址信息，用于将辅助功能数据与解码程序。包括在可编程序列控制器中的逻辑运算电路可操作地连接到比较器电路，以基于解码程序的命令信息检查比较器电路的比较结果，从而对辅助功能数据进行解码。

7. 发明授权

US4249248A Programmable sequence controller with an arithmetic operation function 失效
标题翻译：具有算术运算功能的可编程序列控制器
公开(公告)号：US4249248A
公开(公告)日：1981-02-03
申请号：US14280
申请日：1979-02-23
申请人： Toshihiko Yomogida , Tsuyoshi Yokota
发明人： Toshihiko Yomogida , Tsuyoshi Yokota
IPC分类号： G05B15/02 , G05B19/05 , G06F9/26 , G06F9/32 , G06F15/46
CPC分类号： G05B19/052 , G06F9/264 , G05B2219/15048 , G05B2219/15103 , G05B2219/15127 , G05B2219/15131
摘要： A programmable sequence controller wherein a logic operation processor controls a program counter so as to successively read out from a sequence memory sequence instructions, which are applied to an input and output selector for selectively designating a plurality of input and output elements as well as to the logic operation rocessor. The logic operation processor is programmed to test the operational states of one or more input elements when receiving test commands and to output an energization or deenergization signal based upon the test result when receiving an output command. An output drive device is provided, which energizes or deenergizes selected one of the output elements in response to the energization or deenergization signal. Each of the sequence instructions includes therein any of an arithmetic operation command and the test and output commands, and when the arithmetic operation command is read out, an interrupt is applied to an arithmetic operation processor, which is thus enabled to execute the arithmetic operation command.
摘要翻译：一种可编程顺序控制器，其中逻辑运算处理器控制程序计数器，以便从序列存储器序列指令中连续读出，该指令被应用于输入和输出选择器，用于选择性地指定多个输入和输出元件以及逻辑运算处理器。逻辑运算处理器被编程为在接收测试命令时测试一个或多个输入元件的工作状态，并且当接收到输出命令时，基于测试结果输出通电或断电信号。提供输出驱动装置，其响应于通电或断电信号而激励或去激励选定的一个输出元件。序列指令中的每一个都包括算术运算命令和测试输出命令中的任一个，并且当读出算术运算命令时，中断被运算到算术运算处理器，由此能够执行运算指令。

8. 发明授权

US4176403A Programmable sequence controller 失效
标题翻译：可编程序控制器
公开(公告)号：US4176403A
公开(公告)日：1979-11-27
申请号：US917257
申请日：1978-06-20
申请人： Isao Suzuki , Toshihiko Yomogida , Tsuyoshi Yokota
发明人： Isao Suzuki , Toshihiko Yomogida , Tsuyoshi Yokota
IPC分类号： G05B19/05 , G06F7/00 , G06F7/02
CPC分类号： G05B19/054 , G05B2219/1125 , G05B2219/1174
摘要： A programmable sequence controller wherein in accordance with a sequence program read out from a memory, a logic operation circuit tests a logical value supplied from an input converter connected to an external input element and generates an output command signal based upon the result of the test. The output command signal is stored in an output memory which has two storage addresses for each external output element, each storage address corresponding to a particular memory storage element addressed by the sequence program. A gate circuit is connected to these two memory storage elements and inhibits the application of an output command signal from one of the memory storage elements to an output converter when the gate circuit receives a logical value from the input converter. When receiving an output command signal from the other of the two memory storage elements the gate circuit then applies this signal to the output converter. Thus, an output element connected to the output converter is energized immediately in response to the operation of an input element.
摘要翻译：一种可编程序控制器，其中根据从存储器读出的序列程序，逻辑运算电路测试从连接到外部输入元件的输入转换器提供的逻辑值，并根据测试结果生成输出命令信号。输出命令信号存储在每个外部输出元件具有两个存储地址的输出存储器中，每个存储地址对应于由顺控程序寻址的特定存储器存储元件。门电路连接到这两个存储器存储元件，并且当门电路从输入转换器接收逻辑值时，禁止从存储器存储元件之一向输出转换器施加输出命令信号。当从两个存储器元件中的另一个接收输出命令信号时，门电路然后将该信号施加到输出转换器。因此，响应于输入元件的操作，连接到输出转换器的输出元件被立即通电。

9. 发明授权

US4048622A Programmable sequence controller 失效
标题翻译：可编程序控制器
公开(公告)号：US4048622A
公开(公告)日：1977-09-13
申请号：US713351
申请日：1976-08-11
申请人： Toshihiko Yomogida
发明人： Toshihiko Yomogida
IPC分类号： G06F7/00 , G05B19/05 , G05B11/32
CPC分类号： G05B19/05 , G05B2219/1125 , G05B2219/1127 , G05B2219/15105
摘要： In a programmable sequence controller, a logic operation circuit has first and second AND gates, first and second OR gates and first to fourth flip flops. An input is applied to the two AND gates and the two OR gates. The first and second AND gates receive outputs of the first and second flip flops wich receive outputs of the first and second AND gates and are triggered in response to first and second control commands, respectively. The first and second OR gates receive outputs of the third and fourth flip flops which receive outputs of the first and second OR gates and are triggered in response to third and fourth control commands, respectively. A sequence control is performed in response to the outputs of the first to fourth flip flops.

10. 发明授权

US4881220A Multiplex communication system for sequence controllers 失效
标题翻译：序列控制器的多路复用通信系统
公开(公告)号：US4881220A
公开(公告)日：1989-11-14
申请号：US235498
申请日：1988-08-24
申请人： Toshihiko Yomogida , Tsuyoshi Yamashita , Shigeo Yamamoto , Hideaki Tobita , Hisanori Nakamura , Goro Kobayashi
发明人： Toshihiko Yomogida , Tsuyoshi Yamashita , Shigeo Yamamoto , Hideaki Tobita , Hisanori Nakamura , Goro Kobayashi
IPC分类号： H04J3/14 , H04L12/437
CPC分类号： H04J3/14 , H04L12/437
摘要： Among systems configured by connecting a plurality of sequence controllers to one communication line to intercommunicate, many systems has been disclosed which implement fault location and recovery from the faults. In one of these systems, each substation is connected to a circulating communication line via a branch line and switches are respectively disposed on the branch line and on the communication line at both sides of a connecting point of the branch line and the communication line. Further, the communication line can be formed in a loop by a spare line. In another of these systems, an integrated portion of the communication line is formed near the master station, and the communication line is connected to the master station and is configured of one continuous line which goes and backs in sequence between the integrated portion and vicinity of each substation. In that integrated portion, a switch is disposed on each one of two lines, which connect the integrated portion and each substation. Further, a switch is provided on a line which bypasses these two switches. Other systems are a composite of the above systems. Still other systems have automated portions of fault location and fault recovery.
摘要翻译：在通过将多个序列控制器连接到一个通信线路以进行互通来配置的系统中，已经公开了实现故障定位和从故障恢复的许多系统。在这些系统之一中，每个变电站通过分支线路连接到循环通信线路，并且开关分别设置在分支线路和分支线路和通信线路的连接点两侧的通信线路上。此外，可以通过备用线路将通信线路形成为环路。在这些系统的另一个中，在主站附近形成通信线路的集成部分，并且通信线路连接到主站，并且由一条连续的线路构成，该连续线路在一体化部分和每个变电站。在该集成部分中，开关设置在连接整合部分和每个变电站的两条线路中的每一条线上。此外，在绕过这两个开关的线路上提供开关。其他系统是上述系统的组合。其他系统还具有故障定位和故障恢复的自动化部分。

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