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1. 发明授权

US08482999B2 Semiconductor memory integrated device having a precharge circuit with thin-film transistors gated by a voltage higher than a power supply voltage 有权
标题翻译：半导体存储器集成器件具有通过高于电源电压的电压而门控的薄膜晶体管的预充电电路
公开(公告)号：US08482999B2
公开(公告)日：2013-07-09
申请号：US13600412
申请日：2012-08-31
申请人： Hiroyuki Takahashi , Tetsuo Fukushi
发明人： Hiroyuki Takahashi , Tetsuo Fukushi
IPC分类号： G11C7/12
CPC分类号： G11C11/4085 , G11C7/062 , G11C7/12 , G11C11/4091 , G11C11/4094 , G11C11/4097
摘要： Provided is a semiconductor integrated device including a semiconductor memory circuit and a peripheral circuit of the semiconductor memory circuit. The peripheral circuit includes a first transistor having a first voltage as a breakdown voltage of a gate oxide film. The semiconductor memory circuit includes a pair of bit lines, one of the pair of bit lines being connected to a gate transistor of a memory cell, and a precharge circuit that includes a transistor having a breakdown voltage substantially equal to that of the first transistor, and precharges the pair of bit lines to a predetermined voltage in response to an activation signal. The activation signal of the precharge circuit is a second voltage higher than the first voltage.
摘要翻译：提供一种包括半导体存储电路和半导体存储电路的外围电路的半导体集成器件。外围电路包括具有作为栅氧化膜的击穿电压的第一电压的第一晶体管。半导体存储器电路包括一对位线，一对位线中的一个连接到存储单元的栅极晶体管，以及预充电电路，其包括具有基本上等于第一晶体管的击穿电压的晶体管，并且响应于激活信号将一对位线预充电到预定电压。预充电电路的激活信号是比第一电压高的第二电压。

2. 发明授权

US08279691B2 Semiconductor memory integrated device with a precharge circuit having thin-film transistors gated by a voltage higher than a power supply voltage 失效
标题翻译：具有预充电电路的半导体存储器集成器件，其具有由高于电源电压的电压而选通的薄膜晶体管
公开(公告)号：US08279691B2
公开(公告)日：2012-10-02
申请号：US12769141
申请日：2010-04-28
申请人： Hiroyuki Takahashi , Tetsuo Fukushi
发明人： Hiroyuki Takahashi , Tetsuo Fukushi
IPC分类号： G11C7/12
CPC分类号： G11C11/4085 , G11C7/062 , G11C7/12 , G11C11/4091 , G11C11/4094 , G11C11/4097
摘要： Provided is a semiconductor integrated device including a semiconductor memory circuit and a peripheral circuit of the semiconductor memory circuit. The peripheral circuit includes a first transistor having a first voltage as a breakdown voltage of a gate oxide film. The semiconductor memory circuit includes a pair of bit lines, one of the pair of bit lines being connected to a gate transistor of a memory cell, and a precharge circuit that includes a transistor having a breakdown voltage substantially equal to that of the first transistor, and precharges the pair of bit lines to a predetermined voltage in response to an activation signal. The activation signal of the precharge circuit is a second voltage higher than the first voltage.
摘要翻译：提供一种包括半导体存储电路和半导体存储电路的外围电路的半导体集成器件。外围电路包括具有作为栅氧化膜的击穿电压的第一电压的第一晶体管。半导体存储器电路包括一对位线，一对位线中的一个连接到存储单元的栅极晶体管，以及预充电电路，其包括具有基本上等于第一晶体管的击穿电压的晶体管，并且响应于激活信号将一对位线预充电到预定电压。预充电电路的激活信号是比第一电压高的第二电压。

3. 发明申请

US20120327732A1 SEMICONDUCTOR INTEGRATED DEVICE 有权
标题翻译：半导体集成器件
公开(公告)号：US20120327732A1
公开(公告)日：2012-12-27
申请号：US13600412
申请日：2012-08-31
申请人： Hiroyuki Takahashi , Tetsuo Fukushi
发明人： Hiroyuki Takahashi , Tetsuo Fukushi
IPC分类号： G11C7/12
CPC分类号： G11C11/4085 , G11C7/062 , G11C7/12 , G11C11/4091 , G11C11/4094 , G11C11/4097
摘要： Provided is a semiconductor integrated device including a semiconductor memory circuit and a peripheral circuit of the semiconductor memory circuit. The peripheral circuit includes a first transistor having a first voltage as a breakdown voltage of a gate oxide film. The semiconductor memory circuit includes a pair of bit lines, one of the pair of bit lines being connected to a gate transistor of a memory cell, and a precharge circuit that includes a transistor having a breakdown voltage substantially equal to that of the first transistor, and precharges the pair of bit lines to a predetermined voltage in response to an activation signal. The activation signal of the precharge circuit is a second voltage higher than the first voltage.
摘要翻译：提供一种包括半导体存储电路和半导体存储电路的外围电路的半导体集成器件。外围电路包括具有作为栅氧化膜的击穿电压的第一电压的第一晶体管。半导体存储器电路包括一对位线，一对位线中的一个连接到存储单元的栅极晶体管，以及预充电电路，其包括具有基本上等于第一晶体管的击穿电压的晶体管，并且响应于激活信号将一对位线预充电到预定电压。预充电电路的激活信号是比第一电压高的第二电压。

4. 发明申请

US20100290300A1 SEMICONDUCTOR INTEGRATED DEVICE 失效
标题翻译：半导体集成器件
公开(公告)号：US20100290300A1
公开(公告)日：2010-11-18
申请号：US12769141
申请日：2010-04-28
申请人： Hiroyuki TAKAHASHI , Tetsuo Fukushi
发明人： Hiroyuki TAKAHASHI , Tetsuo Fukushi
IPC分类号： G11C7/00 , G11C7/06
CPC分类号： G11C11/4085 , G11C7/062 , G11C7/12 , G11C11/4091 , G11C11/4094 , G11C11/4097
摘要： Provided is a semiconductor integrated device including a semiconductor memory circuit and a peripheral circuit of the semiconductor memory circuit. The peripheral circuit includes a first transistor having a first voltage as a breakdown voltage of a gate oxide film. The semiconductor memory circuit includes a pair of bit lines, one of the pair of bit lines being connected to a gate transistor of a memory cell, and a precharge circuit that includes a transistor having a breakdown voltage substantially equal to that of the first transistor, and precharges the pair of bit lines to a predetermined voltage in response to an activation signal. The activation signal of the precharge circuit is a second voltage higher than the first voltage.
摘要翻译：提供一种包括半导体存储电路和半导体存储电路的外围电路的半导体集成器件。外围电路包括具有作为栅氧化膜的击穿电压的第一电压的第一晶体管。半导体存储器电路包括一对位线，一对位线中的一个连接到存储单元的栅极晶体管，以及预充电电路，其包括具有基本上等于第一晶体管的击穿电压的晶体管，并且响应于激活信号将一对位线预充电到预定电压。预充电电路的激活信号是比第一电压高的第二电压。

5. 发明申请

US20110025279A1 POWER SUPPLY CIRCUIT AND SEMICONDUCTOR DEVICE 审中-公开
标题翻译：电源电路和半导体器件
公开(公告)号：US20110025279A1
公开(公告)日：2011-02-03
申请号：US12821955
申请日：2010-06-23
申请人： TOSHIKATSU JINBO , Tetsuo Fukushi , Kazutaka Kikuchi
发明人： TOSHIKATSU JINBO , Tetsuo Fukushi , Kazutaka Kikuchi
IPC分类号： G05F1/10
CPC分类号： G11C5/145
摘要： A power supply circuit comprises: a first voltage booster circuit that receives a first clock signal having a fixed frequency, and supplies a voltage to a prescribed circuit; and a second voltage booster circuit that receives a second clock signal having a frequency corresponding to an operating frequency of the prescribed circuit, and supplies a voltage to the prescribed circuit.
摘要翻译：电源电路包括：第一升压电路，其接收具有固定频率的第一时钟信号，并将电压提供给规定的电路; 以及第二升压电路，其接收具有与规定电路的工作频率对应的频率的第二时钟信号，并向规定电路供给电压。

6. 发明授权

US08335116B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US08335116B2
公开(公告)日：2012-12-18
申请号：US13014510
申请日：2011-01-26
申请人： Muneaki Matsushige , Atsunori Hirobe , Kazutaka Kikuchi , Tetsuo Fukushi
发明人： Muneaki Matsushige , Atsunori Hirobe , Kazutaka Kikuchi , Tetsuo Fukushi
IPC分类号： G11C7/00 , G11C8/00 , G11C8/16
CPC分类号： G11C7/00 , G11C7/10
摘要： A semiconductor storage device includes: a plurality of memory cell arrays; a plurality of bidirectional data buses provided in correspondence with respective ones of the plurality of memory cell arrays; a plurality of bidirectional buffer circuits, which are provided in correspondence with respective ones of the memory cell arrays, capable of connecting adjacent bidirectional data buses serially so as to relay data in the bidirectional data buses; and a control circuit for controlling activation of the bidirectional buffer circuits. The bidirectional buffer circuit is arranged so as to invert logic and the bidirectional buffer circuit is arranged so as not to invert logic.
摘要翻译：半导体存储装置包括：多个存储单元阵列; 多个双向数据总线，与所述多个存储单元阵列中的相应数据总线相对应地设置; 多个双向缓冲电路，其与存储单元阵列相对应地设置，能够连续地连接相邻的双向数据总线，以便中继双向数据总线中的数据; 以及用于控制双向缓冲电路的激活的控制电路。双向缓冲电路被布置为反转逻辑，并且双向缓冲电路被布置成不反转逻辑。

7. 发明授权

US07633310B2 Semiconductor integrated circuit capable of autonomously adjusting output impedance 有权
标题翻译：能够自主调节输出阻抗的半导体集成电路
公开(公告)号：US07633310B2
公开(公告)日：2009-12-15
申请号：US11924627
申请日：2007-10-26
申请人： Tetsuo Fukushi
发明人： Tetsuo Fukushi
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/0005
摘要： A semiconductor integrated circuit includes an output driver, a replica driver, a replica resistor, and an impedance adjustment circuit. The output driver is configured to be capable of changing current driving capability. The replica driver is configured to be capable of changing current driving capability. The replica resistor is connected to an output of the replica driver. The impedance adjustment circuit is configured to adjust the current driving capability of the output driver and the replica driver, based on an output voltage of the replica driver. In addition, the output driver, the replica driver, the replica resistor, and the impedance adjustment circuit are mounted in an integrated circuit package.
摘要翻译：半导体集成电路包括输出驱动器，复制驱动器，复制电阻器和阻抗调整电路。输出驱动器被配置为能够改变电流驱动能力。复制驱动器被配置为能够改变当前驱动能力。复制电阻连接到副本驱动器的输出。阻抗调整电路被配置为基于副本驱动器的输出电压来调节输出驱动器和副本驱动器的电流驱动能力。此外，输出驱动器，复制驱动器，复制电阻器和阻抗调节电路安装在集成电路封装中。

8. 发明申请

US20110188330A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20110188330A1
公开(公告)日：2011-08-04
申请号：US13014510
申请日：2011-01-26
申请人： Muneaki MATSUSHIGE , Atsunori Hirobe , Kazutaka Kikuchi , Tetsuo Fukushi
发明人： Muneaki MATSUSHIGE , Atsunori Hirobe , Kazutaka Kikuchi , Tetsuo Fukushi
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/00 , G11C7/10
摘要： A semiconductor storage device includes: a plurality of memory cell arrays; a plurality of bidirectional data buses provided in correspondence with respective ones of the plurality of memory cell arrays; a plurality of bidirectional buffer circuits, which are provided in correspondence with respective ones of the memory cell arrays, capable of connecting adjacent bidirectional data buses serially so as to relay data in the bidirectional data buses; and a control circuit for controlling activation of the bidirectional buffer circuits. The bidirectional buffer circuit is arranged so as to invert logic and the bidirectional buffer circuit is arranged so as not to invert logic.
摘要翻译：半导体存储装置包括：多个存储单元阵列; 多个双向数据总线，与所述多个存储单元阵列中的相应数据总线相对应地设置; 多个双向缓冲电路，其与存储单元阵列相对应地设置，能够连续地连接相邻的双向数据总线，以便中继双向数据总线中的数据; 以及用于控制双向缓冲电路的激活的控制电路。双向缓冲电路被布置为反转逻辑，并且双向缓冲电路被布置成不反转逻辑。

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