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    • 1. 发明申请
    • METHOD OF MANUFACTURING A THIN-FILM MAGNETIC HEAD
    • 制造薄膜磁头的方法
    • US20090283205A1
    • 2009-11-19
    • US12354519
    • 2009-01-15
    • Hiroyuki MiyazawaMasaya KatoMasanori Tachibana
    • Hiroyuki MiyazawaMasaya KatoMasanori Tachibana
    • B32B37/02
    • G11B5/3163G11B5/1278G11B5/3116G11B5/3146G11B5/315
    • A method of manufacturing a thin-film magnetic head is capable of planarizing and forming the upper surface of a main magnetic pole with high precision, of forming a trailing gap with a precise form, and of efficiently and precisely forming side shields and a trailing shield. A stopper layer is formed so as to cover a magnetic pole and so that a thickness thereof at positions on both sides of the magnetic pole is a predetermined side shield gap width. After a resist layer has been formed so that a thickness thereof at positions on both sides of the magnetic pole is a predetermined side shield width, an insulating layer is formed thereupon and then lapping according to a CMP process is carried out until the stopper layer becomes exposed. After this, the stopper layer is removed by dry etching until the upper surface of the magnetic pole becomes exposed, and then the upper surface of the magnetic pole is lapped by a CMP process until the surface is planarized. Next, the resist layer is removed and the stopper layer that becomes exposed due to such removal is also removed to form the trailing shield and the side shields.
    • 制造薄膜磁头的方法能够以高精度平面化和形成主磁极的上表面,以精确的形式形成后跟间隙,并且有效和精确地形成侧屏蔽和后屏蔽 。 形成阻挡层以覆盖磁极,并且使得其在磁极两侧的位置处的厚度为预定的侧屏蔽间隙宽度。 在形成抗蚀剂层之后,使其在磁极两侧的位置处的厚度为预定的侧屏蔽宽度,在其上形成绝缘层,然后进行根据CMP工艺的研磨,直到阻挡层变为 裸露。 之后,通过干蚀刻去除阻挡层,直到磁极的上表面露出,然后通过CMP工艺研磨磁极的上表面,直到表面平坦化。 接下来,除去抗蚀剂层,并且除去由于这种去除而变得露出的阻挡层以形成后屏蔽和侧屏蔽。
    • 6. 发明授权
    • Amplifier
    • 放大器
    • US06586995B1
    • 2003-07-01
    • US10246444
    • 2002-09-19
    • Masanori Tachibana
    • Masanori Tachibana
    • H03F345
    • H03F3/68H03F3/45183
    • An amplifier includes a first voltage follower including P-type MOS transistors and a second voltage follower including N-type MOS transistors. The first voltage follower amplifies without being saturated even if an input signal voltage approaches a level of a power supply voltage when the input signal voltage is at least equal to a bias voltage, but does not amplify when the input voltage is less than the bias voltage. A second voltage follower of the amplifier amplifies without being saturated even if an input signal voltage approaches a ground potential when the input signal voltage is less than the bias voltage, but does not amplify when the input voltage is at least equal to the bias voltage.
    • 放大器包括包括P型MOS晶体管的第一电压跟随器和包括N型MOS晶体管的第二电压跟随器。 即使当输入信号电压至少等于偏置电压时输入信号电压接近电源电压的电平,第一电压跟随器放大而不饱和,但是当输入电压小于偏置电压时不放大 。 即使当输入信号电压小于偏置电压时输入信号电压接近地电位,但是当输入电压至少等于偏置电压时,放大器的第二电压跟随器放大而不饱和。
    • 8. 发明授权
    • Charged-particle beam irradiation device, charged-particle beam irradiation method, and computer readable medium
    • 带电粒子束照射装置,带电粒子束照射方法和计算机可读介质
    • US08294127B2
    • 2012-10-23
    • US13207521
    • 2011-08-11
    • Masanori Tachibana
    • Masanori Tachibana
    • G21K5/00
    • A61N5/1043A61N2005/1087
    • A charged-particle beam irradiation device, which irradiates an object to be irradiated with a charged-particle beam, includes a scanning member that scans the object to be irradiated with the charged-particle beam; an irradiation amount setting unit that sets an irradiation amount of the charged-particle beam at a plurality of target scanning positions on a scanning line of the charged-particle beam with which the scanning member scans the object to be irradiated; and a scanning speed setting unit that sets a target scanning speed of the charged-particle beam at each of the target scanning positions on the basis of the irradiation amount set by the irradiation amount setting unit.
    • 照射带电粒子束的被照射物的带电粒子束照射装置包括扫描被照射物体的扫描部件,该扫描部件用带电粒子束照射被照射物体。 照射量设定单元,其将所述带电粒子束的照射量设定在所述扫描部件扫描所述被照射物体的所述带电粒子束的扫描线上的多个目标扫描位置; 以及扫描速度设定单元,其基于由照射量设定单元设定的照射量,在每个目标扫描位置设定带电粒子束的目标扫描速度。
    • 9. 发明申请
    • Method of manufacturing a metal pattern
    • 金属图案的制造方法
    • US20080008840A1
    • 2008-01-10
    • US11545695
    • 2006-10-10
    • Kentaro SuzukiMasanori TachibanaYukinori Ikegawa
    • Kentaro SuzukiMasanori TachibanaYukinori Ikegawa
    • B05D7/00
    • G11B5/3912G11B5/3163G11B5/855
    • Even when materials with different grinding rates, such as a metal layer and an insulating layer, are present on a substrate, a method of manufacturing can grind the surface of the substrate to form a flat surface and can grind the metal layer to a predetermined thickness without fluctuations. The method includes a step of forming an insulating film on a substrate surface to cover a surface of a metal layer that has a predetermined pattern and then forming a stopper film on a surface of the insulating film; a step of forming a resist pattern that exposes only bulging parts of the insulating film that cover the metal layer and then removing the stopper film from the surface of the bulging parts to form a stopper layer on a surface of the insulating film covered by the resist pattern; a grinding step of grinding the surface of the substrate to grind the bulging parts as far as a position regulated by the stopper layer; and a step of removing the stopper layer from the surface of the insulating film and then carrying out finish-up grinding on the surface of the substrate.
    • 即使当基板上存在诸如金属层和绝缘层的具有不同研磨速度的材料时,制造方法可以研磨基板的表面以形成平坦表面,并且可以将金属层研磨成预定厚度 没有波动。 该方法包括在基板表面上形成绝缘膜以覆盖具有预定图案的金属层的表面,然后在绝缘膜的表面上形成阻挡膜的步骤; 形成抗蚀剂图案的步骤,该抗蚀剂图案仅暴露仅覆盖金属层的绝缘膜的凸出部分,然后从凸出部分的表面去除阻挡膜,以在由抗蚀剂覆盖的绝缘膜的表面上形成阻挡层 模式; 研磨步骤,研磨所述基材的表面以研磨所述凸出部分至所述阻挡层调节的位置; 以及从绝缘膜的表面除去阻挡层,然后在基板的表面进行完成研磨的步骤。
    • 10. 发明授权
    • Clamp circuit for clamping a digital video signal
    • 用于钳位数字视频信号的钳位电路
    • US07095452B2
    • 2006-08-22
    • US10697332
    • 2003-10-31
    • Masanori Tachibana
    • Masanori Tachibana
    • H04N5/04H04N5/16H04N5/18H04N5/57
    • H03G11/00H04N5/18
    • A clamp control circuit outputs a clamp control signal after a delay of a predetermined time if a digital video signal is detected. A sampling circuit that extracts sampling data of a pedestal level from a luminance corrected signal based on a clamp pulse at a timing of the back porch. A data averaging circuit calculates an average of the sampling data of the pedestal level. A data holding circuit holds a difference between the average and a digital signal processing reference level when the clamp control signal is output and also when the clamp control signal is not output. A level correction circuit corrects a level of the luminance signal based on the difference held by the data holding circuit and outputs the corrected luminance signal.
    • 如果检测到数字视频信号,钳位控制电路在预定时间的延迟之后输出钳位控制信号。 一种采样电路,其在后沿的定时基于钳位脉冲从亮度校正信号中提取基准电平的采样数据。 数据平均电路计算基座电平的采样数据的平均值。 当输出钳位控制信号时,数据保持电路还保持平均值和数字信号处理基准电平之间的差值,并且在不输出钳位控制信号时也保持数字信号处理基准电平之间的差。 电平校正电路基于由数据保持电路保持的差异来校正亮度信号的电平,并输出校正的亮度信号。