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    • 1. 发明申请
    • FIELD EFFECT TRANSISTOR AND CIRCUIT DEVICE
    • 场效应晶体管和电路器件
    • US20110114914A1
    • 2011-05-19
    • US13055807
    • 2009-06-19
    • Hideaki NumataSatoru ToguchiHiroyuki Endoh
    • Hideaki NumataSatoru ToguchiHiroyuki Endoh
    • H01L29/12B82Y99/00
    • H01L27/12H01L27/0203H01L27/1225H01L27/1285H01L27/1292H01L29/0673H01L29/41733H01L29/66765
    • An end portion (104a) of a first source electrode (104) and an end portion (105a) of a first drain electrode (105) face each other on a gate insulating film (103) via a channel formation region. The first source electrode (104) and first drain electrode (105) extend over steps, and the end portion (104a) and end portion (105a) face each other on the gate insulating film (103). The highest portions of the end portion (104a) and end portion (105a) are formed higher than the upper surface of the gate insulating film (103) serving as the channel formation region. A field-effect transistor of this invention also includes a second source electrode (107) which is formed in contact with the channel layer (106) and connects the first source electrode (104) and channel layer (106), and a second drain electrode (108) which is formed in contact with the channel layer (106) and connects, the first drain electrode (105) and channel layer (106).
    • 第一源电极(104)的端部(104a)和第一漏极(105)的端部(105a)经由沟道形成区域彼此面对栅极绝缘膜(103)。 第一源电极(104)和第一漏电极(105)在台阶上延伸,并且端部(104a)和端部(105a)在栅极绝缘膜(103)上彼此面对。 端部(104a)和端部(105a)的最高部分形成为高于用作沟道形成区域的栅极绝缘膜(103)的上表面。 本发明的场效应晶体管还包括形成为与沟道层(106)接触并连接第一源电极(104)和沟道层(106)的第二源电极(107)和第二漏电极 (108),其与所述沟道层(106)接触形成并连接所述第一漏电极(105)和沟道层(106)。
    • 8. 发明申请
    • Magnetic memory, and its operating method
    • 磁记忆体及其操作方法
    • US20060056250A1
    • 2006-03-16
    • US10512545
    • 2003-04-21
    • Sadahiko MiuraTadahiko SugibayashiHideaki NumataKiyotaka Tsuji
    • Sadahiko MiuraTadahiko SugibayashiHideaki NumataKiyotaka Tsuji
    • G11C7/00
    • H01L27/228B82Y10/00G11C11/16
    • A technology for eliminating the defects in a tunnel insulation film of magnetic tunnel junction and for suppressing generation of a defective bit in an MRAM using magnetic tunnel junction in a memory. The magnetic memory includes a substrate, an interlayer insulation film covering the upper surface side of the substrate, memory cells, and plugs penetrating the interlayer insulation film. The memory cell includes a first magnetic layer formed on the upper surface side of the interlayer insulation film, a tunnel insulation layer formed on the first magnetic layer, and a second magnetic layer formed on the tunnel insulation layer. The plug is connected electrically with the first magnetic layer. The tunnel current passing part of the tunnel insulation layer located between the first and second magnetic layers is arranged, at least partially, so as not to overlap the plug in the direction perpendicular to the surface of the substrate.
    • 一种用于消除磁隧道结隧道绝缘膜中的缺陷并用于抑制在存储器中使用磁性隧道结的MRAM中的有缺陷位的产生的技术。 磁性存储器包括基板,覆盖基板的上表面侧的层间绝缘膜,存储单元和穿透层间绝缘膜的插塞。 存储单元包括形成在层间绝缘膜的上表面侧的第一磁性层,形成在第一磁性层上的隧道绝缘层和形成在隧道绝缘层上的第二磁性层。 插头与第一磁性层电连接。 位于第一和第二磁性层之间的隧道绝缘层的隧道电流通过部分被布置成至少部分地不与垂直于衬底的表面的方向上的插塞重叠。
    • 9. 发明授权
    • Magnetic random access memory having voltage control circuitry for maintaining sense lines at constant low voltages
    • 磁性随机存取存储器具有用于将感测线保持在恒定低电压的电压控制电路
    • US06462982B1
    • 2002-10-08
    • US09962325
    • 2001-09-26
    • Hideaki NumataKoichi Takeda
    • Hideaki NumataKoichi Takeda
    • G11C1100
    • G11C11/15Y10S977/743
    • A matrix array of memory cells are located on intersections of word lines and sense lines. Each memory cell has a magnetoresistance element and a switching element which establishes a connection between a corresponding sense line and the magnetoresistance element when a corresponding word line is addressed. A number of sense circuits are respectively provided for the sense lines. Each sense circuit includes a capacitive element connected to the corresponding sense line and a switching element for applying a voltage to the capacitive element and causing it to discharge when the corresponding sense line is addressed. The voltage developed across the capacitive element of each sense circuit is used to produce a binary output signal representative of information stored in an address memory cell. A number of voltage control elements are provided for maintaining the sense lines at constant lower voltages regardless of higher voltages produced by the sense circuits.
    • 存储器单元的矩阵阵列位于字线和感测线的交点上。 每个存储单元具有磁阻元件和开关元件,当对应的字线被寻址时,该开关元件在相应的感测线和磁阻元件之间建立连接。 分别为感测线提供多个感测电路。 每个感测电路包括连接到相应感测线的电容元件和用于向电容元件施加电压并使其在对应感测线被寻址时放电的开关元件。 在每个感测电路的电容元件两端产生的电压用于产生表示存储在地址存储单元中的信息的二进制输出信号。 提供多个电压控制元件用于将感测线保持在恒定的较低电压,而不管由感测电路产生的较高电压。