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1. 发明授权

US5081509A Semiconductor rectifying diode with pn geometry 失效
标题翻译：具有pn几何形状的半导体整流二极管
公开(公告)号：US5081509A
公开(公告)日：1992-01-14
申请号：US580534
申请日：1990-09-11
申请人： Hiroshi Kozaka , Susumu Murakami , Masanori Takata , Takao Yaginuma , Naofumi Kohno
发明人： Hiroshi Kozaka , Susumu Murakami , Masanori Takata , Takao Yaginuma , Naofumi Kohno
IPC分类号： H01L29/47 , H01L29/861 , H01L29/872 , H02M3/28
CPC分类号： H01L29/872 , H01L29/0619 , H01L29/861
摘要： A semiconductor rectifying diode includes a first semiconductor region of one conductivity type, a plurality of third semiconductor regions of the other conductivity type provided on one surface of said first semiconductor region to be spaced a distance W, and a main electrode provided on said one main surface in ohmic contact with said first semiconductor region and in contact with said third semiconductor regions through the Schottky barrier. To reduce reverse leakage current a relation of 2wo
摘要翻译：一种半导体整流二极管包括一个导电类型的第一半导体区域，另一个导电类型的多个第三半导体区域设置在所述第一半导体区域的一个表面上以间隔距离W，以及主电极，设置在所述一个主体表面与所述第一半导体区域欧姆接触并通过肖特基势垒与所述第三半导体区域接触。为了减少反向泄漏电流，满足2wo

2. 发明授权

US5256889A Semiconductor rectifying diode with PN geometry 失效
标题翻译：具有PN几何形状的半导体整流二极管
公开(公告)号：US5256889A
公开(公告)日：1993-10-26
申请号：US818515
申请日：1992-01-09
申请人： Hiroshi Kozaka , Susumu Murakami , Masanori Takata , Takao Yaginuma , Naofumi Kohno
发明人： Hiroshi Kozaka , Susumu Murakami , Masanori Takata , Takao Yaginuma , Naofumi Kohno
IPC分类号： H01L29/861 , H01L29/872 , H01L29/90
CPC分类号： H01L29/872 , H01L29/0619 , H01L29/861
摘要： A semiconductor rectifying diode includes a first semiconductor region of one conductivity type, a plurality of third semiconductor regions of the other conductivity type provided on one surface of said first semiconductor region to be spaced a distance W, and a main electrode provided on said one main surface to in ohmic contact with said first semiconductor region and in contact with said third semiconductor regions through the Schottky barrier. To reduce reverse leakage current a relation of 2wo
摘要翻译：一种半导体整流二极管包括一个导电类型的第一半导体区域，另一个导电类型的多个第三半导体区域设置在所述第一半导体区域的一个表面上以间隔距离W，以及主电极，设置在所述一个主体表面与所述第一半导体区域欧姆接触并通过所述肖特基势垒与所述第三半导体区域接触。为了减少反向泄漏电流，满足2wo

3. 发明授权

US4894768A Data processing system with coprocessor 失效
标题翻译：数据处理系统与协处理器
公开(公告)号：US4894768A
公开(公告)日：1990-01-16
申请号：US21007
申请日：1987-03-02
申请人： Kazuhiko Iwasaki , Tsuneo Funabashi , Ikuya Kawasaki , Hideo Inayoshi , Atsushi Hasegawa , Takao Yaginuma , Eiki Kondoh
发明人： Kazuhiko Iwasaki , Tsuneo Funabashi , Ikuya Kawasaki , Hideo Inayoshi , Atsushi Hasegawa , Takao Yaginuma , Eiki Kondoh
IPC分类号： G06F15/16 , G06F9/38 , G06F15/167
CPC分类号： G06F15/167 , G06F9/3877
摘要： When a microprocessor fetches an instruction to be processed by a coprocessor, it sends to the coprocessor a command corresponding to the instruction while informing the coprocessor that the bus cycle is in the mode of transfer of the instruction to the coprocessor. In transferring an operand from the memory to the coprocessor, the microprocessor asserts, in addition to a usual memory read signal, a signal (CYCYCL) indicative of validity of the coprocessor and instructs the coprocessor to fetch data to thereby complete the operand transfer from memory to coprocessor within one bus cycle. In transferring data from the coprocessor to the memory, the microprocessor asserts, in addition to a usual memory write signal, the CYCYCL signal and instructs the coprocessor to deliver the data to thereby complete the data transfer from memory to coprocessor within one bus cycle. Thus, the signal transfer between memory and coprocessor can be completed within one bus cycle without resort to the provision of duplicate hardware in the coprocessor.
摘要翻译：当微处理器提取要由协处理器处理的指令时，它向协处理器发送与指令相对应的命令，同时通知协处理器总线周期处于向协处理器传送指令的模式。在将操作数从存储器传送到协处理器时，除了通常的存储器读取信号之外，微处理器还断言指示协处理器的有效性的信号（＆upbar＆C /），并且指示协处理器提取数据从而完成操作数传送从一个总线周期内的存储器到协处理器。在将数据从协处理器传输到存储器时，微处理器除了通常的存储器写入信号之外，还断言＆upbar＆C /信号并指示协处理器传送数据，从而完成在一个总线周期内从存储器到协处理器的数据传输。因此，存储器和协处理器之间的信号传输可以在一个总线周期内完成，而不需要在协处理器中提供重复的硬件。

4. 发明授权

US5088017A DC-DC converter and a computer using the converter 失效
标题翻译： DC-DC转换器和使用转换器的计算机
公开(公告)号：US5088017A
公开(公告)日：1992-02-11
申请号：US540789
申请日：1990-06-20
申请人： Takao Yaginuma , Kenichi Onda , Yasuo Matsuda , Kouichi Mizuta
发明人： Takao Yaginuma , Kenichi Onda , Yasuo Matsuda , Kouichi Mizuta
IPC分类号： G06F1/26 , H02J1/10 , H02M3/28 , H02M3/335 , H02M3/337 , H03K17/16
CPC分类号： H02M3/337 , H02J1/102 , H02M3/33569
摘要： In order to provide miniaturization and increased-frequency operation of a DC-DC converter used with a computer, etc., a capacitor is connected in parallel with a switching element when the switching element is turned off to reduce turn-off loss. When the switching element is turned on, the capacitor and a DC power source are connected in series to supply the energy stored in the capacitor to a load circuit to result in a high initial voltage being applied across the load circuit.
摘要翻译：为了提供与计算机等一起使用的DC-DC转换器的小型化和增加频率的操作，当开关元件被关断以降低关断损耗时，电容器与开关元件并联连接。当开关元件接通时，电容器和直流电源串联连接，以将存储在电容器中的能量提供给负载电路，从而在负载电路两端施加较高的初始电压。

5. 发明授权

US4888721A Elementary function arithmetic unit 失效
标题翻译：基本功能运算单元
公开(公告)号：US4888721A
公开(公告)日：1989-12-19
申请号：US94752
申请日：1987-09-09
申请人： Eiki Kondoh , Shigeki Morinaga , Takao Yaginuma , Takeshi Asai
发明人： Eiki Kondoh , Shigeki Morinaga , Takao Yaginuma , Takeshi Asai
IPC分类号： G06F7/544 , G06F17/17
CPC分类号： G06F7/5446
摘要： A function arithmetic unit which performs elementary operations at high speeds and which enables required memory capacity to be reduced. The function arithmetic unit includes a constant memory which stores a constant that corresponds to the number of successive iterative operations; a controller which causes addition or subtraction in the successive iterative operations; and arithmetic units which receive, as initial values, an argument of an elementary function value to be found and two constants determined depending upon the elementary functions to be found, and which subject these initial values to n iterative operations to produce elementary function values. A further arithmetic unit subjects the elementary function values to multiplication, addition, subtraction, or division, or a combination thereof, thereby to produce the thus obtained value.
摘要翻译：一种功能运算单元，其以高速执行基本操作，并且能够减少所需的存储器容量。所述功能运算单元包括：恒定存储器，存储对应于连续迭代操作次数的常数; 在连续迭代操作中产生加法或减法的控制器; 以及算术单元，其作为初始值接收要发现的基本函数值的参数和根据要发现的基本函数确定的两个常数，以及将这些初始值映射到n个迭代操作以产生基本函数值。另外的运算单元将基本函数值进行乘法，加法，减法或除法或其组合，从而产生如此获得的值。

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