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1. 发明授权

US4894768A Data processing system with coprocessor 失效
标题翻译：数据处理系统与协处理器
公开(公告)号：US4894768A
公开(公告)日：1990-01-16
申请号：US21007
申请日：1987-03-02
申请人： Kazuhiko Iwasaki , Tsuneo Funabashi , Ikuya Kawasaki , Hideo Inayoshi , Atsushi Hasegawa , Takao Yaginuma , Eiki Kondoh
发明人： Kazuhiko Iwasaki , Tsuneo Funabashi , Ikuya Kawasaki , Hideo Inayoshi , Atsushi Hasegawa , Takao Yaginuma , Eiki Kondoh
IPC分类号： G06F15/16 , G06F9/38 , G06F15/167
CPC分类号： G06F15/167 , G06F9/3877
摘要： When a microprocessor fetches an instruction to be processed by a coprocessor, it sends to the coprocessor a command corresponding to the instruction while informing the coprocessor that the bus cycle is in the mode of transfer of the instruction to the coprocessor. In transferring an operand from the memory to the coprocessor, the microprocessor asserts, in addition to a usual memory read signal, a signal (CYCYCL) indicative of validity of the coprocessor and instructs the coprocessor to fetch data to thereby complete the operand transfer from memory to coprocessor within one bus cycle. In transferring data from the coprocessor to the memory, the microprocessor asserts, in addition to a usual memory write signal, the CYCYCL signal and instructs the coprocessor to deliver the data to thereby complete the data transfer from memory to coprocessor within one bus cycle. Thus, the signal transfer between memory and coprocessor can be completed within one bus cycle without resort to the provision of duplicate hardware in the coprocessor.
摘要翻译：当微处理器提取要由协处理器处理的指令时，它向协处理器发送与指令相对应的命令，同时通知协处理器总线周期处于向协处理器传送指令的模式。在将操作数从存储器传送到协处理器时，除了通常的存储器读取信号之外，微处理器还断言指示协处理器的有效性的信号（＆upbar＆C /），并且指示协处理器提取数据从而完成操作数传送从一个总线周期内的存储器到协处理器。在将数据从协处理器传输到存储器时，微处理器除了通常的存储器写入信号之外，还断言＆upbar＆C /信号并指示协处理器传送数据，从而完成在一个总线周期内从存储器到协处理器的数据传输。因此，存储器和协处理器之间的信号传输可以在一个总线周期内完成，而不需要在协处理器中提供重复的硬件。

2. 发明授权

US4926321A Method of searching a queue in response to a search instruction 失效
标题翻译：响应于搜索指令搜索队列的方法
公开(公告)号：US4926321A
公开(公告)日：1990-05-15
申请号：US089818
申请日：1987-08-27
申请人： Ken Sakamura , Kouzi Hashimoto , Ikuya Kawasaki , Atsushi Hasegawa , Kazuhiko Iwasaki
发明人： Ken Sakamura , Kouzi Hashimoto , Ikuya Kawasaki , Atsushi Hasegawa , Kazuhiko Iwasaki
IPC分类号： G06F9/46 , G06F9/30 , G06F9/312 , G06F17/30
CPC分类号： G06F9/30043 , G06F17/30958 , Y10S707/99933
摘要： A method for searching the memory of a data processing apparatus including a decoder for decoding the contents of an instruction and an execution unit for executing the instruction based on an output from the decoder is performed in response to a search instruction which identifies a desired data storage area from a plurality of data storage areas in the memory which includes an array data structure.
摘要翻译：一种用于搜索数据处理装置的存储器的方法，该数据处理装置包括用于解码指令内容的解码器和用于基于来自解码器的输出执行该指令的执行单元，该方法响应于识别期望数据存储器的搜索指令包括阵列数据结构的存储器中的多个数据存储区域。

3. 发明授权

US5170474A Method of searching a queue in response to a search instruction 失效
标题翻译：响应于搜索指令搜索队列的方法
公开(公告)号：US5170474A
公开(公告)日：1992-12-08
申请号：US755742
申请日：1991-09-24
申请人： Ken Sakamura , Kouzi Hashimoto , Ikuya Kawasaki , Atsushi Hasegawa , Kazuhiko Iwasaki
发明人： Ken Sakamura , Kouzi Hashimoto , Ikuya Kawasaki , Atsushi Hasegawa , Kazuhiko Iwasaki
IPC分类号： G06F9/312 , G06F17/30
CPC分类号： G06F9/30043 , G06F17/30958 , Y10S707/99936
摘要： A method for searching the memory of a data processing apparatus including a decoder for decoding the contents of an instruction and an execution unit for executing is performed in response to an instruction based on an output from the decoder, the search instruction which identifies a desired data storage area from a plurality of data storage areas in the memory which includes an array data structure.
摘要翻译：响应于来自解码器的输出的指令，执行包括用于解码指令的内容的解码器和用于执行的执行单元的数据处理装置的存储器的方法，所述搜索指令识别期望的数据从存储器中的包括阵列数据结构的多个数据存储区域的存储区域。

4. 发明授权

US5398319A Microprocessor having apparatus for dynamically controlling a kind of operation to be performed by instructions to be executed 失效
标题翻译：微处理器具有用于动态地控制要执行的指令执行的操作种类的装置
公开(公告)号：US5398319A
公开(公告)日：1995-03-14
申请号：US943981
申请日：1992-09-11
申请人： Ken Sakamura , Ikuya Kawasaki , Atsushi Hasegawa , Kazuhiko Iwasaki , Motonobu Tonomura
发明人： Ken Sakamura , Ikuya Kawasaki , Atsushi Hasegawa , Kazuhiko Iwasaki , Motonobu Tonomura
IPC分类号： G06F9/305 , G06F7/00 , G06F9/30 , G06F9/308 , G06F9/318 , G06F9/34
CPC分类号： G06F9/30018 , G06F9/30181
摘要： A microprocessor including instruction decoding apparatus, instruction execution apparatus and information holding apparatus. The microprocessor performs a first step of storing information specifying the kind of operation to be performed by the instruction execution apparatus, upon execution of a first instruction, in the information holding apparatus and a second step of causing the instruction execution apparatus to perform the kind of operation specified by information stored in the information holding apparatus when a second instruction is decoded and includes information specifying that the operation to be performed by the instruction execution apparatus is the kind of operation specified by the information stored in the information holding apparatus.
摘要翻译：一种包括指令解码装置，指令执行装置和信息保存装置的微处理器。微处理器执行第一步骤，在执行第一指令时，在信息保持装置中存储指定由指令执行装置执行的操作种类的信息，以及使指令执行装置执行在第二指令被解码时存储在信息保持装置中的信息指定的操作包括指定由指令执行装置执行的操作是由存储在信息保持装置中的信息指定的操作的种类的信息。

5. 发明授权

US4941085A Data processing system having apparatus for increasing the execution speed of bit field instructions 失效
标题翻译：数据处理系统具有用于增加位字段指令的执行速度的装置
公开(公告)号：US4941085A
公开(公告)日：1990-07-10
申请号：US087308
申请日：1987-08-20
申请人： Ken Sakamura , Takuichiro Nakazawa , Atsushi Hasegawa , Ikuya Kawasaki , Kazuhiko Iwasaki
发明人： Ken Sakamura , Takuichiro Nakazawa , Atsushi Hasegawa , Ikuya Kawasaki , Kazuhiko Iwasaki
IPC分类号： G06F9/305 , G06F7/00 , G06F9/308 , G06F9/34 , G06F12/04
CPC分类号： G06F9/30018 , G06F9/30167
摘要： In addition to an ordinary bit field instruction without limitation which makes use of an offset value and a field width, a bit field instruction with limitation which does not calculate the spread of the bit field is separately installed. In the present invention the calculation for determination of the spread of the bit field is not performed when the bit field instruction with limitation is executed. In addition, when executing a bit field instruction with limitation, the offset value and the field width can be obtained directly as immediate values thereby decreasing the execution time of the instruction.
摘要翻译：除了使用偏移值和场宽的无限制的普通位字段指令之外，分别安装不计算位字段扩展的限制的位字段指令。在本发明中，当执行具有限制的位字段指令时，不执行用于确定位字段扩展的计算。此外，当执行限制的位字段指令时，可以直接获得偏移值和字段宽度作为立即值，从而减少指令的执行时间。

6. 发明授权

US5210835A Data processing system having apparatus for increasing the execution speed of bit field instructions 失效
标题翻译：数据处理系统具有用于增加位字段指令的执行速度的装置
公开(公告)号：US5210835A
公开(公告)日：1993-05-11
申请号：US460003
申请日：1990-01-02
申请人： Ken Sakamura , Takuichiro Nakazawa , Atsushi Hasegawa , Ikuya Kawasaki , Kazuhiko Iwasaki
发明人： Ken Sakamura , Takuichiro Nakazawa , Atsushi Hasegawa , Ikuya Kawasaki , Kazuhiko Iwasaki
IPC分类号： G06F9/308
CPC分类号： G06F9/30018 , G06F9/30167
摘要： In addition to an ordinary bit field instruction without limitation which makes use of an offset value and a field width, a bit field instruction with limitation which does not calculate the spread of the bit field is separately installed. In the present invention the calculation for determination of the spread of the bit field is not performed when the bit field instruction with limitation is executed. In addition, when executing a bit field instruction with limitation, the offset value and the field width can be obtained directly as immediate values thereby decreasing the execution time of the instruction.
摘要翻译：除了使用偏移值和场宽的无限制的普通位字段指令之外，分别安装不计算位字段扩展的限制的位字段指令。在本发明中，当执行具有限制的位字段指令时，不执行用于确定位字段扩展的计算。此外，当执行限制的位字段指令时，可以直接获得偏移值和字段宽度作为立即值，从而减少指令的执行时间。

7. 发明授权

US5193159A Microprocessor system 失效
标题翻译：微处理器系统
公开(公告)号：US5193159A
公开(公告)日：1993-03-09
申请号：US709783
申请日：1991-06-03
申请人： Kouzi Hashimoto , Atsushi Hasegawa , Ikuya Kawasaki , Kazuhiko Iwasaki
发明人： Kouzi Hashimoto , Atsushi Hasegawa , Ikuya Kawasaki , Kazuhiko Iwasaki
IPC分类号： G06F9/312 , G06F9/38
CPC分类号： G06F9/30043 , G06F9/3877
摘要： When a coprocessor communicates a plurality of data items with a master processor and a memory according to a bus access cycle activated by the master processor, the coprocessor is supplied therein with information indicating a data storage position as a data transfer source or destination. The master processor and coprocessor independently monitor the number of the sequence of data transfers or the end of the sequence of data transfer operations. As a consequence, when executing a sequence of plural data transfer operations, the coprocessor need not receive a command from the master processor for each data transfer thereto. Further, it is not required for the coprocessor to indicate the end of the sequence of data transfer cycles to the master processor since the master processor can determine this on its own.
摘要翻译：当协处理器根据由主处理器激活的总线访问周期与主处理器和存储器通信多个数据项时，协处理器在其中提供指示数据存储位置作为数据传送源或目的地的信息。主处理器和协处理器独立地监视数据传输序列的数量或数据传输操作序列的结束。因此，当执行多个数据传送操作的序列时，协处理器不需要从主处理器接收每次数据传送的命令。此外，协处理器不需要指示到主处理器的数据传送周期的结束，因为主处理器可以自己确定这一点。

8. 发明授权

US5125095A System using microprocessor address lines for coprocessor selection within a multi-coprocessor apparatus 失效
标题翻译：在多协处理器装置中使用微处理器地址线进行协处理器选择的系统
公开(公告)号：US5125095A
公开(公告)日：1992-06-23
申请号：US678906
申请日：1991-03-28
申请人： Takuichiro Nakazawa , Makoto Hanawa , Atsushi Hasegawa , Ikuya Kawasaki , Kazuhiko Iwasaki , Shigeki Morinaga , Hisashi Kaziwara , Takeshi Asai , Junichi Tatezaki
发明人： Takuichiro Nakazawa , Makoto Hanawa , Atsushi Hasegawa , Ikuya Kawasaki , Kazuhiko Iwasaki , Shigeki Morinaga , Hisashi Kaziwara , Takeshi Asai , Junichi Tatezaki
IPC分类号： G06F9/38 , G06F15/16 , G06F15/177
CPC分类号： G06F9/3877 , G06F9/3885
摘要： A microcomputer system has a microprocessor and a number of independent coprocessors for executing individual instructions according to instruction data sent from the microprocessor. An address bus and a data bus interconnect the coprocessors with the microprocessor. The microprocessor sends instruction data to the coprocessors via the data bus and concurrently sends coprocessor designation data to the coprocessors via the address bus. The coprocessor designated by the designation data reads and reacts to the instruction data while the other coprocessors within the system disregard the instruction data.
摘要翻译：微计算机系统具有微处理器和多个独立的协处理器，用于根据从微处理器发送的指令数据执行各个指令。地址总线和数据总线将协处理器与微处理器互连。微处理器通过数据总线向协处理器发送指令数据，同时通过地址总线向协处理器发送协处理器指定数据。由指定数据指定的协处理器读取并对指令数据进行响应，而系统内的其他协处理器忽略指令数据。

9. 发明授权

US5073856A Method of searching a queue in response to a search instruction 失效
标题翻译：在搜索引擎中搜索队列的方法
公开(公告)号：US5073856A
公开(公告)日：1991-12-17
申请号：US489240
申请日：1990-03-26
申请人： Ken Sakamura , Kouzi Hashimoto , Ikuya Kawasaki , Atsushi Hasegawa , Kazuhiko Iwasaki
发明人： Ken Sakamura , Kouzi Hashimoto , Ikuya Kawasaki , Atsushi Hasegawa , Kazuhiko Iwasaki
IPC分类号： G06F9/46 , G06F9/30 , G06F9/312 , G06F17/30
CPC分类号： G06F9/30043 , G06F17/30958 , Y10S707/99933
摘要： A method for searching the memory of a data processing apparatus including a decoder for decoding the contents of an instruction and an execution unit for executing the instruction based on an output from the decoder is performed in response to a search instruction which identifies a desired data storage area from a plurality of data storage areas in the memory which includes an array data structure.

10. 发明授权

US5778237A Data processor and single-chip microcomputer with changing clock frequency and operating voltage 失效
标题翻译：数据处理器和单片机具有时钟频率和工作电压的变化
公开(公告)号：US5778237A
公开(公告)日：1998-07-07
申请号：US572677
申请日：1995-12-14
申请人： Mitsuyoshi Yamamoto , Ikuya Kawasaki , Hideo Inayoshi , Susumu Narita , Masaharu Kubo
发明人： Mitsuyoshi Yamamoto , Ikuya Kawasaki , Hideo Inayoshi , Susumu Narita , Masaharu Kubo
IPC分类号： G06F1/32 , G06F1/00 , G06F1/18 , G06F1/26
CPC分类号： G06F1/324 , G06F1/32 , G06F1/3296 , Y02B60/1217 , Y02B60/1285
摘要： A microcomputer has a clock generator capable of changing the frequency of an output clock signal: and a power circuit capable of changing the level of an operating voltage to be outputted. The frequencies of clock signals and the levels of operating voltages to be individually fed to a plurality of circuit modules can be dynamically changed according to the content of a packaged register. If the content of the register instructs the reduction of the clock signal frequency and the operating voltage in its absolute value, the operating voltage is lowered in its absolute value prior to the change in the clock signal frequency. On the contrary, if the instruction is to increase the frequency of the clock signal and the operating voltage in its absolute value, the clock signal having the increased frequency is outputted prior to the increase of the operating voltage in the absolute value. As a result, it is possible to prevent in advance the malfunctions of the circuit at the time of switching the operation frequency and the operating voltage of the circuit module.
摘要翻译：微计算机具有能够改变输出时钟信号的频率的时钟发生器和能够改变要输出的工作电压的电平的电源电路。可以根据打包寄存器的内容来动态地改变要分别馈送到多个电路模块的时钟信号的频率和工作电压的电平。如果寄存器的内容指示将时钟信号频率和工作电压降低到其绝对值，则在时钟信号频率变化之前，工作电压以其绝对值降低。相反，如果指令是将时钟信号的频率和工作电压增加到绝对值，则在绝对值的工作电压增加之前输出具有增加的频率的时钟信号。结果，可以预先切换在切换电路模块的工作频率和工作电压时电路的故障。

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