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1. 发明授权

US5463504A Magnetic disk system and waveform equalizer therefor 失效
标题翻译：磁盘系统及其波形均衡器
公开(公告)号：US5463504A
公开(公告)日：1995-10-31
申请号：US62770
申请日：1993-05-18
申请人： Hiroshi Kimura , Shoichi Miyazawa , Ryutaro Horita , Kenichi Hase , Akihiko Hirano , Akira Uragami
发明人： Hiroshi Kimura , Shoichi Miyazawa , Ryutaro Horita , Kenichi Hase , Akihiko Hirano , Akira Uragami
IPC分类号： G11B5/012 , G11B5/09 , G11B20/10 , G11B20/12 , G11B20/14
CPC分类号： G11B20/10046 , G11B20/10009 , G11B20/10222 , G11B20/1403 , G11B5/012 , G11B5/09 , G11B20/1258
摘要： A magnetic disk system which records and reproduces data on a magnetic disk at different data transfer rates depending on a track position on the disk includes a transversal waveform equalizing circuit which implements an optimal waveform shaping for a readout waveform. The waveform equalizing circuit consists of a register, a frequency synthesizer, a PLL, and a transversal circuit. The transversal circuit consists of variable delay circuits, variable gain amplifiers, and an adder. The frequency synthesizer produces a write clock signal having a frequency which corresponds to a value stored in the register which depends on the data transfer rate, and the PLL responds to the write clock signal to produce a control signal by which the delay time of the transversal circuit is controlled. Consequently, the delay characteristic is not affected by disparity of circuit components of the transversal circuit, and the write clock frequency and the delay time of the transversal circuit can be set to intended values by merely changing the value stored in the register in response to a variation of the data transfer rate.
摘要翻译：根据磁盘上的轨道位置以不同的数据传输速率记录和再现磁盘上的数据的磁盘系统包括对读出波形实现最佳波形整形的横向波形均衡电路。波形均衡电路由寄存器，频率合成器，PLL和横向电路组成。横向电路由可变延迟电路，可变增益放大器和加法器组成。频率合成器产生具有对应于存储在寄存器中的取决于数据传输速率的值的频率的写时钟信号，并且PLL响应于写时钟信号以产生控制信号，通过该控制信号，横向延迟时间电路被控制。因此，延迟特性不受横向电路的电路部件的不均匀影响，并且横向电路的写入时钟频率和延迟时间可以通过仅响应于一个变化来改变存储在寄存器中的值来设置为预期值数据传输速率的变化。

2. 发明授权

US5475715A Sync data introduction method and system 失效
标题翻译：同步数据介绍方法和系统
公开(公告)号：US5475715A
公开(公告)日：1995-12-12
申请号：US886860
申请日：1992-05-22
申请人： Kenichi Hase , Syoichi Miyazawa , Ryutaro Horita , Akihiko Hirano , Hiroshi Kimura , Akira Uragami
发明人： Kenichi Hase , Syoichi Miyazawa , Ryutaro Horita , Akihiko Hirano , Hiroshi Kimura , Akira Uragami
IPC分类号： G11B20/10 , G11B20/14 , H04L1/00 , H04L7/00 , H04L7/033 , H04L7/08
CPC分类号： G11B20/1403 , H04L7/08 , H04L7/033
摘要： A data device for introducing the data read from a recording medium includes first creation device for receiving a read code signal corresponding to the data stored on a data recording medium to create first two phase signals which repeat inversion with a substantially equal period to each other on the basis of a change in the waveform of the read code; second creation device for receiving the first two phase signals to create second two phase signals with their one phase occupying most of their period having an overlapping portion with each other, the period being twice as long as that of the first two phase signals; and third creation device for receiving the read code signal and said second two phase signals to create a second code signal corresponding to the read code signal which shifts during the one phase period of said second two phase signals. The second two phase signals serve to extend sufficiently the window for introducing the read code to provide stabilized read for the data including jitter due to rotation fluctuation of the recording medium.
摘要翻译：用于引入从记录介质读取的数据的数据设备包括：第一创建设备，用于接收与存储在数据记录介质上的数据相对应的读取代码信号，以产生以两个相同周期重复反相的第一两个相位信号读取代码的波形变化的基础; 第二创建装置，用于接收前两个相位信号以产生第二两相信号，其相位占据其大部分周期具有彼此重叠的部分，该周期是前两个相位信号的两倍; 以及第三创建装置，用于接收读取代码信号和所述第二两个相位信号，以产生对应于在所述第二两个相位信号的一个相位周期期间移位的读取代码信号的第二代码信号。第二个两个相位信号充分地延伸用于引入读取代码的窗口，以提供包括由记录介质的旋转波动引起的抖动的数据的稳定读数。

3. 发明授权

US5636254A Signal processing delay circuit 失效
标题翻译：信号处理延迟电路
公开(公告)号：US5636254A
公开(公告)日：1997-06-03
申请号：US430534
申请日：1995-04-25
申请人： Kenichi Hase , Ryutaro Horita , Kunio Watanabe , Yoshiteru Ishida , Takashi Nara , Hiroshi Kimura
发明人： Kenichi Hase , Ryutaro Horita , Kunio Watanabe , Yoshiteru Ishida , Takashi Nara , Hiroshi Kimura
IPC分类号： G11B5/09 , G11B20/10 , G11B20/14 , H03H11/26 , H03H11/54 , H03K5/13 , H03K5/135 , H03L7/081 , H03L7/089 , H03L7/099 , H04L7/00 , H04L7/02
CPC分类号： H03L7/0805 , G11B20/10 , G11B20/1403 , H03K5/13 , H03L7/0812 , H03L7/0896 , H03L7/0995 , H04L7/02 , H04L7/0008 , H04L7/0041
摘要： A signal processing delay circuit is fabricated as a semiconductor integration circuit to cope with increase in the data transfer speed and data recording and reproducing density on a recording medium. In the delay circuit, the amount of delay of a reference delay circuit of a delay PLL is controlled to take a fixed value independent of deviation in quality of the semiconductor circuit, change in power, and alteration in temperature. A control signal supervising the delay amount of the reference delay circuit is employed to control amounts of delay of input signals supplied to a window adjustment delay circuit of a window adjustment circuit and a T/2 generation delay circuit generating a synchronizing signal. Each of these delay circuits includes an analog variable delay circuit having the same configuration. The window adjustment delay circuit is supervised by a signal obtained by weighting the control signal by a D/A converter. A data acquisition circuit and a data write circuit each include an analog variable delay circuit.
摘要翻译：制造信号处理延迟电路作为半导体积分电路，以应对数据传送速度的增加和记录介质上的数据记录和再现密度。在延迟电路中，延迟PLL的参考延迟电路的延迟量被控制为独立于半导体电路的质量偏差，功率变化和温度变化的固定值。采用监视参考延迟电路的延迟量的控制信号来控制提供给窗口调整电路的窗口调整延迟电路的输入信号的延迟量和产生同步信号的T / 2产生延迟电路。这些延迟电路中的每一个包括具有相同配置的模拟可变延迟电路。窗口调整延迟电路由通过D / A转换器对控制信号进行加权而获得的信号进行监视。数据采集电路和数据写入电路各自包括模拟可变延迟电路。

4. 发明授权

US5572163A Active filter control apparatus 失效
标题翻译：有源滤波器控制装置
公开(公告)号：US5572163A
公开(公告)日：1996-11-05
申请号：US362874
申请日：1994-12-23
申请人： Hiroshi Kimura , Ryutaro Horita , Kenichi Hase , Kunio Watanabe , Takashi Nara
发明人： Hiroshi Kimura , Ryutaro Horita , Kenichi Hase , Kunio Watanabe , Takashi Nara
IPC分类号： H03H11/04 , H03B5/00
CPC分类号： H03H11/0472 , H03H11/0433 , H03H2210/023
摘要： An active filter control apparatus for controlling or tuning an active filter having a variable cut-off frequency. The active filter control apparatus includes a control circuit for controlling or tuning the cut-off frequency of the active filter and a characteristic correction generator for generating a correction signal to correct a group delay characteristic of the active filter in accordance with a set cut-off frequency. The characteristic correction includes a correction signal generator for generating the correction signal in accordance with a set correction amount. The cut-off frequency controller controls tunes the characteristic of the active filter in accordance with the correction signal. Preferably, the apparatus is formed of a one-chip LSI integrated on one chip. The control apparatus can be utilized to control the speed in a recording/reproducing apparatus such as a optical disk drive or a magnetic tape drive apparatus.
摘要翻译：一种用于控制或调谐具有可变截止频率的有源滤波器的有源滤波器控制装置。有源滤波器控制装置包括用于控制或调谐有源滤波器的截止频率的控制电路和用于根据设定的截止产生校正信号校正有源滤波器的组延迟特性的特性校正发生器频率。特征校正包括用于根据设定的校正量产生校正信号的校正信号发生器。截止频率控制器根据校正信号控制有源滤波器的特性。优选地，该装置由集成在一个芯片上的单芯片LSI形成。控制装置可以用于控制诸如光盘驱动器或磁带驱动装置的记录/再现装置中的速度。

5. 发明授权

US5878097A Signal processing delay circuit 失效
标题翻译：信号处理延迟电路
公开(公告)号：US5878097A
公开(公告)日：1999-03-02
申请号：US865704
申请日：1997-05-30
申请人： Kenichi Hase , Ryutaro Horita , Kunio Watanabe , Yoshiteru Ishida , Takashi Nara , Hiroshi Kimura
发明人： Kenichi Hase , Ryutaro Horita , Kunio Watanabe , Yoshiteru Ishida , Takashi Nara , Hiroshi Kimura
IPC分类号： G11B5/09 , G11B20/10 , G11B20/14 , H03H11/26 , H03H11/54 , H03K5/13 , H03K5/135 , H03L7/081 , H03L7/089 , H03L7/099 , H04L7/00 , H04L7/02 , H04L25/36 , H04L25/40
CPC分类号： H03L7/0805 , G11B20/10 , G11B20/1403 , H03K5/13 , H03L7/0812 , H03L7/0896 , H03L7/0995 , H04L7/02 , H04L7/0008 , H04L7/0041
摘要： A signal processing delay circuit is fabricated as a semiconductor integration circuit to cope with increase in the data transfer speed and data recording and reproducing density on a recording medium. In the delay circuit, the amount of delay of a reference delay circuit of a delay PLL is controlled to take a fixed value independent of deviation in quality of the semiconductor circuit, change in power, and alteration in temperature. A control signal supervising the delay amount of the reference delay circuit is employed to control amounts of delay of input signals supplied to a window adjustment delay circuit of a window adjustment circuit and a T/2 generation delay circuit generating a synchronizing signal. Each of these delay circuits includes an analog variable delay circuit having the same configuration. The window adjustment delay circuit is supervised by a signal obtained by weighting the control signal by a D/A converter. A data acquisition circuit and a data write circuit each include an analog variable delay circuit.
摘要翻译：制造信号处理延迟电路作为半导体积分电路，以应对数据传送速度的增加和记录介质上的数据记录和再现密度。在延迟电路中，延迟PLL的参考延迟电路的延迟量被控制为独立于半导体电路的质量偏差，功率变化和温度变化的固定值。采用监视参考延迟电路的延迟量的控制信号来控制提供给窗口调整电路的窗口调整延迟电路的输入信号的延迟量和产生同步信号的T / 2产生延迟电路。这些延迟电路中的每一个包括具有相同配置的模拟可变延迟电路。窗口调整延迟电路由通过D / A转换器对控制信号进行加权而获得的信号进行监视。数据采集电路和数据写入电路各自包括模拟可变延迟电路。

6. 发明授权

US08819091B2 Information processing apparatus, information processing system, information recording medium, information processing method, and program 有权
标题翻译：信息处理装置，信息处理系统，信息记录介质，信息处理方法和程序
公开(公告)号：US08819091B2
公开(公告)日：2014-08-26
申请号：US12496020
申请日：2009-07-01
申请人： Tatsuya Inokuchi , Takahisa Ohgami , Goh Shimizu , Koichi Sotoyama , Satoshi Aida , Shizuka Watanabe , Yoshinori Ichikawa , Hiroshi Kimura
发明人： Tatsuya Inokuchi , Takahisa Ohgami , Goh Shimizu , Koichi Sotoyama , Satoshi Aida , Shizuka Watanabe , Yoshinori Ichikawa , Hiroshi Kimura
IPC分类号： G06F17/30 , G11B27/10
CPC分类号： G11B27/10 , G11B2220/2541 , G11B2220/2562
摘要： An information processing apparatus includes a communicating section that executes communication with a server, a local storage section that stores subsequent data acquired from the server, and a data processing section that executes an acquisition process of the subsequent data, and a data playback process using data stored on a disc and the subsequent data stored on the local storage section. The data processing section builds a virtual file system for reading data stored on the disc and the local storage section, at the time of the data playback process, and performs the acquisition process of the subsequent data by transmitting a package ID to the server at the time of the acquisition process of the subsequent data, the package ID being information specifying a package corresponding to a file set necessary for building or updating the virtual file system.
摘要翻译：信息处理装置包括执行与服务器的通信的通信部分，存储从服务器获取的后续数据的本地存储部分，以及执行后续数据的获取处理的数据处理部分，以及使用数据的数据重放处理存储在盘上以及存储在本地存储部分上的后续数据。在数据重放处理时，数据处理部分构建用于读取存储在盘上的数据和本地存储部分的虚拟文件系统，并且通过在服务器上发送包ID来执行后续数据的获取处理获取后续数据的时间，包ID是指定与构建或更新虚拟文件系统所需的文件集对应的包的信息。

7. 发明授权

US08743945B2 Shift register based downsampled floating tap decision feedback equalization 有权
标题翻译：基于移位寄存器的下采样浮点判定反馈均衡
公开(公告)号：US08743945B2
公开(公告)日：2014-06-03
申请号：US13540923
申请日：2012-07-03
申请人： Pervez M. Aziz , Hiroshi Kimura , Amaresh V. Malipatil , Hairong Gao
发明人： Pervez M. Aziz , Hiroshi Kimura , Amaresh V. Malipatil , Hairong Gao
IPC分类号： H03H7/30
CPC分类号： H04L25/14 , H04L25/03057 , H04L25/03885 , H04L2025/0349 , H04L2025/03579
摘要： Described embodiments receive a signal by a set of fixed taps and a set of floating taps of a receiver, each tap corresponding to a detected symbol. Each of the floating taps is stored in a corresponding shift register to account for process, operating voltage and temperature (PVT) variations of the receiver without calibration of delay elements. Multiplexing logic selects (i) corresponding floating taps for equalization by coupling selected floating taps to the outputs of the fixed taps, and (ii) different phases of each possible floating tap position. The multiplexing logic prunes and/or amalgamates the phases of each possible floating tap position and selects floating taps based on a magnitude of each phase. A combiner adjusts each output value of the fixed taps and the selected floating taps by a corresponding tap-weight, combines the adjusted values into an output signal and subtracts the output signal from the input signal.
摘要翻译：描述的实施例通过一组固定抽头和接收器的一组浮动抽头接收信号，每个抽头对应于检测到的符号。每个浮动抽头存储在相应的移位寄存器中，以解决接收器的过程，工作电压和温度（PVT）变化，而不校准延迟元件。多路复用逻辑通过将选定的浮动抽头耦合到固定抽头的输出端，选择（i）相应的浮动抽头进行均衡，以及（ii）每个可能的浮动抽头位置的不同相位。多路复用逻辑修剪和/或合并每个可能的浮动抽头位置的相位，并且基于每相的幅度选择浮动抽头。组合器通过相应的抽头调整固定抽头和所选浮动抽头的每个输出值，将调整后的值组合成输出信号，并从输入信号中减去输出信号。

8. 发明申请

US20130287605A1 ELECTRIC FAN 有权
标题翻译：电扇
公开(公告)号：US20130287605A1
公开(公告)日：2013-10-31
申请号：US13978786
申请日：2012-01-10
申请人： Hiroshi Kimura , Hiroki Masuyama , Keiichi Hosoi , Shinya Saito
发明人： Hiroshi Kimura , Hiroki Masuyama , Keiichi Hosoi , Shinya Saito
IPC分类号： F04B17/03
CPC分类号： F04B17/03 , F04D25/0613 , F04D29/083 , H02K5/10 , H02K7/14
摘要： This electric fan has a rotation shaft that is provided rotatably with respect to a stator, a rotor yoke provided on the rotation shaft and formed in a bottomed cylindrical shape so as to cover the stator from a front surface, and a bracket that fixes the stator to a fan shroud and is formed so as to cover a rear surface of the stator, with a fan body provided so as to integrally rotate with the rotation shaft and the rotor yoke. The fan body has a fan boss formed in a bottomed cylindrical shape so as to cover the rotor yoke from a front surface, and a plurality of blades that is provided protruding radially from an outer circumferential surface of the fan boss. A first labyrinth portion is provided between an opening portion of the fan boss and the fan shroud.
摘要翻译：该电动风扇具有相对于定子可旋转地设置的旋转轴，设置在旋转轴上并形成为有底圆筒形以便从前表面覆盖定子的转子轭，以及将定子形成为覆盖定子的后表面的风扇罩，其设置为与旋转轴和转子轭一体地旋转。风扇主体具有形成为有底圆筒形状的风扇凸起，以从前表面覆盖转子磁轭，以及从风扇凸台的外周表面径向设置的多个叶片。第一迷宫部分设置在风扇凸台的开口部分和风扇罩之间。

9. 发明申请

US20130249157A1 DEFORMABLE THIN OBJECT SPREADING DEVICE AND METHOD 有权
标题翻译：不可变薄的物体扩展装置和方法
公开(公告)号：US20130249157A1
公开(公告)日：2013-09-26
申请号：US13991066
申请日：2011-11-30
申请人： Yoshimasa Endo , Hiroshi Kitagawa , Hiroshi Kimura
发明人： Yoshimasa Endo , Hiroshi Kitagawa , Hiroshi Kimura
IPC分类号： B23Q3/18
CPC分类号： B23Q3/18 , B25J9/026 , B25J9/1679 , B25J15/0253 , D06F67/04 , G05B2219/39469 , G05B2219/39571 , G05B2219/40011 , G05B2219/40044 , Y10T29/49998
摘要： A deformable thin object spreading device and method are disclosed. The device includes a control part configured to: control a clamping unit and a moving mechanism to cause the clamping unit to clamp a first point of a deformable thin object; cause an endpoint detecting part to detect a first endpoint; control the clamping unit and the moving mechanism to cause the clamping unit to clamp the first endpoint; cause the endpoint detecting part to detect a second endpoint; control the clamping unit and the moving mechanism to cause the clamping unit to clamp both of the first endpoint and the second endpoint; cause the endpoint detecting part to detect a third endpoint; and control the clamping unit and the moving mechanism to cause the clamping unit to clamp both of the first endpoint or the second endpoint and the third endpoint of the deformable thin object.
摘要翻译：公开了一种可变形的薄物扩散装置和方法。该装置包括控制部件，该控制部件被构造成：控制夹紧单元和移动机构，以使夹紧单元夹紧可变形薄物体的第一点; 使端点检测部分检测第一端点; 控制夹紧单元和移动机构使夹紧单元夹紧第一端点; 使端点检测部分检测到第二端点; 控制夹紧单元和移动机构以使夹紧单元夹紧第一端点和第二端点; 使端点检测部分检测第三端点; 并且控制夹紧单元和移动机构以使夹紧单元夹紧可变形薄物体的第一端点或第二端点和第三端点。

10. 发明授权

US08236273B2 Method of producing pre-oxidation fiber and carbon fiber 有权
标题翻译：生产预氧化纤维和碳纤维的方法
公开(公告)号：US08236273B2
公开(公告)日：2012-08-07
申请号：US12747386
申请日：2008-12-10
申请人： Taro Oyama , Rie Kawahito , Hiroshi Kimura
发明人： Taro Oyama , Rie Kawahito , Hiroshi Kimura
IPC分类号： D01F9/12
CPC分类号： D01F9/225
摘要： There is disclosed a method of producing a pre-oxidation fiber in the production of the pre-oxidation fiber by subjecting a polyacrylic precursor fiber to pre-oxidation processing in an oxidizing atmosphere, including shrinking the precursor fiber as a pretreatment of pre-oxidation at a load of 0.58 g/tex or less in the temperature range of 220 to 260° C. under conditions in which the degree of cyclization (I1620/I2240) of the precursor fiber measured by a Fourier transform infrared spectrophotometer (FT-IR) does not exceed 7%, initially-drawing the precursor fiber at a load of 2.7 to 3.5 g/tex in an oxidizing atmosphere at 230 to 260° C. in the ranges of the degree of cyclization of not exceeding 27% and of the density of not exceeding 1.2 g/cm3, and then subjecting the pre-oxidation fiber to pre-oxidation treatment. A carbon fiber of high strength and high elasticity that is appropriate for composite materials that exhibit high composite performance is obtained by continuously subjecting this pre-oxidation fiber to carbonization treatment.
摘要翻译：公开了通过在氧化气氛中对聚丙烯酸前驱体纤维进行预氧化处理来制造预氧化纤维的方法，包括将前体纤维收缩为预氧化的预处理在通过傅立叶变换红外分光光度计（FT-IR）测量的前体纤维的环化度（I1620 / I2240）的条件下，在220〜260℃的温度范围内的负载为0.58g / tex以下不超过7％，首先在230〜260℃的氧化性气氛中，在2.7〜3.5g / tex的负荷下拉伸前体纤维，其环化度不超过27％，密度为不超过1.2g / cm 3，然后对预氧化纤维进行预氧化处理。通过对该预氧化纤维进行碳化处理，可以获得适用于复合性高的复合材料的高强度，高弹性的碳纤维。

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